| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
78 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
88 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo)
[all...] |
| LegalizeVectorOps.cpp | 286 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
293 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
408 // Bitcast the operands to be the same type as the mask.
411 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
412 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
421 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
|
| LegalizeVectorTypes.cpp | 50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
344 case ISD::BITCAST:
378 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
458 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
579 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
580 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
588 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
589 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
603 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo)
[all...] |
| SelectionDAGBuilder.cpp | 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
281 // Vector/Vector bitcast.
283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
294 // Trivial bitcast if the types are the same size and the destination
298 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
361 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val)
[all...] |
| LegalizeDAG.cpp | 311 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
434 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
[all...] |
| LegalizeFloatTypes.cpp | 59 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
584 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
697 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
[all...] |
| FastISel.cpp | 115 !(I->getOpcode() == Instruction::BitCast ||
726 // If the bitcast doesn't change the type, just use the operand value.
735 // Bitcasts of other values become reg-reg copies or BITCAST operators.
752 // First, try to perform the bitcast by inserting a reg-reg copy.
765 // If the reg-reg copy failed, select a BITCAST opcode.
768 ISD::BITCAST, Op0, Op0IsKill);
855 // Bitcast the value to integer, twiddle the sign bit with xor,
856 // and then bitcast it back to floating-point.
863 ISD::BITCAST, OpReg, OpRegIsKill);
875 ISD::BITCAST, IntResultReg, /*Kill=*/true)
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGDumper.cpp | 227 case ISD::BITCAST: return "bitcast";
|
| LegalizeTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
254 // make us bitcast between two vectors which are legalized in different ways.
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
763 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
[all...] |
| SelectionDAG.cpp | 113 if (N->getOpcode() == ISD::BITCAST)
163 if (N->getOpcode() == ISD::BITCAST)
[all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 357 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
358 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
359 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
360 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
687 DAG.getNode(ISD::BITCAST, dl, vecVT, result));
700 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones);
727 result = DAG.getNode(ISD::BITCAST, dl, vecVT,
[all...] |
| SPUISelDAGToDAG.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 417 // BITCAST - This operator converts between integer, vector and FP
424 BITCAST,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 330 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
331 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
[all...] |
| X86FastISel.cpp | 362 case Instruction::BitCast:
610 case Instruction::BitCast:
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 207 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
215 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
262 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
429 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
519 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
727 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
728 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| ARMFastISel.cpp | 793 case Instruction::BitCast: {
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 192 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
193 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
194 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
195 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 126 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
127 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
[all...] |
