| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 43 unsigned DestReg, unsigned SrcReg,
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
81 unsigned DestReg, int FI,
85 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
86 isARMLowRegister(DestReg))) && "Unknown regclass!");
89 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
90 isARMLowRegister(DestReg))) {
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| Thumb1InstrInfo.h | 44 unsigned DestReg, unsigned SrcReg,
54 unsigned DestReg, int FrameIndex,
|
| Thumb2RegisterInfo.h | 35 unsigned DestReg, unsigned SubIdx, int Val,
|
| Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx,
49 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| Thumb2InstrInfo.cpp | 114 unsigned DestReg, unsigned SrcReg,
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
153 unsigned DestReg, int FI,
169 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
174 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
179 unsigned DestReg, unsigned BaseReg, int NumBytes,
187 if (DestReg != ARM::SP && DestReg != BaseReg &
[all...] |
| Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx,
78 .addReg(DestReg, getDefRegState(true), SubIdx)
85 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
92 unsigned DestReg, unsigned BaseReg,
98 bool isHigh = !isARMLowRegister(DestReg) ||
109 unsigned LdReg = DestReg;
110 if (DestReg == ARM::SP) {
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
133 if (DestReg == ARM::SP || isSub)
165 /// a destreg = basereg + immediate in Thumb code
[all...] |
| Thumb2InstrInfo.h | 45 unsigned DestReg, unsigned SrcReg,
56 unsigned DestReg, int FrameIndex,
|
| ARMBaseInstrInfo.h | 111 unsigned DestReg, unsigned SrcReg,
122 unsigned DestReg, int FrameIndex,
136 unsigned DestReg, unsigned SubIdx,
357 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
361 unsigned DestReg, unsigned BaseReg, int NumBytes,
367 unsigned DestReg, unsigned BaseReg, int NumBytes,
372 unsigned DestReg, unsigned BaseReg,
|
| Thumb1RegisterInfo.h | 40 unsigned DestReg, unsigned SubIdx, int Val,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 87 int DestReg = MI->getOperand(0).getReg();
93 if (DestReg != SrcReg1) {
95 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
97 if (DestReg != SrcReg2) {
99 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
104 int DestReg = MI->getOperand(0).getReg();
109 DestReg).addReg(SrcReg1).addImm(Immed1);
111 DestReg).addReg(SrcReg1).addImm(Immed2);
|
| HexagonInstrInfo.h | 71 unsigned DestReg, unsigned SrcReg,
87 unsigned DestReg, int FrameIndex,
91 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 323 unsigned DestReg, unsigned SrcReg,
326 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
328 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
330 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
332 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
334 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
336 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
343 BuildMI(MBB, I, DL, MCID, DestReg)
346 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
522 unsigned DestReg, int FrameIdx
[all...] |
| PPCInstrInfo.h | 76 unsigned DestReg, int FrameIdx,
120 unsigned DestReg, unsigned SrcReg,
131 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 104 unsigned DestReg, unsigned SrcReg,
108 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
121 if (Mips::CCRRegClass.contains(DestReg))
123 else if (Mips::FGR32RegClass.contains(DestReg))
125 else if (DestReg == Mips::HI)
126 Opc = Mips::MTHI, DestReg = 0;
127 else if (DestReg == Mips::LO)
128 Opc = Mips::MTLO, DestReg = 0;
130 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
132 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)
[all...] |
| MipsInstrInfo.h | 81 unsigned DestReg, unsigned SrcReg,
91 unsigned DestReg, int FrameIndex,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 199 unsigned DestReg) {
201 .addReg(DestReg, RegState::Define);
212 unsigned DestReg) {
215 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
222 unsigned DestReg) {
225 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
232 unsigned DestReg) {
235 return BuildMI(BB, MII, DL, MCID, DestReg);
239 return BuildMI(BB, MII, DL, MCID, DestReg);
294 unsigned DestReg) {
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.h | 49 unsigned DestReg, unsigned SrcReg,
62 unsigned DestReg, int FrameIndex,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg,
68 unsigned DestReg, int FrameIdx,
|
| MSP430InstrInfo.cpp | 64 unsigned DestReg, int FrameIdx,
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
90 unsigned DestReg, unsigned SrcReg,
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 87 unsigned DestReg, unsigned SrcReg,
98 unsigned DestReg, int FrameIndex,
|
| SparcInstrInfo.cpp | 282 unsigned DestReg, unsigned SrcReg,
284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
321 unsigned DestReg, int FI,
328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
77 unsigned DestReg, int FrameIndex,
|
| XCoreInstrInfo.cpp | 336 unsigned DestReg, unsigned SrcReg,
338 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
353 if (DestReg == XCore::SP && GRSrc) {
378 unsigned DestReg, int FrameIndex,
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
|
| /external/llvm/lib/CodeGen/ |
| StrongPHIElimination.cpp | 243 unsigned DestReg = BBI->getOperand(0).getReg();
244 addReg(DestReg);
251 unionRegs(DestReg, SrcReg);
287 unsigned DestReg = BBI->getOperand(0).getReg();
288 addReg(DestReg);
293 unionRegs(DestReg, SrcReg);
317 unsigned DestReg = PHI->getOperand(0).getReg();
318 if (!InsertedDestCopies.count(DestReg))
319 MergeLIsAndRename(DestReg, NewReg);
340 unsigned DestReg = I->first
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 187 unsigned DestReg, unsigned SubIdx,
223 unsigned DestReg, unsigned SrcReg,
240 unsigned DestReg, int FrameIndex,
244 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
