| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 324 // Much like the scalar select and setcc, each bit in the condition selects
337 // SetCC operator - This evaluates to a true value iff the condition is
343 SETCC,
491 // compare, rather than as a combined SetCC node. The operands in order are
[all...] |
| SelectionDAG.h | 565 /// getSetCC - Helper function to make it easier to build SetCC's if you just
574 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 30 SETCC,
|
| HexagonISelDAGToDAG.cpp | 817 if (N0.getOpcode() == ISD::SETCC) {
826 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
850 // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
[all...] |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
189 case ISD::SETCC: return LowerSETCC(Op, DAG);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 196 case ISD::SETCC:
254 else if (Node->getOpcode() == ISD::SETCC)
486 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
|
| LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
287 // Turn it into a scalar SETCC.
288 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
314 // Turn it into a scalar SETCC.
315 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
470 case ISD::SETCC:
[all...] |
| LegalizeFloatTypes.cpp | 591 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
611 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
618 assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
675 default: llvm_unreachable("Do not know how to soften this setcc!");
686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT),
689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS,
[all...] |
| SelectionDAGDumper.cpp | 186 case ISD::SETCC: return "setcc";
283 default: llvm_unreachable("Unknown setcc condition!");
|
| LegalizeDAG.cpp | 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
748 case ISD::SETCC:
751 Node->getOpcode() == ISD::SETCC ? 2 : 1;
[all...] |
| DAGCombiner.cpp | 530 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
531 // that selects between the values 1 and 0, making it equivalent to a setcc.
537 if (N.getOpcode() == ISD::SETCC) {
556 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| TargetLowering.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
494 // Promote all the way up to the canonical SetCC type.
524 // Get the SETCC result using the canonical SETCC type.
525 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
530 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
[all...] |
| SelectionDAG.cpp | 233 /// 'op' is a valid SetCC operation.
253 default: llvm_unreachable("Illegal integer setcc operation!");
274 // Cannot fold a signed integer setcc with an unsigned integer setcc.
284 // Canonicalize illegal integer setcc's.
298 // Cannot fold a signed setcc with an unsigned setcc.
304 // Canonicalize illegal integer setcc's.
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 81 // select_cc => setcc
98 // customise setcc to use bitwise logic if possible
100 //setOperationAction(ISD::SETCC, MVT::i1, Custom);
101 setOperationAction(ISD::SETCC, MVT::i1, Legal);
120 case ISD::SETCC:
155 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
180 llvm_unreachable("setcc was not matched by a pattern!");
182 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
444 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
452 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
[all...] |
| X86ISelLowering.h | 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
91 SETCC,
93 // Same as SETCC except it's materialized with a sbb and the value is all
97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
507 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 319 setOperationAction(ISD::SETCC, MVT::i8, Legal);
320 setOperationAction(ISD::SETCC, MVT::i16, Legal);
321 setOperationAction(ISD::SETCC, MVT::i32, Legal);
322 setOperationAction(ISD::SETCC, MVT::i64, Legal);
323 setOperationAction(ISD::SETCC, MVT::f64, Custom);
511 // Return the Cell SPU's SETCC result type
515 // i8, i16 and i32 are valid SETCC result types
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 730 // Sparc has no select or setcc: expand to SELECT_CC.
734 setOperationAction(ISD::SETCC, MVT::i32, Expand);
735 setOperationAction(ISD::SETCC, MVT::f32, Expand);
736 setOperationAction(ISD::SETCC, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 94 // setcc operations results (slt, sgt, ...).
125 // Used by legalize types to correctly generate the setcc result.
126 // Without this, every float setcc comes with a AND/OR with the result,
129 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
140 setOperationAction(ISD::SETCC, MVT::f32, Custom);
141 setOperationAction(ISD::SETCC, MVT::f64, Custom);
545 // Creates and returns an FPCmp node from a setcc node.
546 // Returns Op if setcc is not a floating point comparison.
548 // must be a SETCC node
549 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 60 // setcc operations results (slt, sgt, ...).
138 // Used by legalize types to correctly generate the setcc result.
139 // Without this, every float setcc comes with a AND/OR with the result,
142 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
364 // setcc r1, r2, r3
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 572 /// associated with the SetCC condition, and whether or not the field is
615 // We can codegen setcc op, imm very efficiently compared to a brcond.
617 // setcc op, 0
647 } else if (Imm == ~0U) { // setcc op, -1
817 case ISD::SETCC:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 106 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
488 // FIXME: Code duplication: SETCC has custom operation action, see
490 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
533 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
534 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
[all...] |
