| /external/expat/bcb5/ |
| expat_static.mak | 147 .PATH.RC = $(PATHRC)
183 .rc.res:
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| expatw.mak | 147 .PATH.RC = $(PATHRC)
181 .rc.res:
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| expatw_static.mak | 148 .PATH.RC = $(PATHRC)
184 .rc.res:
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| outline.mak | 146 .PATH.RC = $(PATHRC)
180 .rc.res:
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| xmlwf.mak | 147 .PATH.RC = $(PATHRC)
181 .rc.res:
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| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 129 const TargetRegisterClass *const RC;
148 ExeDepsFix(const TargetRegisterClass *rc)
149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
471 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
647 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
650 << RC->getName() << " **********\n");
655 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end()
[all...] |
| PrologEpilogInserter.cpp | 248 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
265 unsigned Align = RC->getAlignment();
272 FrameIdx = MFI->CreateStackObject(RC->getSize(), Align, true);
277 FrameIdx = MFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset, true);
316 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
318 CSI[i].getFrameIdx(), RC, TRI);
343 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
346 RC, TRI);
391 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
395 RC, TRI)
[all...] |
| RegAllocFast.cpp | 150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
185 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
192 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
193 RC->getAlignment());
275 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
276 int FI = getStackSpaceFor(LRI->VirtReg, RC);
278 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
512 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
516 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
532 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
[all...] |
| StrongPHIElimination.cpp | 689 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
690 CopyReg = MRI->createVirtualRegister(RC);
761 const TargetRegisterClass *RC = MRI->getRegClass(DestReg);
762 unsigned CopyReg = MRI->createVirtualRegister(RC);
|
| TailDuplication.cpp | 387 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
392 unsigned NewDef = MRI->createVirtualRegister(RC);
424 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
425 unsigned NewReg = MRI->createVirtualRegister(RC);
[all...] |
| MachineInstr.cpp | [all...] |
| MachineLICM.cpp | 782 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
783 EVT VT = *RC->vt_begin();
785 RCId = RC->getID();
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 570 const TargetRegisterClass *RC =
572 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
574 // If cross copy register class is the same as RC, then it must be
576 // If cross copy register class is not the same as RC, then it's
582 if (DestRC != RC) {
591 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 482 const TargetRegisterClass *RC =
484 unsigned CountReg = MF->getRegInfo().createVirtualRegister(RC);
489 CountReg = MF->getRegInfo().createVirtualRegister(RC);
|
| HexagonInstrInfo.cpp | 358 const TargetRegisterClass *RC,
373 if (Hexagon::IntRegsRegisterClass->hasSubClassEq(RC)) {
377 } else if (Hexagon::DoubleRegsRegisterClass->hasSubClassEq(RC)) {
381 } else if (Hexagon::PredRegsRegisterClass->hasSubClassEq(RC)) {
395 const TargetRegisterClass *RC,
405 const TargetRegisterClass *RC,
419 if (RC == Hexagon::IntRegsRegisterClass) {
422 } else if (RC == Hexagon::DoubleRegsRegisterClass) {
425 } else if (RC == Hexagon::PredRegsRegisterClass) {
436 const TargetRegisterClass *RC,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 135 const TargetRegisterClass *RC;
136 RC = Subtarget.isABI_N64() ?
139 V0 = RegInfo.createVirtualRegister(RC);
140 V1 = RegInfo.createVirtualRegister(RC);
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 130 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
133 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
134 const CodeGenRegister::Set &Regs = RC.getMembers();
139 RC.buildRegUnitSet(RegUnits);
143 OS << "}, \t// " << RC.getName() << "\n";
146 << " return RCWeightTable[RC->getID()];\n"
172 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
192 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
535 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
[all...] |
| DAGISelMatcherGen.cpp | 31 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
32 const CodeGenRegisterClass &RC = *RCs[rc];
33 if (!RC.contains(Reg))
38 VT = RC.getValueTypeNum(0);
43 assert(VT == RC.getValueTypeNum(0));
[all...] |
| /frameworks/av/media/libstagefright/rtsp/ |
| ARTPConnection.cpp | 597 size_t RC = data[0] & 0x1f;
599 if (size < (7 + RC * 6) * 4) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 429 // addic RC, R0, 0
430 // bneid RC, start
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 779 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
780 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
781 RC->getAlignment(),
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 195 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
196 assert(RC && "This value type is not natively supported!");
197 return RC;
207 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
208 return RC;
[all...] |
| /external/llvm/lib/Analysis/ |
| ScalarEvolution.cpp | 532 const SCEVConstant *RC = cast<SCEVConstant>(RHS);
536 const APInt &RA = RC->getValue()->getValue();
576 const SCEVNAryExpr *RC = cast<SCEVNAryExpr>(RHS);
579 unsigned LNumOps = LC->getNumOperands(), RNumOps = RC->getNumOperands();
583 long X = compare(LC->getOperand(i), RC->getOperand(i));
592 const SCEVUDivExpr *RC = cast<SCEVUDivExpr>(RHS);
595 long X = compare(LC->getLHS(), RC->getLHS());
598 return compare(LC->getRHS(), RC->getRHS());
605 const SCEVCastExpr *RC = cast<SCEVCastExpr>(RHS);
608 return compare(LC->getOperand(), RC->getOperand())
[all...] |
