| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.td | [all...] |
| ARMInstrInfo.cpp | 47 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
48 switch (Opc) {
|
| Thumb2InstrInfo.h | 33 // Return the non-pre/post incrementing version of 'Opc'. Return 0
35 unsigned getUnindexedOpcode(unsigned Opc) const;
|
| Thumb2InstrInfo.cpp | 43 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
226 unsigned Opc = 0;
240 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
241 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
248 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
261 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
265 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
280 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
610 unsigned Opc = MI->getOpcode();
611 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc
[all...] |
| Thumb2SizeReduction.cpp | 295 unsigned Opc = MI->getOpcode();
296 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
297 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
298 Opc == ARM::t2LDMDB_UPD);
299 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
315 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)
[all...] |
| ARMLoadStoreOptimizer.cpp | 262 static bool isT2i32Load(unsigned Opc) {
263 return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
266 static bool isi32Load(unsigned Opc) {
267 return Opc == ARM::LDRi12 || isT2i32Load(Opc);
270 static bool isT2i32Store(unsigned Opc) {
271 return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8;
274 static bool isi32Store(unsigned Opc) {
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrFormats.td | 257 class RI10_Int_v8i16<bits<8> opcode, string opc, InstrItinClass itin,
260 !strconcat(opc, " $rT, $rA, $val"), itin,
264 class RI10_Int_v4i32<bits<8> opcode, string opc, InstrItinClass itin,
267 !strconcat(opc, " $rT, $rA, $val"), itin,
272 class RR_Int_v8i16<bits<11> opcode, string opc, InstrItinClass itin,
275 !strconcat(opc, " $rT, $rA, $rB"), itin,
280 class RR_Int_v4i32<bits<11> opcode, string opc, InstrItinClass itin,
283 !strconcat(opc, " $rT, $rA, $rB"), itin,
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.h | 144 inline static bool isUncondBranchOpcode(int Opc) {
145 switch (Opc) {
155 inline static bool isCondBranchOpcode(int Opc) {
156 switch (Opc) {
|
| /external/llvm/utils/TableGen/ |
| FixedLenDecoderEmitter.cpp | 330 void SingletonExists(unsigned Opc) const;
348 unsigned Opc) const;
351 unsigned Opc) const;
356 unsigned Opc) const;
672 void FilterChooser::SingletonExists(unsigned Opc) const {
674 insnWithID(Insn0, Opc);
676 errs() << "Singleton exists: " << nameWithID(Opc)
679 if (Opcodes[i] == Opc) continue;
794 unsigned Opc) const {
796 AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates")
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 84 int Opc = MI->getOpcode();
85 if (Opc == Hexagon::TFR_condset_rr) {
103 } else if (Opc == Hexagon::TFR_condset_ii) {
|
| HexagonExpandPredSpillCode.cpp | 76 int Opc = MI->getOpcode();
77 if (Opc == Hexagon::STriw_pred) {
119 } else if (Opc == Hexagon::LDriw_pred) {
|
| /external/qemu/tcg/hppa/ |
| tcg-target.c | 954 int addr_reg, int addend_reg, int opc)
962 switch (opc) {
1020 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1024 int datahi_reg = (opc == 3 ? *args++ : TCG_REG_R0);
[all...] |
| /external/llvm/docs/ |
| TableGenFundamentals.html | 659 <b>class</b> inst<<b>int</b> opc, <b>string</b> asmstr, <b>dag</b> operandlist>;
661 <b>multiclass</b> ri_inst<<b>int</b> opc, <b>string</b> asmstr> {
662 def _rr : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
664 def _ri : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
688 <b>class</b> inst<<b>int</b> opc, <b>string</b> asmstr, <b>dag</b> operandlist>;
690 <b>class</b> rrinst<<b>int</b> opc, <b>string</b> asmstr>
691 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
694 <b>class</b> riinst<<b>int</b> opc, <b>string</b> asmstr>
695 : inst<opc, !strconcat(asmstr, " $dst, $src1, $src2"),
716 <b>class</b> Instruction<bits<4> opc, string Name>
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 304 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
305 return N->getOpcode() == Opc
448 unsigned Opc;
477 Opc = PPC::CMPLW;
482 Opc = PPC::CMPLW;
489 Opc = PPC::CMPW;
520 Opc = PPC::CMPLD;
525 Opc = PPC::CMPLD;
532 Opc = PPC::CMPD;
535 Opc = PPC::FCMPUS
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 300 #define OPCD(opc) ((opc)<<26)
301 #define XO31(opc) (OPCD(31)|((opc)<<1))
302 #define XO19(opc) (OPCD(19)|((opc)<<1))
527 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
539 if (opc == 3)
548 s_bits = opc & 3;
603 switch (opc) {
[all...] |
| /external/qemu/tcg/sparc/ |
| tcg-target.c | 471 static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
478 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
482 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
487 static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
494 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
499 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
749 int opc)
759 s_bits = opc & 3;
819 switch(opc) {
892 switch(opc) {
[all...] |
| /external/wpa_supplicant_6/wpa_supplicant/src/hlr_auc_gw/ |
| hlr_auc_gw.c | 67 /* OPc and AMF parameters for Milenage (Example algorithms for AKA). */
72 u8 opc[16]; member in struct:milenage_parameters
271 /* Parse IMSI Ki OPc AMF SQN */
323 /* OPc */
326 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
331 if (strlen(pos) != 32 || hexstr2bin(pos, m->opc, 16)) {
332 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
423 gsm_milenage(m->opc, m->ki, _rand, sres, kc);
491 milenage_generate(m->opc, m->amf, m->ki, m->sqn, _rand,
564 if (milenage_auts(m->opc, m->ki, _rand, _auts, sqn))
[all...] |
| /external/wpa_supplicant_8/hostapd/ |
| hlr_auc_gw.c | 62 /* OPc and AMF parameters for Milenage (Example algorithms for AKA). */
67 u8 opc[16]; member in struct:milenage_parameters
266 /* Parse IMSI Ki OPc AMF SQN */
318 /* OPc */
321 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
326 if (strlen(pos) != 32 || hexstr2bin(pos, m->opc, 16)) {
327 printf("%s:%d - Invalid OPc (%s)\n", fname, line, pos);
418 gsm_milenage(m->opc, m->ki, _rand, sres, kc);
486 milenage_generate(m->opc, m->amf, m->ki, m->sqn, _rand,
559 if (milenage_auts(m->opc, m->ki, _rand, _auts, sqn))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 677 SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops,
679 : NodeType(Opc), OperandsNeedDelete(true), HasDebugValue(false),
694 SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs)
695 : NodeType(Opc), OperandsNeedDelete(false), HasDebugValue(false),
830 UnarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X)
831 : SDNode(Opc, dl, VTs) {
841 BinarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y)
842 : SDNode(Opc, dl, VTs) {
852 TernarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y,
854 : SDNode(Opc, dl, VTs)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 92 unsigned Opc;
94 Opc = MSP430::MOV16rr;
96 Opc = MSP430::MOV8rr;
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| /external/clang/lib/Sema/ |
| SemaExpr.cpp | [all...] |
| /external/clang/include/clang/AST/ |
| Expr.h | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 47 default: llvm_unreachable("Unknown shift opc!");
58 default: llvm_unreachable("Unknown shift opc!");
108 // This is stored three operands [rega, regb, opc]. The first is the base
407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
410 bool isSub = Opc == sub;
441 /// getAM3Opc - This function encodes the addrmode3 opc field.
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
444 bool isSub = Opc == sub;
491 /// getAM5Opc - This function encodes the addrmode5 opc field.
492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
[all...] |
| /external/qemu/target-mips/ |
| translate.c | [all...] |
| /external/libpcap/ |
| tokdefs.h | 127 OPC = 353,
231 #define OPC 353
|
