HomeSort by relevance Sort by last modified time
    Searched refs:SHL (Results 26 - 50 of 79) sorted by null

12 3 4

  /external/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp     [all...]
FastISel.cpp     [all...]
LegalizeVectorOps.cpp 183 case ISD::SHL:
441 // Notice that we can also use SHL+SHR, but using a constant is slightly
SelectionDAGBuilder.h 495 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
SelectionDAGDumper.cpp 170 case ISD::SHL: return "shl";
LegalizeFloatTypes.cpp 186 SDValue SignBit = DAG.getNode(ISD::SHL, dl, RVT, DAG.getConstant(1, RVT),
200 SignBit = DAG.getNode(ISD::SHL, dl, LVT, SignBit,
206 SDValue Mask = DAG.getNode(ISD::SHL, dl, LVT, DAG.getConstant(1, LVT),
    [all...]
SelectionDAG.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsISelLowering.cpp 656 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
674 // See if Op's second operand matches (and (shl $src, pos), mask1).
686 SDValue Shl = And1.getOperand(0);
687 if (Shl.getOpcode() != ISD::SHL)
690 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
701 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.h 91 SRL, SRA, SHL,
PPCISelLowering.cpp 296 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
483 case PPCISD::SHL: return "PPCISD::SHL";
    [all...]
  /external/v8/src/
builtins.h 240 V(SHL, 1) \
ast.cc 140 case Token::ASSIGN_SHL: return Token::SHL;
295 case Token::SHL:
    [all...]
ic.cc     [all...]
  /external/v8/src/ia32/
code-stubs-ia32.cc 734 __ shl(scratch2, big_shift_distance);
775 __ shl(scratch, shift_distance);
    [all...]
  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp 472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
    [all...]
X86ISelDAGToDAG.cpp 765 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
777 InsertDAGNode(DAG, N, Shl);
778 DAG.ReplaceAllUsesWith(N, Shl);
791 if (Shift.getOpcode() != ISD::SHL ||
810 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
829 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
830 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
    [all...]
  /prebuilts/tools/common/asm-tools/
asm-commons-4.0.jar 
  /external/openssl/crypto/bn/asm/
ppc.pl 120 $SHL= "slw"; # shift left
144 $SHL= "sld"; # shift left
    [all...]
  /external/llvm/lib/Target/CellSPU/
SPUISelLowering.cpp 240 setOperationAction(ISD::SHL, MVT::i8, Custom);
245 setOperationAction(ISD::SHL, MVT::i64, Legal);
395 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
450 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
    [all...]
  /dalvik/dx/src/com/android/dx/cf/code/
RopperMachine.java 811 return RegOps.SHL;
    [all...]
  /external/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 346 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
367 Base.getOperand(1).getOpcode() == ISD::SHL) {
434 // shl high_shifted, high, 32 - (offset & 0x3) * 8
451 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
470 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
    [all...]
  /external/llvm/lib/TableGen/
Record.cpp 942 case SHL:
952 case SHL: Result = LHSv << RHSv; break;
977 case SHL: Result = "!shl"; break;
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMISelLowering.cpp 128 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
547 setTargetDAGCombine(ISD::SHL);
    [all...]
  /external/v8/src/arm/
lithium-arm.cc 185 case Token::SHL: return "shl-t";
    [all...]

Completed in 2298 milliseconds

12 3 4