| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 108 .addReg(MBlaze::R1).addImm(-Amount);
112 .addReg(MBlaze::R1).addImm(Amount);
|
| MBlazeInstrInfo.cpp | 99 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
109 .addFrameIndex(FI).addImm(0); //.addFrameIndex(FI);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
102 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
|
| DelaySlotFiller.cpp | 122 TII->get(SP::UNIMP)).addImm(structSize);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 560 .addImm(ExtraInfo);
621 .addReg(Reg, RegState::Debug).addImm(Offset)
638 .addReg(0U).addImm(DI->getOffset())
643 .addCImm(CI).addImm(DI->getOffset())
647 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
651 .addFPImm(CF).addImm(DI->getOffset())
655 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 99 .addReg(MSP430::SPW).addImm(NumBytes);
162 .addReg(MSP430::SPW).addImm(CSSize);
171 .addReg(MSP430::SPW).addImm(NumBytes);
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| MSP430BranchSelector.cpp | 156 .addImm(4).addOperand(Cond[0]);
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 242 .addImm(SignExtend64<16>(Inst->ImmOpnd));
245 .addImm(SignExtend64<16>(Inst->ImmOpnd));
250 .addImm(SignExtend64<16>(Inst->ImmOpnd));
|
| MipsInstrInfo.cpp | 205 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
231 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
240 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
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| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 218 .addFrameIndex(FramePtrSpillFI).addImm(0)
293 .addImm(MaxAlign-1)));
306 .addImm(MaxAlign-1)));
324 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
404 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
446 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
626 .addImm(-4);
704 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
706 MIB.addImm(4);
765 .addImm(8 * NumAlignedDPRCS2Regs)))
[all...] |
| ARMFastISel.cpp | 373 .addImm(Imm));
377 .addImm(Imm));
419 .addImm(Imm));
424 .addImm(Imm));
440 .addImm(Imm));
443 .addImm(Imm));
459 .addImm(Imm1).addImm(Imm2));
462 .addImm(Imm1).addImm(Imm2))
[all...] |
| Thumb1RegisterInfo.cpp | 79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
117 .addImm(NumBytes).setMIFlags(MIFlags);
120 .addImm(NumBytes).setMIFlags(MIFlags);
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
263 MIB.addReg(DestReg).addImm(ThisVal);
271 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
293 .addImm(((unsigned)NumBytes) & 3)
355 .addImm(ThisVal));
432 .addImm(Offset / Scale));
460 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask))
[all...] |
| ARMLoadStoreOptimizer.cpp | 339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
340 .addImm(Pred).addReg(PredReg).addReg(0);
351 .addImm(Pred).addReg(PredReg);
782 .addImm(Pred).addReg(PredReg);
935 .addImm(Pred).addReg(PredReg)
945 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
950 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
[all...] |
| MLxExpansionPass.cpp | 229 MIB.addImm(LaneImm);
230 MIB.addImm(Pred).addReg(PredReg);
242 MIB.addImm(Pred).addReg(PredReg);
|
| ARMBaseInstrInfo.cpp | 170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
183 .addImm(Pred).addReg(0).addReg(0);
193 .addReg(BaseReg).addImm(Amt)
194 .addImm(Pred).addReg(0).addReg(0);
199 .addImm(Pred).addReg(0).addReg(0);
209 .addReg(WBReg).addImm(0).addImm(Pred)
[all...] |
| Thumb2ITBlockPass.cpp | 186 .addImm(CC);
236 MIB.addImm(Mask);
|
| ARMConstantIslandPass.cpp | 559 .addImm(i).addConstantPoolIndex(i).addImm(Size);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 191 .addImm(ThisVal);
697 .addImm(-TailCallReturnAddrDelta)
791 .addImm(-MaxAlign)
881 .addImm(NumBytes)
887 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 164 .addImm((ME+1) & 31)
165 .addImm((MB-1) & 31);
310 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
316 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
431 .addReg(ScratchReg).addImm(ShiftBits)
432 .addImm(0).addImm(31));
573 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
574 .addImm(31))
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 282 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
284 .addMBB(FBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
288 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
292 .addMBB(TBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 74 /// addImm - Add a new immediate operand.
76 const MachineInstrBuilder &addImm(int64_t Val) const {
177 return addImm(Disp.getImm() + off);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 336 Hexagon::subreg_hireg))).addImm(0);
342 Hexagon::subreg_hireg))).addImm(0);
375 .addFrameIndex(FI).addImm(0)
379 .addFrameIndex(FI).addImm(0)
383 .addFrameIndex(FI).addImm(0)
421 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
424 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
427 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
[all...] |
