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  /external/llvm/test/TableGen/
DefmInsideMultiClass.td 4 class Instruction<bits<4> opc, string Name> {
5 bits<4> opcode = opc;
9 multiclass basic_r<bits<4> opc> {
10 def rr : Instruction<opc, "rr">;
11 def rm : Instruction<opc, "rm">;
14 multiclass basic_s<bits<4> opc> {
15 defm SS : basic_r<opc>;
16 defm SD : basic_r<opc>;
19 multiclass basic_p<bits<4> opc> {
20 defm PS : basic_r<opc>;
    [all...]
LetInsideMultiClasses.td 4 class Instruction<bits<4> opc, string Name> {
5 bits<4> opcode = opc;
10 multiclass basic_r<bits<4> opc> {
12 def rr : Instruction<opc, "rr">;
13 def rm : Instruction<opc, "rm">;
17 def rx : Instruction<opc, "rx">;
20 multiclass basic_ss<bits<4> opc> {
22 defm SS : basic_r<opc>;
25 defm SD : basic_r<opc>;
  /external/webkit/Source/JavaScriptCore/assembler/
SH4Assembler.h 220 inline uint16_t getOpcodeGroup1(uint16_t opc, int rm, int rn)
222 return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4));
225 inline uint16_t getOpcodeGroup2(uint16_t opc, int rm)
227 return (opc | ((rm & 0xf) << 8));
230 inline uint16_t getOpcodeGroup3(uint16_t opc, int rm, int rn)
232 return (opc | ((rm & 0xf) << 8) | (rn & 0xff));
235 inline uint16_t getOpcodeGroup4(uint16_t opc, int rm, int rn, int offset)
237 return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4) | (offset & 0xf));
240 inline uint16_t getOpcodeGroup5(uint16_t opc, int rm)
242 return (opc | (rm & 0xff))
446 uint16_t opc = getOpcodeGroup2(MOVT_OPCODE, dst); local
454 uint16_t opc = getOpcodeGroup1(ADD_OPCODE, dst, src); local
460 uint16_t opc = getOpcodeGroup1(ADDC_OPCODE, dst, src); local
466 uint16_t opc = getOpcodeGroup1(ADDV_OPCODE, dst, src); local
474 uint16_t opc = getOpcodeGroup3(ADDIMM_OPCODE, dst, imm8); local
480 uint16_t opc = getOpcodeGroup1(AND_OPCODE, dst, src); local
489 uint16_t opc = getOpcodeGroup5(ANDIMM_OPCODE, imm8); local
495 uint16_t opc = getOpcodeGroup1(DIV1_OPCODE, dst, src); local
501 uint16_t opc = getOpcodeGroup1(DIV0_OPCODE, dst, src); local
507 uint16_t opc = getOpcodeGroup1(NOT_OPCODE, dst, src); local
513 uint16_t opc = getOpcodeGroup1(OR_OPCODE, dst, src); local
522 uint16_t opc = getOpcodeGroup5(ORIMM_OPCODE, imm8); local
528 uint16_t opc = getOpcodeGroup1(SUB_OPCODE, dst, src); local
534 uint16_t opc = getOpcodeGroup1(SUBV_OPCODE, dst, src); local
540 uint16_t opc = getOpcodeGroup1(XOR_OPCODE, dst, src); local
549 uint16_t opc = getOpcodeGroup5(XORIMM_OPCODE, imm8); local
575 uint16_t opc = getOpcodeGroup1(NEG_OPCODE, dst, src); local
581 uint16_t opc = getOpcodeGroup1(SHLD_OPCODE, dst, rShift); local
599 uint16_t opc = getOpcodeGroup1(SHAD_OPCODE, dst, rShift); local
625 uint16_t opc = getOpcodeGroup1(MULL_OPCODE, dst, src); local
631 uint16_t opc = getOpcodeGroup1(DMULL_L_OPCODE, dst, src); local
637 uint16_t opc = getOpcodeGroup1(DMULSL_OPCODE, dst, src); local
643 uint16_t opc = getOpcodeGroup2(STSMACL_OPCODE, reg); local
649 uint16_t opc = getOpcodeGroup2(STSMACH_OPCODE, reg); local
695 uint16_t opc = getOpcodeGroup2(CMPPL_OPCODE, reg); local
701 uint16_t opc = getOpcodeGroup2(CMPPZ_OPCODE, reg); local
707 uint16_t opc = getOpcodeGroup5(CMPEQIMM_OPCODE, imm); local
713 uint16_t opc = getOpcodeGroup1(TST_OPCODE, dst, src); local
721 uint16_t opc = getOpcodeGroup5(TSTIMM_OPCODE, imm); local
792 uint16_t opc = getOpcodeGroup2(LDSPR_OPCODE, reg); local
798 uint16_t opc = getOpcodeGroup2(STSPR_OPCODE, reg); local
804 uint16_t opc = getOpcodeGroup1(EXTUW_OPCODE, dst, src); local
812 uint16_t opc = getOpcodeGroup2(LDS_RM_FPUL_OPCODE, src); local
818 uint16_t opc = getOpcodeGroup2(FNEG_OPCODE, dst); local
824 uint16_t opc = getOpcodeGroup2(FSQRT_OPCODE, dst); local
830 uint16_t opc = getOpcodeGroup2(STS_FPUL_RN_OPCODE, src); local
836 uint16_t opc = getOpcodeGroup2(FLOAT_OPCODE, src); local
842 uint16_t opc = getOpcodeGroup1(FMUL_OPCODE, dst, src); local
848 uint16_t opc = getOpcodeGroup1(FMOVS_READ_RM_OPCODE, dst, src); local
854 uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_RN_OPCODE, dst, src); local
860 uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_R0RN_OPCODE, dst, src); local
866 uint16_t opc = getOpcodeGroup1(FMOVS_READ_R0RM_OPCODE, dst, src); local
872 uint16_t opc = getOpcodeGroup1(FMOVS_READ_RM_INC_OPCODE, dst, src); local
878 uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_RN_DEC_OPCODE, dst, src); local
884 uint16_t opc = getOpcodeGroup2(FTRC_OPCODE, src); local
890 uint16_t opc = getOpcodeGroup2(FLDS_FRM_FPUL_OPCODE, src); local
896 uint16_t opc = getOpcodeGroup2(FSTS_FPUL_FRN_OPCODE, src); local
902 uint16_t opc = getOpcodeGroup2(LDSFPSCR_OPCODE, reg); local
908 uint16_t opc = getOpcodeGroup2(STSFPSCR_OPCODE, reg); local
916 uint16_t opc = getOpcodeGroup7(FCNVDS_DRM_FPUL_OPCODE, src >> 1); local
922 uint16_t opc = getOpcodeGroup8(FCMPEQ_OPCODE, dst >> 1, src >> 1); local
928 uint16_t opc = getOpcodeGroup8(FCMPGT_OPCODE, dst >> 1, src >> 1); local
934 uint16_t opc = getOpcodeGroup8(FMUL_OPCODE, dst >> 1, src >> 1); local
940 uint16_t opc = getOpcodeGroup8(FSUB_OPCODE, dst >> 1, src >> 1); local
946 uint16_t opc = getOpcodeGroup8(FADD_OPCODE, dst >> 1, src >> 1); local
952 uint16_t opc = getOpcodeGroup8(FMOV_OPCODE, dst >> 1, src >> 1); local
958 uint16_t opc = getOpcodeGroup8(FDIV_OPCODE, dst >> 1, src >> 1); local
964 uint16_t opc = getOpcodeGroup7(FSQRT_OPCODE, dst >> 1); local
970 uint16_t opc = getOpcodeGroup7(FNEG_OPCODE, dst >> 1); local
976 uint16_t opc = getOpcodeGroup10(FMOVS_READ_RM_OPCODE, dst >> 1, src); local
982 uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_RN_OPCODE, dst, src >> 1); local
988 uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_R0RN_OPCODE, dst, src >> 1); local
994 uint16_t opc = getOpcodeGroup10(FMOVS_READ_R0RM_OPCODE, dst >> 1, src); local
1000 uint16_t opc = getOpcodeGroup10(FMOVS_READ_RM_INC_OPCODE, dst >> 1, src); local
1006 uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_RN_DEC_OPCODE, dst, src >> 1); local
1012 uint16_t opc = getOpcodeGroup7(FLOAT_OPCODE, src >> 1); local
1018 uint16_t opc = getOpcodeGroup7(FTRC_OPCODE, src >> 1); local
1028 uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, imm8); local
1034 uint16_t opc = getOpcodeGroup1(MOV_OPCODE, dst, src); local
1040 uint16_t opc = getOpcodeGroup1(MOVW_WRITE_RN_OPCODE, dst, src); local
1046 uint16_t opc = getOpcodeGroup1(MOVW_READ_RM_OPCODE, dst, src); local
1055 uint16_t opc = getOpcodeGroup3(MOVW_READ_OFFPC_OPCODE, dst, offset); local
1063 uint16_t opc = getOpcodeGroup11(MOVW_READ_OFFRM_OPCODE, base, offset); local
1069 uint16_t opc = getOpcodeGroup1(MOVW_READ_R0RM_OPCODE, dst, src); local
1087 uint16_t opc = getOpcodeGroup1(MOVL_WRITE_RN_OPCODE, base, src); local
1112 uint16_t opc = getOpcodeGroup11(MOVB_READ_OFFRM_OPCODE, base, offset); local
1118 uint16_t opc = getOpcodeGroup1(MOVB_READ_R0RM_OPCODE, dst, src); local
1124 uint16_t opc = getOpcodeGroup1(MOVB_READ_RM_OPCODE, dst, src); local
1130 uint16_t opc = getOpcodeGroup1(MOVL_READ_RM_OPCODE, dst, base); local
1136 uint16_t opc = getOpcodeGroup1(MOVL_READ_RMINC_OPCODE, dst, base); local
1142 uint16_t opc = getOpcodeGroup1(MOVL_READ_R0RM_OPCODE, dst, src); local
1148 uint16_t opc = getOpcodeGroup1(MOVL_WRITE_R0RN_OPCODE, dst, src); local
1156 uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, imm8); local
1167 uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, 0); local
1176 uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, 0); local
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonIntrinsics.td 20 class qi_ALU32_sisi<string opc, Intrinsic IntID>
22 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
25 class qi_ALU32_sis10<string opc, Intrinsic IntID>
27 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
30 class qi_ALU32_sis8<string opc, Intrinsic IntID>
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
35 class qi_ALU32_siu8<string opc, Intrinsic IntID>
37 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
40 class qi_ALU32_siu9<string opc, Intrinsic IntID>
42 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)"))
    [all...]
HexagonIntrinsicsV4.td 20 class si_ALU32_sisi_not<string opc, Intrinsic IntID>
22 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
25 class di_ALU32_s8si<string opc, Intrinsic IntID>
27 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
30 class di_ALU32_sis8<string opc, Intrinsic IntID>
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
35 class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
37 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
40 class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
42 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)"))
    [all...]
HexagonCFGOptimizer.cpp 53 static bool IsConditionalBranch(int Opc) {
54 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot)
55 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt);
59 static bool IsUnconditionalJump(int Opc) {
60 return (Opc == Hexagon::JMP);
106 int Opc = MI->getOpcode();
107 if (IsConditionalBranch(Opc)) {
  /external/wpa_supplicant_8/src/crypto/
milenage.h 12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
milenage.c 27 * @opc: OPc = 128-bit value derived from OP and K
36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
44 tmp1[i] = _rand[i] ^ opc[i];
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i];
67 tmp1[i] ^= opc[i];
78 * @opc: OPc = 128-bit value derived from OP and K
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
96 tmp1[i] = _rand[i] ^ opc[i]
    [all...]
  /external/llvm/lib/Target/Mips/
MipsInstrInfo.cpp 51 unsigned Opc = MI->getOpcode();
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
56 (Opc == Mips::LDC164_P8))
    [all...]
  /external/wpa_supplicant_6/wpa_supplicant/src/hlr_auc_gw/
milenage.h 18 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
21 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
23 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
25 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
hlr_auc_gw.milenage_db 2 # The example Ki, OPc, and AMF values here are from 3GPP TS 35.208 v6.0.0
8 # IMSI Ki OPc AMF SQN
  /external/llvm/lib/Target/CellSPU/
SPUInstrInfo.cpp 33 unsigned opc = I->getOpcode(); local
35 return (opc == SPU::BR
36 || opc == SPU::BRA
37 || opc == SPU::BI);
42 unsigned opc = I->getOpcode(); local
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
46 || opc == SPU::BRZr32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr1
145 unsigned opc; local
180 unsigned opc; local
    [all...]
  /external/llvm/lib/Target/X86/
X86InstrXOP.td 14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
45 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
47 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
51 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
68 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
70 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
73 def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
85 multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int>
    [all...]
X86Instr3DNow.td 36 multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
38 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
41 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> {
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
45 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
51 multiclass I3DNow_conv_rm<bits<8> opc, string Mn> {
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
53 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
56 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = "">
    [all...]
X86InstrCMovSetCC.td 17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
42 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
48 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
53 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
81 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
83 def r : I<opc, MRM0r, (outs GR8:$dst), (ins),
87 def m : I<opc, MRM0m, (outs), (ins i8mem:$dst)
    [all...]
X86InstrFMA.td 18 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
19 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
23 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
27 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
31 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
69 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop> {
70 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
74 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
101 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
103 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst)
    [all...]
X86FrameLowering.cpp 107 unsigned Opc = MBBI->getOpcode();
108 switch (Opc) {
152 unsigned Opc;
154 Opc = getLEArOpcode(Is64Bit);
156 Opc = isSub
171 Opc = isSub
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
209 unsigned Opc = PI->getOpcode()
    [all...]
  /external/wpa_supplicant_8/hostapd/
hlr_auc_gw.milenage_db 2 # The example Ki, OPc, and AMF values here are from 3GPP TS 35.208 v6.0.0
8 # IMSI Ki OPc AMF SQN
  /external/llvm/lib/Target/ARM/
ARMInstrFormats.td 398 string opc, string asm, string cstr,
405 let AsmString = !strconcat(opc, "${p}", asm);
413 string opc, string asm, string cstr,
418 let AsmString = !strconcat(opc, asm);
429 string opc, string asm, string cstr,
439 let AsmString = !strconcat(opc, "${s}${p}", asm);
457 string opc, string asm, list<dag> pattern>
459 opc, asm, "", pattern>;
461 string opc, string asm, list<dag> pattern>
463 opc, asm, "", pattern>
    [all...]
ARMBaseInstrInfo.h 41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
323 bool isUncondBranchOpcode(int Opc) {
324 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
328 bool isCondBranchOpcode(int Opc) {
329 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc
    [all...]
ARMISelDAGToDAG.cpp 115 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
118 SDValue &Offset, SDValue &Opc);
120 SDValue &Opc) {
121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
125 SDValue &Opc) {
126 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
130 SDValue &Opc) {
131 SelectAddrMode2Worker(N, Base, Offset, Opc);
132 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
138 SDValue &Offset, SDValue &Opc);
    [all...]
  /external/qemu/tcg/
tcg-op.h 28 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
30 *gen_opc_ptr++ = opc;
34 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
36 *gen_opc_ptr++ = opc;
40 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
42 *gen_opc_ptr++ = opc;
46 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
48 *gen_opc_ptr++ = opc;
53 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
55 *gen_opc_ptr++ = opc;
    [all...]
  /external/qemu/tcg/x86_64/
tcg-target.c 238 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
242 rex |= (opc & P_REXW) >> 6; /* REX.W */
252 rex |= opc & (r >= 4 ? P_REXB_R : 0);
253 rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
258 if (opc & P_EXT) {
261 tcg_out8(s, opc & 0xff);
264 static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
266 tcg_out_opc(s, opc, r, rm, 0);
271 static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
276 tcg_out_opc(s, opc, r, 0, 0)
    [all...]
  /external/qemu/
translate-op.c 31 #include "opc-trace.h"
33 #include "opc.h"
  /external/qemu/tcg/i386/
tcg-target.c 351 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
355 if (opc & P_DATA16) {
357 assert((opc & P_REXW) == 0);
360 if (opc & P_ADDR32) {
365 rex |= (opc & P_REXW) >> 8; /* REX.W */
375 rex |= opc & (r >= 4 ? P_REXB_R : 0);
376 rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
382 if (opc & P_EXT) {
385 tcg_out8(s, opc);
388 static void tcg_out_opc(TCGContext *s, int opc)
518 int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); local
568 int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); local
575 int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0); local
    [all...]

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