1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower X86 MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86MCInstLower.h" 16 #include "X86AsmPrinter.h" 17 #include "X86COFFMachineModuleInfo.h" 18 #include "InstPrinter/X86ATTInstPrinter.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 21 #include "llvm/MC/MCAsmInfo.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCStreamer.h" 26 #include "llvm/MC/MCSymbol.h" 27 #include "llvm/Target/Mangler.h" 28 #include "llvm/Support/FormattedStream.h" 29 #include "llvm/ADT/SmallString.h" 30 using namespace llvm; 31 32 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf, 33 X86AsmPrinter &asmprinter) 34 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()), 35 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {} 36 37 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 38 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 39 } 40 41 42 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 43 /// operand to an MCSymbol. 44 MCSymbol *X86MCInstLower:: 45 GetSymbolFromOperand(const MachineOperand &MO) const { 46 assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference"); 47 48 SmallString<128> Name; 49 50 if (!MO.isGlobal()) { 51 assert(MO.isSymbol()); 52 Name += MAI.getGlobalPrefix(); 53 Name += MO.getSymbolName(); 54 } else { 55 const GlobalValue *GV = MO.getGlobal(); 56 bool isImplicitlyPrivate = false; 57 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB || 58 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY || 59 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE || 60 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE) 61 isImplicitlyPrivate = true; 62 63 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate); 64 } 65 66 // If the target flags on the operand changes the name of the symbol, do that 67 // before we return the symbol. 68 switch (MO.getTargetFlags()) { 69 default: break; 70 case X86II::MO_DLLIMPORT: { 71 // Handle dllimport linkage. 72 const char *Prefix = "__imp_"; 73 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix)); 74 break; 75 } 76 case X86II::MO_DARWIN_NONLAZY: 77 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 78 Name += "$non_lazy_ptr"; 79 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 80 81 MachineModuleInfoImpl::StubValueTy &StubSym = 82 getMachOMMI().getGVStubEntry(Sym); 83 if (StubSym.getPointer() == 0) { 84 assert(MO.isGlobal() && "Extern symbol not handled yet"); 85 StubSym = 86 MachineModuleInfoImpl:: 87 StubValueTy(Mang->getSymbol(MO.getGlobal()), 88 !MO.getGlobal()->hasInternalLinkage()); 89 } 90 return Sym; 91 } 92 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: { 93 Name += "$non_lazy_ptr"; 94 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 95 MachineModuleInfoImpl::StubValueTy &StubSym = 96 getMachOMMI().getHiddenGVStubEntry(Sym); 97 if (StubSym.getPointer() == 0) { 98 assert(MO.isGlobal() && "Extern symbol not handled yet"); 99 StubSym = 100 MachineModuleInfoImpl:: 101 StubValueTy(Mang->getSymbol(MO.getGlobal()), 102 !MO.getGlobal()->hasInternalLinkage()); 103 } 104 return Sym; 105 } 106 case X86II::MO_DARWIN_STUB: { 107 Name += "$stub"; 108 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 109 MachineModuleInfoImpl::StubValueTy &StubSym = 110 getMachOMMI().getFnStubEntry(Sym); 111 if (StubSym.getPointer()) 112 return Sym; 113 114 if (MO.isGlobal()) { 115 StubSym = 116 MachineModuleInfoImpl:: 117 StubValueTy(Mang->getSymbol(MO.getGlobal()), 118 !MO.getGlobal()->hasInternalLinkage()); 119 } else { 120 Name.erase(Name.end()-5, Name.end()); 121 StubSym = 122 MachineModuleInfoImpl:: 123 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false); 124 } 125 return Sym; 126 } 127 } 128 129 return Ctx.GetOrCreateSymbol(Name.str()); 130 } 131 132 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 133 MCSymbol *Sym) const { 134 // FIXME: We would like an efficient form for this, so we don't have to do a 135 // lot of extra uniquing. 136 const MCExpr *Expr = 0; 137 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 138 139 switch (MO.getTargetFlags()) { 140 default: llvm_unreachable("Unknown target flag on GV operand"); 141 case X86II::MO_NO_FLAG: // No flag. 142 // These affect the name of the symbol, not any suffix. 143 case X86II::MO_DARWIN_NONLAZY: 144 case X86II::MO_DLLIMPORT: 145 case X86II::MO_DARWIN_STUB: 146 break; 147 148 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; 149 case X86II::MO_TLVP_PIC_BASE: 150 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 151 // Subtract the pic base. 152 Expr = MCBinaryExpr::CreateSub(Expr, 153 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), 154 Ctx), 155 Ctx); 156 break; 157 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break; 158 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 159 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 160 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 161 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 162 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 163 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 164 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 165 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 166 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 167 case X86II::MO_PIC_BASE_OFFSET: 168 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 169 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: 170 Expr = MCSymbolRefExpr::Create(Sym, Ctx); 171 // Subtract the pic base. 172 Expr = MCBinaryExpr::CreateSub(Expr, 173 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx), 174 Ctx); 175 if (MO.isJTI() && MAI.hasSetDirective()) { 176 // If .set directive is supported, use it to reduce the number of 177 // relocations the assembler will generate for differences between 178 // local labels. This is only safe when the symbols are in the same 179 // section so we are restricting it to jumptable references. 180 MCSymbol *Label = Ctx.CreateTempSymbol(); 181 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr); 182 Expr = MCSymbolRefExpr::Create(Label, Ctx); 183 } 184 break; 185 } 186 187 if (Expr == 0) 188 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx); 189 190 if (!MO.isJTI() && MO.getOffset()) 191 Expr = MCBinaryExpr::CreateAdd(Expr, 192 MCConstantExpr::Create(MO.getOffset(), Ctx), 193 Ctx); 194 return MCOperand::CreateExpr(Expr); 195 } 196 197 198 199 static void lower_subreg32(MCInst *MI, unsigned OpNo) { 200 // Convert registers in the addr mode according to subreg32. 201 unsigned Reg = MI->getOperand(OpNo).getReg(); 202 if (Reg != 0) 203 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32)); 204 } 205 206 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) { 207 // Convert registers in the addr mode according to subreg64. 208 for (unsigned i = 0; i != 4; ++i) { 209 if (!MI->getOperand(OpNo+i).isReg()) continue; 210 211 unsigned Reg = MI->getOperand(OpNo+i).getReg(); 212 if (Reg == 0) continue; 213 214 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64)); 215 } 216 } 217 218 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8. 219 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { 220 OutMI.setOpcode(NewOpc); 221 lower_subreg32(&OutMI, 0); 222 } 223 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R 224 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { 225 OutMI.setOpcode(NewOpc); 226 OutMI.addOperand(OutMI.getOperand(0)); 227 OutMI.addOperand(OutMI.getOperand(0)); 228 } 229 230 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 231 /// a short fixed-register form. 232 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 233 unsigned ImmOp = Inst.getNumOperands() - 1; 234 assert(Inst.getOperand(0).isReg() && 235 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 236 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 237 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 238 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 239 240 // Check whether the destination register can be fixed. 241 unsigned Reg = Inst.getOperand(0).getReg(); 242 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 243 return; 244 245 // If so, rewrite the instruction. 246 MCOperand Saved = Inst.getOperand(ImmOp); 247 Inst = MCInst(); 248 Inst.setOpcode(Opcode); 249 Inst.addOperand(Saved); 250 } 251 252 /// \brief Simplify things like MOV32rm to MOV32o32a. 253 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 254 unsigned Opcode) { 255 // Don't make these simplifications in 64-bit mode; other assemblers don't 256 // perform them because they make the code larger. 257 if (Printer.getSubtarget().is64Bit()) 258 return; 259 260 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 261 unsigned AddrBase = IsStore; 262 unsigned RegOp = IsStore ? 0 : 5; 263 unsigned AddrOp = AddrBase + 3; 264 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 265 Inst.getOperand(AddrBase + 0).isReg() && // base 266 Inst.getOperand(AddrBase + 1).isImm() && // scale 267 Inst.getOperand(AddrBase + 2).isReg() && // index register 268 (Inst.getOperand(AddrOp).isExpr() || // address 269 Inst.getOperand(AddrOp).isImm())&& 270 Inst.getOperand(AddrBase + 4).isReg() && // segment 271 "Unexpected instruction!"); 272 273 // Check whether the destination register can be fixed. 274 unsigned Reg = Inst.getOperand(RegOp).getReg(); 275 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 276 return; 277 278 // Check whether this is an absolute address. 279 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 280 // to do this here. 281 bool Absolute = true; 282 if (Inst.getOperand(AddrOp).isExpr()) { 283 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 284 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 285 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 286 Absolute = false; 287 } 288 289 if (Absolute && 290 (Inst.getOperand(AddrBase + 0).getReg() != 0 || 291 Inst.getOperand(AddrBase + 2).getReg() != 0 || 292 Inst.getOperand(AddrBase + 4).getReg() != 0 || 293 Inst.getOperand(AddrBase + 1).getImm() != 1)) 294 return; 295 296 // If so, rewrite the instruction. 297 MCOperand Saved = Inst.getOperand(AddrOp); 298 Inst = MCInst(); 299 Inst.setOpcode(Opcode); 300 Inst.addOperand(Saved); 301 } 302 303 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 304 OutMI.setOpcode(MI->getOpcode()); 305 306 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 307 const MachineOperand &MO = MI->getOperand(i); 308 309 MCOperand MCOp; 310 switch (MO.getType()) { 311 default: 312 MI->dump(); 313 llvm_unreachable("unknown operand type"); 314 case MachineOperand::MO_Register: 315 // Ignore all implicit register operands. 316 if (MO.isImplicit()) continue; 317 MCOp = MCOperand::CreateReg(MO.getReg()); 318 break; 319 case MachineOperand::MO_Immediate: 320 MCOp = MCOperand::CreateImm(MO.getImm()); 321 break; 322 case MachineOperand::MO_MachineBasicBlock: 323 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( 324 MO.getMBB()->getSymbol(), Ctx)); 325 break; 326 case MachineOperand::MO_GlobalAddress: 327 case MachineOperand::MO_ExternalSymbol: 328 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 329 break; 330 case MachineOperand::MO_JumpTableIndex: 331 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 332 break; 333 case MachineOperand::MO_ConstantPoolIndex: 334 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 335 break; 336 case MachineOperand::MO_BlockAddress: 337 MCOp = LowerSymbolOperand(MO, 338 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 339 break; 340 case MachineOperand::MO_RegisterMask: 341 // Ignore call clobbers. 342 continue; 343 } 344 345 OutMI.addOperand(MCOp); 346 } 347 348 // Handle a few special cases to eliminate operand modifiers. 349 ReSimplify: 350 switch (OutMI.getOpcode()) { 351 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand. 352 lower_lea64_32mem(&OutMI, 1); 353 // FALL THROUGH. 354 case X86::LEA64r: 355 case X86::LEA16r: 356 case X86::LEA32r: 357 // LEA should have a segment register, but it must be empty. 358 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && 359 "Unexpected # of LEA operands"); 360 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && 361 "LEA has segment specified!"); 362 break; 363 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break; 364 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break; 365 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break; 366 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break; 367 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break; 368 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break; 369 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break; 370 case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break; 371 case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break; 372 case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break; 373 case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break; 374 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break; 375 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break; 376 case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break; 377 case X86::AVX_SET0PSY: LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break; 378 case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break; 379 case X86::AVX_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break; 380 case X86::AVX2_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDYrr);break; 381 case X86::AVX2_SET0: LowerUnaryToTwoAddr(OutMI, X86::VPXORYrr); break; 382 383 case X86::MOV16r0: 384 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0 385 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr 386 break; 387 case X86::MOV64r0: 388 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0 389 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr 390 break; 391 392 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 393 // inputs modeled as normal uses instead of implicit uses. As such, truncate 394 // off all but the first operand (the callee). FIXME: Change isel. 395 case X86::TAILJMPr64: 396 case X86::CALL64r: 397 case X86::CALL64pcrel32: { 398 unsigned Opcode = OutMI.getOpcode(); 399 MCOperand Saved = OutMI.getOperand(0); 400 OutMI = MCInst(); 401 OutMI.setOpcode(Opcode); 402 OutMI.addOperand(Saved); 403 break; 404 } 405 406 case X86::EH_RETURN: 407 case X86::EH_RETURN64: { 408 OutMI = MCInst(); 409 OutMI.setOpcode(X86::RET); 410 break; 411 } 412 413 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions. 414 case X86::TAILJMPr: 415 case X86::TAILJMPd: 416 case X86::TAILJMPd64: { 417 unsigned Opcode; 418 switch (OutMI.getOpcode()) { 419 default: llvm_unreachable("Invalid opcode"); 420 case X86::TAILJMPr: Opcode = X86::JMP32r; break; 421 case X86::TAILJMPd: 422 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; 423 } 424 425 MCOperand Saved = OutMI.getOperand(0); 426 OutMI = MCInst(); 427 OutMI.setOpcode(Opcode); 428 OutMI.addOperand(Saved); 429 break; 430 } 431 432 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 433 // this with an ugly goto in case the resultant OR uses EAX and needs the 434 // short form. 435 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 436 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 437 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 438 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 439 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 440 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 441 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 442 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 443 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 444 445 // The assembler backend wants to see branches in their small form and relax 446 // them to their large form. The JIT can only handle the large form because 447 // it does not do relaxation. For now, translate the large form to the 448 // small one here. 449 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break; 450 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break; 451 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break; 452 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break; 453 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break; 454 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break; 455 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break; 456 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break; 457 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break; 458 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break; 459 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break; 460 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break; 461 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break; 462 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break; 463 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break; 464 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break; 465 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break; 466 467 // Atomic load and store require a separate pseudo-inst because Acquire 468 // implies mayStore and Release implies mayLoad; fix these to regular MOV 469 // instructions here 470 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; 471 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; 472 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; 473 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; 474 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; 475 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; 476 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; 477 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; 478 479 // We don't currently select the correct instruction form for instructions 480 // which have a short %eax, etc. form. Handle this by custom lowering, for 481 // now. 482 // 483 // Note, we are currently not handling the following instructions: 484 // MOV64ao8, MOV64o8a 485 // XCHG16ar, XCHG32ar, XCHG64ar 486 case X86::MOV8mr_NOREX: 487 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break; 488 case X86::MOV8rm_NOREX: 489 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break; 490 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break; 491 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break; 492 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break; 493 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break; 494 495 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break; 496 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break; 497 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break; 498 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break; 499 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break; 500 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break; 501 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break; 502 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break; 503 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break; 504 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break; 505 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break; 506 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break; 507 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break; 508 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break; 509 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break; 510 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break; 511 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break; 512 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break; 513 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break; 514 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break; 515 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break; 516 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break; 517 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break; 518 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break; 519 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break; 520 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break; 521 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break; 522 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break; 523 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break; 524 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break; 525 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break; 526 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break; 527 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break; 528 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break; 529 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break; 530 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break; 531 532 case X86::MORESTACK_RET: 533 OutMI.setOpcode(X86::RET); 534 break; 535 536 case X86::MORESTACK_RET_RESTORE_R10: { 537 MCInst retInst; 538 539 OutMI.setOpcode(X86::MOV64rr); 540 OutMI.addOperand(MCOperand::CreateReg(X86::R10)); 541 OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); 542 543 retInst.setOpcode(X86::RET); 544 AsmPrinter.OutStreamer.EmitInstruction(retInst); 545 break; 546 } 547 } 548 } 549 550 static void LowerTlsAddr(MCStreamer &OutStreamer, 551 X86MCInstLower &MCInstLowering, 552 const MachineInstr &MI) { 553 bool is64Bits = MI.getOpcode() == X86::TLS_addr64; 554 MCContext &context = OutStreamer.getContext(); 555 556 if (is64Bits) { 557 MCInst prefix; 558 prefix.setOpcode(X86::DATA16_PREFIX); 559 OutStreamer.EmitInstruction(prefix); 560 } 561 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 562 const MCSymbolRefExpr *symRef = 563 MCSymbolRefExpr::Create(sym, MCSymbolRefExpr::VK_TLSGD, context); 564 565 MCInst LEA; 566 if (is64Bits) { 567 LEA.setOpcode(X86::LEA64r); 568 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest 569 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base 570 LEA.addOperand(MCOperand::CreateImm(1)); // scale 571 LEA.addOperand(MCOperand::CreateReg(0)); // index 572 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 573 LEA.addOperand(MCOperand::CreateReg(0)); // seg 574 } else { 575 LEA.setOpcode(X86::LEA32r); 576 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 577 LEA.addOperand(MCOperand::CreateReg(0)); // base 578 LEA.addOperand(MCOperand::CreateImm(1)); // scale 579 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index 580 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 581 LEA.addOperand(MCOperand::CreateReg(0)); // seg 582 } 583 OutStreamer.EmitInstruction(LEA); 584 585 if (is64Bits) { 586 MCInst prefix; 587 prefix.setOpcode(X86::DATA16_PREFIX); 588 OutStreamer.EmitInstruction(prefix); 589 prefix.setOpcode(X86::DATA16_PREFIX); 590 OutStreamer.EmitInstruction(prefix); 591 prefix.setOpcode(X86::REX64_PREFIX); 592 OutStreamer.EmitInstruction(prefix); 593 } 594 595 MCInst call; 596 if (is64Bits) 597 call.setOpcode(X86::CALL64pcrel32); 598 else 599 call.setOpcode(X86::CALLpcrel32); 600 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 601 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name); 602 const MCSymbolRefExpr *tlsRef = 603 MCSymbolRefExpr::Create(tlsGetAddr, 604 MCSymbolRefExpr::VK_PLT, 605 context); 606 607 call.addOperand(MCOperand::CreateExpr(tlsRef)); 608 OutStreamer.EmitInstruction(call); 609 } 610 611 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 612 OutStreamer.EmitCodeRegion(); 613 614 X86MCInstLower MCInstLowering(Mang, *MF, *this); 615 switch (MI->getOpcode()) { 616 case TargetOpcode::DBG_VALUE: 617 if (isVerbose() && OutStreamer.hasRawTextSupport()) { 618 std::string TmpStr; 619 raw_string_ostream OS(TmpStr); 620 PrintDebugValueComment(MI, OS); 621 OutStreamer.EmitRawText(StringRef(OS.str())); 622 } 623 return; 624 625 // Emit nothing here but a comment if we can. 626 case X86::Int_MemBarrier: 627 if (OutStreamer.hasRawTextSupport()) 628 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER")); 629 return; 630 631 632 case X86::EH_RETURN: 633 case X86::EH_RETURN64: { 634 // Lower these as normal, but add some comments. 635 unsigned Reg = MI->getOperand(0).getReg(); 636 OutStreamer.AddComment(StringRef("eh_return, addr: %") + 637 X86ATTInstPrinter::getRegisterName(Reg)); 638 break; 639 } 640 case X86::TAILJMPr: 641 case X86::TAILJMPd: 642 case X86::TAILJMPd64: 643 // Lower these as normal, but add some comments. 644 OutStreamer.AddComment("TAILCALL"); 645 break; 646 647 case X86::TLS_addr32: 648 case X86::TLS_addr64: 649 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI); 650 651 case X86::MOVPC32r: { 652 MCInst TmpInst; 653 // This is a pseudo op for a two instruction sequence with a label, which 654 // looks like: 655 // call "L1$pb" 656 // "L1$pb": 657 // popl %esi 658 659 // Emit the call. 660 MCSymbol *PICBase = MF->getPICBaseSymbol(); 661 TmpInst.setOpcode(X86::CALLpcrel32); 662 // FIXME: We would like an efficient form for this, so we don't have to do a 663 // lot of extra uniquing. 664 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase, 665 OutContext))); 666 OutStreamer.EmitInstruction(TmpInst); 667 668 // Emit the label. 669 OutStreamer.EmitLabel(PICBase); 670 671 // popl $reg 672 TmpInst.setOpcode(X86::POP32r); 673 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg()); 674 OutStreamer.EmitInstruction(TmpInst); 675 return; 676 } 677 678 case X86::ADD32ri: { 679 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 680 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 681 break; 682 683 // Okay, we have something like: 684 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 685 686 // For this, we want to print something like: 687 // MYGLOBAL + (. - PICBASE) 688 // However, we can't generate a ".", so just emit a new label here and refer 689 // to it. 690 MCSymbol *DotSym = OutContext.CreateTempSymbol(); 691 OutStreamer.EmitLabel(DotSym); 692 693 // Now that we have emitted the label, lower the complex operand expression. 694 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 695 696 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); 697 const MCExpr *PICBase = 698 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext); 699 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext); 700 701 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), 702 DotExpr, OutContext); 703 704 MCInst TmpInst; 705 TmpInst.setOpcode(X86::ADD32ri); 706 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 707 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); 708 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr)); 709 OutStreamer.EmitInstruction(TmpInst); 710 return; 711 } 712 } 713 714 MCInst TmpInst; 715 MCInstLowering.Lower(MI, TmpInst); 716 OutStreamer.EmitInstruction(TmpInst); 717 } 718 719
