1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the ARM implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMFrameLowering.h" 15 #include "ARMBaseInstrInfo.h" 16 #include "ARMBaseRegisterInfo.h" 17 #include "ARMMachineFunctionInfo.h" 18 #include "MCTargetDesc/ARMAddressingModes.h" 19 #include "llvm/Function.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/RegisterScavenging.h" 25 #include "llvm/Target/TargetOptions.h" 26 #include "llvm/Support/CommandLine.h" 27 28 using namespace llvm; 29 30 static cl::opt<bool> 31 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true), 32 cl::desc("Align ARM NEON spills in prolog and epilog")); 33 34 static MachineBasicBlock::iterator 35 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 36 unsigned NumAlignedDPRCS2Regs); 37 38 /// hasFP - Return true if the specified function should have a dedicated frame 39 /// pointer register. This is true if the function has variable sized allocas 40 /// or if frame pointer elimination is disabled. 41 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 42 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 43 44 // iOS requires FP not to be clobbered for backtracing purpose. 45 if (STI.isTargetIOS()) 46 return true; 47 48 const MachineFrameInfo *MFI = MF.getFrameInfo(); 49 // Always eliminate non-leaf frame pointers. 50 return ((MF.getTarget().Options.DisableFramePointerElim(MF) && 51 MFI->hasCalls()) || 52 RegInfo->needsStackRealignment(MF) || 53 MFI->hasVarSizedObjects() || 54 MFI->isFrameAddressTaken()); 55 } 56 57 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 58 /// not required, we reserve argument space for call sites in the function 59 /// immediately on entry to the current function. This eliminates the need for 60 /// add/sub sp brackets around call sites. Returns true if the call frame is 61 /// included as part of the stack frame. 62 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 63 const MachineFrameInfo *FFI = MF.getFrameInfo(); 64 unsigned CFSize = FFI->getMaxCallFrameSize(); 65 // It's not always a good idea to include the call frame as part of the 66 // stack frame. ARM (especially Thumb) has small immediate offset to 67 // address the stack frame. So a large call frame can cause poor codegen 68 // and may even makes it impossible to scavenge a register. 69 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 70 return false; 71 72 return !MF.getFrameInfo()->hasVarSizedObjects(); 73 } 74 75 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the 76 /// call frame pseudos can be simplified. Unlike most targets, having a FP 77 /// is not sufficient here since we still may reference some objects via SP 78 /// even when FP is available in Thumb2 mode. 79 bool 80 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { 81 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 82 } 83 84 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) { 85 for (unsigned i = 0; CSRegs[i]; ++i) 86 if (Reg == CSRegs[i]) 87 return true; 88 return false; 89 } 90 91 static bool isCSRestore(MachineInstr *MI, 92 const ARMBaseInstrInfo &TII, 93 const uint16_t *CSRegs) { 94 // Integer spill area is handled with "pop". 95 if (MI->getOpcode() == ARM::LDMIA_RET || 96 MI->getOpcode() == ARM::t2LDMIA_RET || 97 MI->getOpcode() == ARM::LDMIA_UPD || 98 MI->getOpcode() == ARM::t2LDMIA_UPD || 99 MI->getOpcode() == ARM::VLDMDIA_UPD) { 100 // The first two operands are predicates. The last two are 101 // imp-def and imp-use of SP. Check everything in between. 102 for (int i = 5, e = MI->getNumOperands(); i != e; ++i) 103 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 104 return false; 105 return true; 106 } 107 if ((MI->getOpcode() == ARM::LDR_POST_IMM || 108 MI->getOpcode() == ARM::LDR_POST_REG || 109 MI->getOpcode() == ARM::t2LDR_POST) && 110 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && 111 MI->getOperand(1).getReg() == ARM::SP) 112 return true; 113 114 return false; 115 } 116 117 static void 118 emitSPUpdate(bool isARM, 119 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 120 DebugLoc dl, const ARMBaseInstrInfo &TII, 121 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 122 if (isARM) 123 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 124 ARMCC::AL, 0, TII, MIFlags); 125 else 126 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 127 ARMCC::AL, 0, TII, MIFlags); 128 } 129 130 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { 131 MachineBasicBlock &MBB = MF.front(); 132 MachineBasicBlock::iterator MBBI = MBB.begin(); 133 MachineFrameInfo *MFI = MF.getFrameInfo(); 134 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 135 const ARMBaseRegisterInfo *RegInfo = 136 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 137 const ARMBaseInstrInfo &TII = 138 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 139 assert(!AFI->isThumb1OnlyFunction() && 140 "This emitPrologue does not support Thumb1!"); 141 bool isARM = !AFI->isThumbFunction(); 142 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 143 unsigned NumBytes = MFI->getStackSize(); 144 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 145 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 146 unsigned FramePtr = RegInfo->getFrameRegister(MF); 147 148 // Determine the sizes of each callee-save spill areas and record which frame 149 // belongs to which callee-save spill areas. 150 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 151 int FramePtrSpillFI = 0; 152 int D8SpillFI = 0; 153 154 // Allocate the vararg register save area. This is not counted in NumBytes. 155 if (VARegSaveSize) 156 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize, 157 MachineInstr::FrameSetup); 158 159 if (!AFI->hasStackFrame()) { 160 if (NumBytes != 0) 161 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 162 MachineInstr::FrameSetup); 163 return; 164 } 165 166 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 167 unsigned Reg = CSI[i].getReg(); 168 int FI = CSI[i].getFrameIdx(); 169 switch (Reg) { 170 case ARM::R4: 171 case ARM::R5: 172 case ARM::R6: 173 case ARM::R7: 174 case ARM::LR: 175 if (Reg == FramePtr) 176 FramePtrSpillFI = FI; 177 AFI->addGPRCalleeSavedArea1Frame(FI); 178 GPRCS1Size += 4; 179 break; 180 case ARM::R8: 181 case ARM::R9: 182 case ARM::R10: 183 case ARM::R11: 184 if (Reg == FramePtr) 185 FramePtrSpillFI = FI; 186 if (STI.isTargetIOS()) { 187 AFI->addGPRCalleeSavedArea2Frame(FI); 188 GPRCS2Size += 4; 189 } else { 190 AFI->addGPRCalleeSavedArea1Frame(FI); 191 GPRCS1Size += 4; 192 } 193 break; 194 default: 195 // This is a DPR. Exclude the aligned DPRCS2 spills. 196 if (Reg == ARM::D8) 197 D8SpillFI = FI; 198 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) { 199 AFI->addDPRCalleeSavedAreaFrame(FI); 200 DPRCSSize += 8; 201 } 202 } 203 } 204 205 // Move past area 1. 206 if (GPRCS1Size > 0) MBBI++; 207 208 // Set FP to point to the stack slot that contains the previous FP. 209 // For iOS, FP is R7, which has now been stored in spill area 1. 210 // Otherwise, if this is not iOS, all the callee-saved registers go 211 // into spill area 1, including the FP in R11. In either case, it is 212 // now safe to emit this assignment. 213 bool HasFP = hasFP(MF); 214 if (HasFP) { 215 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 216 MachineInstrBuilder MIB = 217 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 218 .addFrameIndex(FramePtrSpillFI).addImm(0) 219 .setMIFlag(MachineInstr::FrameSetup); 220 AddDefaultCC(AddDefaultPred(MIB)); 221 } 222 223 // Move past area 2. 224 if (GPRCS2Size > 0) MBBI++; 225 226 // Determine starting offsets of spill areas. 227 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 228 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 229 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 230 if (HasFP) 231 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 232 NumBytes); 233 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 234 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 235 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 236 237 // Move past area 3. 238 if (DPRCSSize > 0) { 239 MBBI++; 240 // Since vpush register list cannot have gaps, there may be multiple vpush 241 // instructions in the prologue. 242 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) 243 MBBI++; 244 } 245 246 // Move past the aligned DPRCS2 area. 247 if (AFI->getNumAlignedDPRCS2Regs() > 0) { 248 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs()); 249 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and 250 // leaves the stack pointer pointing to the DPRCS2 area. 251 // 252 // Adjust NumBytes to represent the stack slots below the DPRCS2 area. 253 NumBytes += MFI->getObjectOffset(D8SpillFI); 254 } else 255 NumBytes = DPRCSOffset; 256 257 if (NumBytes) { 258 // Adjust SP after all the callee-save spills. 259 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 260 MachineInstr::FrameSetup); 261 if (HasFP && isARM) 262 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 263 // Note it's not safe to do this in Thumb2 mode because it would have 264 // taken two instructions: 265 // mov sp, r7 266 // sub sp, #24 267 // If an interrupt is taken between the two instructions, then sp is in 268 // an inconsistent state (pointing to the middle of callee-saved area). 269 // The interrupt handler can end up clobbering the registers. 270 AFI->setShouldRestoreSPFromFP(true); 271 } 272 273 if (STI.isTargetELF() && hasFP(MF)) 274 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 275 AFI->getFramePtrSpillOffset()); 276 277 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 278 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 279 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 280 281 // If we need dynamic stack realignment, do it here. Be paranoid and make 282 // sure if we also have VLAs, we have a base pointer for frame access. 283 // If aligned NEON registers were spilled, the stack has already been 284 // realigned. 285 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { 286 unsigned MaxAlign = MFI->getMaxAlignment(); 287 assert (!AFI->isThumb1OnlyFunction()); 288 if (!AFI->isThumbFunction()) { 289 // Emit bic sp, sp, MaxAlign 290 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 291 TII.get(ARM::BICri), ARM::SP) 292 .addReg(ARM::SP, RegState::Kill) 293 .addImm(MaxAlign-1))); 294 } else { 295 // We cannot use sp as source/dest register here, thus we're emitting the 296 // following sequence: 297 // mov r4, sp 298 // bic r4, r4, MaxAlign 299 // mov sp, r4 300 // FIXME: It will be better just to find spare register here. 301 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 302 .addReg(ARM::SP, RegState::Kill)); 303 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 304 TII.get(ARM::t2BICri), ARM::R4) 305 .addReg(ARM::R4, RegState::Kill) 306 .addImm(MaxAlign-1))); 307 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 308 .addReg(ARM::R4, RegState::Kill)); 309 } 310 311 AFI->setShouldRestoreSPFromFP(true); 312 } 313 314 // If we need a base pointer, set it up here. It's whatever the value 315 // of the stack pointer is at this point. Any variable size objects 316 // will be allocated after this, so we can still use the base pointer 317 // to reference locals. 318 // FIXME: Clarify FrameSetup flags here. 319 if (RegInfo->hasBasePointer(MF)) { 320 if (isARM) 321 BuildMI(MBB, MBBI, dl, 322 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 323 .addReg(ARM::SP) 324 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 325 else 326 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 327 RegInfo->getBaseRegister()) 328 .addReg(ARM::SP)); 329 } 330 331 // If the frame has variable sized objects then the epilogue must restore 332 // the sp from fp. We can assume there's an FP here since hasFP already 333 // checks for hasVarSizedObjects. 334 if (MFI->hasVarSizedObjects()) 335 AFI->setShouldRestoreSPFromFP(true); 336 } 337 338 void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 339 MachineBasicBlock &MBB) const { 340 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 341 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks"); 342 unsigned RetOpcode = MBBI->getOpcode(); 343 DebugLoc dl = MBBI->getDebugLoc(); 344 MachineFrameInfo *MFI = MF.getFrameInfo(); 345 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 346 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 347 const ARMBaseInstrInfo &TII = 348 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 349 assert(!AFI->isThumb1OnlyFunction() && 350 "This emitEpilogue does not support Thumb1!"); 351 bool isARM = !AFI->isThumbFunction(); 352 353 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 354 int NumBytes = (int)MFI->getStackSize(); 355 unsigned FramePtr = RegInfo->getFrameRegister(MF); 356 357 if (!AFI->hasStackFrame()) { 358 if (NumBytes != 0) 359 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 360 } else { 361 // Unwind MBBI to point to first LDR / VLDRD. 362 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(); 363 if (MBBI != MBB.begin()) { 364 do 365 --MBBI; 366 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 367 if (!isCSRestore(MBBI, TII, CSRegs)) 368 ++MBBI; 369 } 370 371 // Move SP to start of FP callee save spill area. 372 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 373 AFI->getGPRCalleeSavedArea2Size() + 374 AFI->getDPRCalleeSavedAreaSize()); 375 376 // Reset SP based on frame pointer only if the stack frame extends beyond 377 // frame pointer stack slot or target is ELF and the function has FP. 378 if (AFI->shouldRestoreSPFromFP()) { 379 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 380 if (NumBytes) { 381 if (isARM) 382 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 383 ARMCC::AL, 0, TII); 384 else { 385 // It's not possible to restore SP from FP in a single instruction. 386 // For iOS, this looks like: 387 // mov sp, r7 388 // sub sp, #24 389 // This is bad, if an interrupt is taken after the mov, sp is in an 390 // inconsistent state. 391 // Use the first callee-saved register as a scratch register. 392 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 393 "No scratch register to restore SP from FP!"); 394 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 395 ARMCC::AL, 0, TII); 396 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 397 ARM::SP) 398 .addReg(ARM::R4)); 399 } 400 } else { 401 // Thumb2 or ARM. 402 if (isARM) 403 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 404 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 405 else 406 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 407 ARM::SP) 408 .addReg(FramePtr)); 409 } 410 } else if (NumBytes) 411 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 412 413 // Increment past our save areas. 414 if (AFI->getDPRCalleeSavedAreaSize()) { 415 MBBI++; 416 // Since vpop register list cannot have gaps, there may be multiple vpop 417 // instructions in the epilogue. 418 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD) 419 MBBI++; 420 } 421 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; 422 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; 423 } 424 425 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) { 426 // Tail call return: adjust the stack pointer and jump to callee. 427 MBBI = MBB.getLastNonDebugInstr(); 428 MachineOperand &JumpTarget = MBBI->getOperand(0); 429 430 // Jump to label or value in register. 431 if (RetOpcode == ARM::TCRETURNdi) { 432 unsigned TCOpcode = STI.isThumb() ? 433 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) : 434 ARM::TAILJMPd; 435 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 436 if (JumpTarget.isGlobal()) 437 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 438 JumpTarget.getTargetFlags()); 439 else { 440 assert(JumpTarget.isSymbol()); 441 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 442 JumpTarget.getTargetFlags()); 443 } 444 445 // Add the default predicate in Thumb mode. 446 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); 447 } else if (RetOpcode == ARM::TCRETURNri) { 448 BuildMI(MBB, MBBI, dl, 449 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)). 450 addReg(JumpTarget.getReg(), RegState::Kill); 451 } 452 453 MachineInstr *NewMI = prior(MBBI); 454 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 455 NewMI->addOperand(MBBI->getOperand(i)); 456 457 // Delete the pseudo instruction TCRETURN. 458 MBB.erase(MBBI); 459 MBBI = NewMI; 460 } 461 462 if (VARegSaveSize) 463 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 464 } 465 466 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for 467 /// debug info. It's the same as what we use for resolving the code-gen 468 /// references for now. FIXME: This can go wrong when references are 469 /// SP-relative and simple call frames aren't used. 470 int 471 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 472 unsigned &FrameReg) const { 473 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 474 } 475 476 int 477 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, 478 int FI, unsigned &FrameReg, 479 int SPAdj) const { 480 const MachineFrameInfo *MFI = MF.getFrameInfo(); 481 const ARMBaseRegisterInfo *RegInfo = 482 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 483 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 484 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 485 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 486 bool isFixed = MFI->isFixedObjectIndex(FI); 487 488 FrameReg = ARM::SP; 489 Offset += SPAdj; 490 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 491 return Offset - AFI->getGPRCalleeSavedArea1Offset(); 492 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 493 return Offset - AFI->getGPRCalleeSavedArea2Offset(); 494 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 495 return Offset - AFI->getDPRCalleeSavedAreaOffset(); 496 497 // SP can move around if there are allocas. We may also lose track of SP 498 // when emergency spilling inside a non-reserved call frame setup. 499 bool hasMovingSP = !hasReservedCallFrame(MF); 500 501 // When dynamically realigning the stack, use the frame pointer for 502 // parameters, and the stack/base pointer for locals. 503 if (RegInfo->needsStackRealignment(MF)) { 504 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 505 if (isFixed) { 506 FrameReg = RegInfo->getFrameRegister(MF); 507 Offset = FPOffset; 508 } else if (hasMovingSP) { 509 assert(RegInfo->hasBasePointer(MF) && 510 "VLAs and dynamic stack alignment, but missing base pointer!"); 511 FrameReg = RegInfo->getBaseRegister(); 512 } 513 return Offset; 514 } 515 516 // If there is a frame pointer, use it when we can. 517 if (hasFP(MF) && AFI->hasStackFrame()) { 518 // Use frame pointer to reference fixed objects. Use it for locals if 519 // there are VLAs (and thus the SP isn't reliable as a base). 520 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) { 521 FrameReg = RegInfo->getFrameRegister(MF); 522 return FPOffset; 523 } else if (hasMovingSP) { 524 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); 525 if (AFI->isThumb2Function()) { 526 // Try to use the frame pointer if we can, else use the base pointer 527 // since it's available. This is handy for the emergency spill slot, in 528 // particular. 529 if (FPOffset >= -255 && FPOffset < 0) { 530 FrameReg = RegInfo->getFrameRegister(MF); 531 return FPOffset; 532 } 533 } 534 } else if (AFI->isThumb2Function()) { 535 // Use add <rd>, sp, #<imm8> 536 // ldr <rd>, [sp, #<imm8>] 537 // if at all possible to save space. 538 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) 539 return Offset; 540 // In Thumb2 mode, the negative offset is very limited. Try to avoid 541 // out of range references. ldr <rt>,[<rn>, #-<imm8>] 542 if (FPOffset >= -255 && FPOffset < 0) { 543 FrameReg = RegInfo->getFrameRegister(MF); 544 return FPOffset; 545 } 546 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 547 // Otherwise, use SP or FP, whichever is closer to the stack slot. 548 FrameReg = RegInfo->getFrameRegister(MF); 549 return FPOffset; 550 } 551 } 552 // Use the base pointer if we have one. 553 if (RegInfo->hasBasePointer(MF)) 554 FrameReg = RegInfo->getBaseRegister(); 555 return Offset; 556 } 557 558 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, 559 int FI) const { 560 unsigned FrameReg; 561 return getFrameIndexReference(MF, FI, FrameReg); 562 } 563 564 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, 565 MachineBasicBlock::iterator MI, 566 const std::vector<CalleeSavedInfo> &CSI, 567 unsigned StmOpc, unsigned StrOpc, 568 bool NoGap, 569 bool(*Func)(unsigned, bool), 570 unsigned NumAlignedDPRCS2Regs, 571 unsigned MIFlags) const { 572 MachineFunction &MF = *MBB.getParent(); 573 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 574 575 DebugLoc DL; 576 if (MI != MBB.end()) DL = MI->getDebugLoc(); 577 578 SmallVector<std::pair<unsigned,bool>, 4> Regs; 579 unsigned i = CSI.size(); 580 while (i != 0) { 581 unsigned LastReg = 0; 582 for (; i != 0; --i) { 583 unsigned Reg = CSI[i-1].getReg(); 584 if (!(Func)(Reg, STI.isTargetIOS())) continue; 585 586 // D-registers in the aligned area DPRCS2 are NOT spilled here. 587 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 588 continue; 589 590 // Add the callee-saved register as live-in unless it's LR and 591 // @llvm.returnaddress is called. If LR is returned for 592 // @llvm.returnaddress then it's already added to the function and 593 // entry block live-in sets. 594 bool isKill = true; 595 if (Reg == ARM::LR) { 596 if (MF.getFrameInfo()->isReturnAddressTaken() && 597 MF.getRegInfo().isLiveIn(Reg)) 598 isKill = false; 599 } 600 601 if (isKill) 602 MBB.addLiveIn(Reg); 603 604 // If NoGap is true, push consecutive registers and then leave the rest 605 // for other instructions. e.g. 606 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} 607 if (NoGap && LastReg && LastReg != Reg-1) 608 break; 609 LastReg = Reg; 610 Regs.push_back(std::make_pair(Reg, isKill)); 611 } 612 613 if (Regs.empty()) 614 continue; 615 if (Regs.size() > 1 || StrOpc== 0) { 616 MachineInstrBuilder MIB = 617 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) 618 .addReg(ARM::SP).setMIFlags(MIFlags)); 619 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 620 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 621 } else if (Regs.size() == 1) { 622 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), 623 ARM::SP) 624 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) 625 .addReg(ARM::SP).setMIFlags(MIFlags) 626 .addImm(-4); 627 AddDefaultPred(MIB); 628 } 629 Regs.clear(); 630 } 631 } 632 633 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, 634 MachineBasicBlock::iterator MI, 635 const std::vector<CalleeSavedInfo> &CSI, 636 unsigned LdmOpc, unsigned LdrOpc, 637 bool isVarArg, bool NoGap, 638 bool(*Func)(unsigned, bool), 639 unsigned NumAlignedDPRCS2Regs) const { 640 MachineFunction &MF = *MBB.getParent(); 641 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 642 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 643 DebugLoc DL = MI->getDebugLoc(); 644 unsigned RetOpcode = MI->getOpcode(); 645 bool isTailCall = (RetOpcode == ARM::TCRETURNdi || 646 RetOpcode == ARM::TCRETURNri); 647 648 SmallVector<unsigned, 4> Regs; 649 unsigned i = CSI.size(); 650 while (i != 0) { 651 unsigned LastReg = 0; 652 bool DeleteRet = false; 653 for (; i != 0; --i) { 654 unsigned Reg = CSI[i-1].getReg(); 655 if (!(Func)(Reg, STI.isTargetIOS())) continue; 656 657 // The aligned reloads from area DPRCS2 are not inserted here. 658 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs) 659 continue; 660 661 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) { 662 Reg = ARM::PC; 663 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; 664 // Fold the return instruction into the LDM. 665 DeleteRet = true; 666 } 667 668 // If NoGap is true, pop consecutive registers and then leave the rest 669 // for other instructions. e.g. 670 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} 671 if (NoGap && LastReg && LastReg != Reg-1) 672 break; 673 674 LastReg = Reg; 675 Regs.push_back(Reg); 676 } 677 678 if (Regs.empty()) 679 continue; 680 if (Regs.size() > 1 || LdrOpc == 0) { 681 MachineInstrBuilder MIB = 682 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) 683 .addReg(ARM::SP)); 684 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 685 MIB.addReg(Regs[i], getDefRegState(true)); 686 if (DeleteRet) { 687 MIB->copyImplicitOps(&*MI); 688 MI->eraseFromParent(); 689 } 690 MI = MIB; 691 } else if (Regs.size() == 1) { 692 // If we adjusted the reg to PC from LR above, switch it back here. We 693 // only do that for LDM. 694 if (Regs[0] == ARM::PC) 695 Regs[0] = ARM::LR; 696 MachineInstrBuilder MIB = 697 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) 698 .addReg(ARM::SP, RegState::Define) 699 .addReg(ARM::SP); 700 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 701 // that refactoring is complete (eventually). 702 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { 703 MIB.addReg(0); 704 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); 705 } else 706 MIB.addImm(4); 707 AddDefaultPred(MIB); 708 } 709 Regs.clear(); 710 } 711 } 712 713 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers 714 /// starting from d8. Also insert stack realignment code and leave the stack 715 /// pointer pointing to the d8 spill slot. 716 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, 717 MachineBasicBlock::iterator MI, 718 unsigned NumAlignedDPRCS2Regs, 719 const std::vector<CalleeSavedInfo> &CSI, 720 const TargetRegisterInfo *TRI) { 721 MachineFunction &MF = *MBB.getParent(); 722 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 723 DebugLoc DL = MI->getDebugLoc(); 724 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 725 MachineFrameInfo &MFI = *MF.getFrameInfo(); 726 727 // Mark the D-register spill slots as properly aligned. Since MFI computes 728 // stack slot layout backwards, this can actually mean that the d-reg stack 729 // slot offsets can be wrong. The offset for d8 will always be correct. 730 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 731 unsigned DNum = CSI[i].getReg() - ARM::D8; 732 if (DNum >= 8) 733 continue; 734 int FI = CSI[i].getFrameIdx(); 735 // The even-numbered registers will be 16-byte aligned, the odd-numbered 736 // registers will be 8-byte aligned. 737 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16); 738 739 // The stack slot for D8 needs to be maximally aligned because this is 740 // actually the point where we align the stack pointer. MachineFrameInfo 741 // computes all offsets relative to the incoming stack pointer which is a 742 // bit weird when realigning the stack. Any extra padding for this 743 // over-alignment is not realized because the code inserted below adjusts 744 // the stack pointer by numregs * 8 before aligning the stack pointer. 745 if (DNum == 0) 746 MFI.setObjectAlignment(FI, MFI.getMaxAlignment()); 747 } 748 749 // Move the stack pointer to the d8 spill slot, and align it at the same 750 // time. Leave the stack slot address in the scratch register r4. 751 // 752 // sub r4, sp, #numregs * 8 753 // bic r4, r4, #align - 1 754 // mov sp, r4 755 // 756 bool isThumb = AFI->isThumbFunction(); 757 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 758 AFI->setShouldRestoreSPFromFP(true); 759 760 // sub r4, sp, #numregs * 8 761 // The immediate is <= 64, so it doesn't need any special encoding. 762 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; 763 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 764 .addReg(ARM::SP) 765 .addImm(8 * NumAlignedDPRCS2Regs))); 766 767 // bic r4, r4, #align-1 768 Opc = isThumb ? ARM::t2BICri : ARM::BICri; 769 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment(); 770 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 771 .addReg(ARM::R4, RegState::Kill) 772 .addImm(MaxAlign - 1))); 773 774 // mov sp, r4 775 // The stack pointer must be adjusted before spilling anything, otherwise 776 // the stack slots could be clobbered by an interrupt handler. 777 // Leave r4 live, it is used below. 778 Opc = isThumb ? ARM::tMOVr : ARM::MOVr; 779 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) 780 .addReg(ARM::R4); 781 MIB = AddDefaultPred(MIB); 782 if (!isThumb) 783 AddDefaultCC(MIB); 784 785 // Now spill NumAlignedDPRCS2Regs registers starting from d8. 786 // r4 holds the stack slot address. 787 unsigned NextReg = ARM::D8; 788 789 // 16-byte aligned vst1.64 with 4 d-regs and address writeback. 790 // The writeback is only needed when emitting two vst1.64 instructions. 791 if (NumAlignedDPRCS2Regs >= 6) { 792 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 793 ARM::QQPRRegisterClass); 794 MBB.addLiveIn(SupReg); 795 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), 796 ARM::R4) 797 .addReg(ARM::R4, RegState::Kill).addImm(16) 798 .addReg(NextReg) 799 .addReg(SupReg, RegState::ImplicitKill)); 800 NextReg += 4; 801 NumAlignedDPRCS2Regs -= 4; 802 } 803 804 // We won't modify r4 beyond this point. It currently points to the next 805 // register to be spilled. 806 unsigned R4BaseReg = NextReg; 807 808 // 16-byte aligned vst1.64 with 4 d-regs, no writeback. 809 if (NumAlignedDPRCS2Regs >= 4) { 810 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 811 ARM::QQPRRegisterClass); 812 MBB.addLiveIn(SupReg); 813 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) 814 .addReg(ARM::R4).addImm(16).addReg(NextReg) 815 .addReg(SupReg, RegState::ImplicitKill)); 816 NextReg += 4; 817 NumAlignedDPRCS2Regs -= 4; 818 } 819 820 // 16-byte aligned vst1.64 with 2 d-regs. 821 if (NumAlignedDPRCS2Regs >= 2) { 822 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 823 ARM::QPRRegisterClass); 824 MBB.addLiveIn(SupReg); 825 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) 826 .addReg(ARM::R4).addImm(16).addReg(SupReg)); 827 NextReg += 2; 828 NumAlignedDPRCS2Regs -= 2; 829 } 830 831 // Finally, use a vanilla vstr.64 for the odd last register. 832 if (NumAlignedDPRCS2Regs) { 833 MBB.addLiveIn(NextReg); 834 // vstr.64 uses addrmode5 which has an offset scale of 4. 835 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) 836 .addReg(NextReg) 837 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2)); 838 } 839 840 // The last spill instruction inserted should kill the scratch register r4. 841 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI); 842 } 843 844 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an 845 /// iterator to the following instruction. 846 static MachineBasicBlock::iterator 847 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, 848 unsigned NumAlignedDPRCS2Regs) { 849 // sub r4, sp, #numregs * 8 850 // bic r4, r4, #align - 1 851 // mov sp, r4 852 ++MI; ++MI; ++MI; 853 assert(MI->mayStore() && "Expecting spill instruction"); 854 855 // These switches all fall through. 856 switch(NumAlignedDPRCS2Regs) { 857 case 7: 858 ++MI; 859 assert(MI->mayStore() && "Expecting spill instruction"); 860 default: 861 ++MI; 862 assert(MI->mayStore() && "Expecting spill instruction"); 863 case 1: 864 case 2: 865 case 4: 866 assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); 867 ++MI; 868 } 869 return MI; 870 } 871 872 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers 873 /// starting from d8. These instructions are assumed to execute while the 874 /// stack is still aligned, unlike the code inserted by emitPopInst. 875 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, 876 MachineBasicBlock::iterator MI, 877 unsigned NumAlignedDPRCS2Regs, 878 const std::vector<CalleeSavedInfo> &CSI, 879 const TargetRegisterInfo *TRI) { 880 MachineFunction &MF = *MBB.getParent(); 881 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 882 DebugLoc DL = MI->getDebugLoc(); 883 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 884 885 // Find the frame index assigned to d8. 886 int D8SpillFI = 0; 887 for (unsigned i = 0, e = CSI.size(); i != e; ++i) 888 if (CSI[i].getReg() == ARM::D8) { 889 D8SpillFI = CSI[i].getFrameIdx(); 890 break; 891 } 892 893 // Materialize the address of the d8 spill slot into the scratch register r4. 894 // This can be fairly complicated if the stack frame is large, so just use 895 // the normal frame index elimination mechanism to do it. This code runs as 896 // the initial part of the epilog where the stack and base pointers haven't 897 // been changed yet. 898 bool isThumb = AFI->isThumbFunction(); 899 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1"); 900 901 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; 902 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) 903 .addFrameIndex(D8SpillFI).addImm(0))); 904 905 // Now restore NumAlignedDPRCS2Regs registers starting from d8. 906 unsigned NextReg = ARM::D8; 907 908 // 16-byte aligned vld1.64 with 4 d-regs and writeback. 909 if (NumAlignedDPRCS2Regs >= 6) { 910 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 911 ARM::QQPRRegisterClass); 912 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) 913 .addReg(ARM::R4, RegState::Define) 914 .addReg(ARM::R4, RegState::Kill).addImm(16) 915 .addReg(SupReg, RegState::ImplicitDefine)); 916 NextReg += 4; 917 NumAlignedDPRCS2Regs -= 4; 918 } 919 920 // We won't modify r4 beyond this point. It currently points to the next 921 // register to be spilled. 922 unsigned R4BaseReg = NextReg; 923 924 // 16-byte aligned vld1.64 with 4 d-regs, no writeback. 925 if (NumAlignedDPRCS2Regs >= 4) { 926 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 927 ARM::QQPRRegisterClass); 928 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) 929 .addReg(ARM::R4).addImm(16) 930 .addReg(SupReg, RegState::ImplicitDefine)); 931 NextReg += 4; 932 NumAlignedDPRCS2Regs -= 4; 933 } 934 935 // 16-byte aligned vld1.64 with 2 d-regs. 936 if (NumAlignedDPRCS2Regs >= 2) { 937 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, 938 ARM::QPRRegisterClass); 939 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) 940 .addReg(ARM::R4).addImm(16)); 941 NextReg += 2; 942 NumAlignedDPRCS2Regs -= 2; 943 } 944 945 // Finally, use a vanilla vldr.64 for the remaining odd register. 946 if (NumAlignedDPRCS2Regs) 947 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) 948 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg))); 949 950 // Last store kills r4. 951 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI); 952 } 953 954 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 955 MachineBasicBlock::iterator MI, 956 const std::vector<CalleeSavedInfo> &CSI, 957 const TargetRegisterInfo *TRI) const { 958 if (CSI.empty()) 959 return false; 960 961 MachineFunction &MF = *MBB.getParent(); 962 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 963 964 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; 965 unsigned PushOneOpc = AFI->isThumbFunction() ? 966 ARM::t2STR_PRE : ARM::STR_PRE_IMM; 967 unsigned FltOpc = ARM::VSTMDDB_UPD; 968 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 969 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0, 970 MachineInstr::FrameSetup); 971 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0, 972 MachineInstr::FrameSetup); 973 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register, 974 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup); 975 976 // The code above does not insert spill code for the aligned DPRCS2 registers. 977 // The stack realignment code will be inserted between the push instructions 978 // and these spills. 979 if (NumAlignedDPRCS2Regs) 980 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 981 982 return true; 983 } 984 985 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 986 MachineBasicBlock::iterator MI, 987 const std::vector<CalleeSavedInfo> &CSI, 988 const TargetRegisterInfo *TRI) const { 989 if (CSI.empty()) 990 return false; 991 992 MachineFunction &MF = *MBB.getParent(); 993 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 994 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 995 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs(); 996 997 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2 998 // registers. Do that here instead. 999 if (NumAlignedDPRCS2Regs) 1000 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI); 1001 1002 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 1003 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; 1004 unsigned FltOpc = ARM::VLDMDIA_UPD; 1005 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register, 1006 NumAlignedDPRCS2Regs); 1007 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1008 &isARMArea2Register, 0); 1009 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 1010 &isARMArea1Register, 0); 1011 1012 return true; 1013 } 1014 1015 // FIXME: Make generic? 1016 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 1017 const ARMBaseInstrInfo &TII) { 1018 unsigned FnSize = 0; 1019 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 1020 MBBI != E; ++MBBI) { 1021 const MachineBasicBlock &MBB = *MBBI; 1022 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 1023 I != E; ++I) 1024 FnSize += TII.GetInstSizeInBytes(I); 1025 } 1026 return FnSize; 1027 } 1028 1029 /// estimateStackSize - Estimate and return the size of the frame. 1030 /// FIXME: Make generic? 1031 static unsigned estimateStackSize(MachineFunction &MF) { 1032 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1033 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 1034 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 1035 unsigned MaxAlign = MFI->getMaxAlignment(); 1036 int Offset = 0; 1037 1038 // This code is very, very similar to PEI::calculateFrameObjectOffsets(). 1039 // It really should be refactored to share code. Until then, changes 1040 // should keep in mind that there's tight coupling between the two. 1041 1042 for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) { 1043 int FixedOff = -MFI->getObjectOffset(i); 1044 if (FixedOff > Offset) Offset = FixedOff; 1045 } 1046 for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { 1047 if (MFI->isDeadObjectIndex(i)) 1048 continue; 1049 Offset += MFI->getObjectSize(i); 1050 unsigned Align = MFI->getObjectAlignment(i); 1051 // Adjust to alignment boundary 1052 Offset = (Offset+Align-1)/Align*Align; 1053 1054 MaxAlign = std::max(Align, MaxAlign); 1055 } 1056 1057 if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF)) 1058 Offset += MFI->getMaxCallFrameSize(); 1059 1060 // Round up the size to a multiple of the alignment. If the function has 1061 // any calls or alloca's, align to the target's StackAlignment value to 1062 // ensure that the callee's frame or the alloca data is suitably aligned; 1063 // otherwise, for leaf functions, align to the TransientStackAlignment 1064 // value. 1065 unsigned StackAlign; 1066 if (MFI->adjustsStack() || MFI->hasVarSizedObjects() || 1067 (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0)) 1068 StackAlign = TFI->getStackAlignment(); 1069 else 1070 StackAlign = TFI->getTransientStackAlignment(); 1071 1072 // If the frame pointer is eliminated, all frame offsets will be relative to 1073 // SP not FP. Align to MaxAlign so this works. 1074 StackAlign = std::max(StackAlign, MaxAlign); 1075 unsigned AlignMask = StackAlign - 1; 1076 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask); 1077 1078 return (unsigned)Offset; 1079 } 1080 1081 /// estimateRSStackSizeLimit - Look at each instruction that references stack 1082 /// frames and return the stack size limit beyond which some of these 1083 /// instructions will require a scratch register during their expansion later. 1084 // FIXME: Move to TII? 1085 static unsigned estimateRSStackSizeLimit(MachineFunction &MF, 1086 const TargetFrameLowering *TFI) { 1087 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1088 unsigned Limit = (1 << 12) - 1; 1089 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 1090 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 1091 I != E; ++I) { 1092 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 1093 if (!I->getOperand(i).isFI()) continue; 1094 1095 // When using ADDri to get the address of a stack object, 255 is the 1096 // largest offset guaranteed to fit in the immediate offset. 1097 if (I->getOpcode() == ARM::ADDri) { 1098 Limit = std::min(Limit, (1U << 8) - 1); 1099 break; 1100 } 1101 1102 // Otherwise check the addressing mode. 1103 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 1104 case ARMII::AddrMode3: 1105 case ARMII::AddrModeT2_i8: 1106 Limit = std::min(Limit, (1U << 8) - 1); 1107 break; 1108 case ARMII::AddrMode5: 1109 case ARMII::AddrModeT2_i8s4: 1110 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 1111 break; 1112 case ARMII::AddrModeT2_i12: 1113 // i12 supports only positive offset so these will be converted to 1114 // i8 opcodes. See llvm::rewriteT2FrameIndex. 1115 if (TFI->hasFP(MF) && AFI->hasStackFrame()) 1116 Limit = std::min(Limit, (1U << 8) - 1); 1117 break; 1118 case ARMII::AddrMode4: 1119 case ARMII::AddrMode6: 1120 // Addressing modes 4 & 6 (load/store) instructions can't encode an 1121 // immediate offset for stack references. 1122 return 0; 1123 default: 1124 break; 1125 } 1126 break; // At most one FI per instruction 1127 } 1128 } 1129 } 1130 1131 return Limit; 1132 } 1133 1134 // In functions that realign the stack, it can be an advantage to spill the 1135 // callee-saved vector registers after realigning the stack. The vst1 and vld1 1136 // instructions take alignment hints that can improve performance. 1137 // 1138 static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) { 1139 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0); 1140 if (!SpillAlignedNEONRegs) 1141 return; 1142 1143 // Naked functions don't spill callee-saved registers. 1144 if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 1145 return; 1146 1147 // We are planning to use NEON instructions vst1 / vld1. 1148 if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON()) 1149 return; 1150 1151 // Don't bother if the default stack alignment is sufficiently high. 1152 if (MF.getTarget().getFrameLowering()->getStackAlignment() >= 8) 1153 return; 1154 1155 // Aligned spills require stack realignment. 1156 const ARMBaseRegisterInfo *RegInfo = 1157 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 1158 if (!RegInfo->canRealignStack(MF)) 1159 return; 1160 1161 // We always spill contiguous d-registers starting from d8. Count how many 1162 // needs spilling. The register allocator will almost always use the 1163 // callee-saved registers in order, but it can happen that there are holes in 1164 // the range. Registers above the hole will be spilled to the standard DPRCS 1165 // area. 1166 MachineRegisterInfo &MRI = MF.getRegInfo(); 1167 unsigned NumSpills = 0; 1168 for (; NumSpills < 8; ++NumSpills) 1169 if (!MRI.isPhysRegOrOverlapUsed(ARM::D8 + NumSpills)) 1170 break; 1171 1172 // Don't do this for just one d-register. It's not worth it. 1173 if (NumSpills < 2) 1174 return; 1175 1176 // Spill the first NumSpills D-registers after realigning the stack. 1177 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills); 1178 1179 // A scratch register is required for the vst1 / vld1 instructions. 1180 MF.getRegInfo().setPhysRegUsed(ARM::R4); 1181 } 1182 1183 void 1184 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1185 RegScavenger *RS) const { 1186 // This tells PEI to spill the FP as if it is any other callee-save register 1187 // to take advantage the eliminateFrameIndex machinery. This also ensures it 1188 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 1189 // to combine multiple loads / stores. 1190 bool CanEliminateFrame = true; 1191 bool CS1Spilled = false; 1192 bool LRSpilled = false; 1193 unsigned NumGPRSpills = 0; 1194 SmallVector<unsigned, 4> UnspilledCS1GPRs; 1195 SmallVector<unsigned, 4> UnspilledCS2GPRs; 1196 const ARMBaseRegisterInfo *RegInfo = 1197 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 1198 const ARMBaseInstrInfo &TII = 1199 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 1200 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1201 MachineFrameInfo *MFI = MF.getFrameInfo(); 1202 unsigned FramePtr = RegInfo->getFrameRegister(MF); 1203 1204 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 1205 // scratch register. Also spill R4 if Thumb2 function has varsized objects, 1206 // since it's not always possible to restore sp from fp in a single 1207 // instruction. 1208 // FIXME: It will be better just to find spare register here. 1209 if (AFI->isThumb2Function() && 1210 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) 1211 MF.getRegInfo().setPhysRegUsed(ARM::R4); 1212 1213 if (AFI->isThumb1OnlyFunction()) { 1214 // Spill LR if Thumb1 function uses variable length argument lists. 1215 if (AFI->getVarArgsRegSaveSize() > 0) 1216 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1217 1218 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know 1219 // for sure what the stack size will be, but for this, an estimate is good 1220 // enough. If there anything changes it, it'll be a spill, which implies 1221 // we've used all the registers and so R4 is already used, so not marking 1222 // it here will be OK. 1223 // FIXME: It will be better just to find spare register here. 1224 unsigned StackSize = estimateStackSize(MF); 1225 if (MFI->hasVarSizedObjects() || StackSize > 508) 1226 MF.getRegInfo().setPhysRegUsed(ARM::R4); 1227 } 1228 1229 // See if we can spill vector registers to aligned stack. 1230 checkNumAlignedDPRCS2Regs(MF); 1231 1232 // Spill the BasePtr if it's used. 1233 if (RegInfo->hasBasePointer(MF)) 1234 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); 1235 1236 // Don't spill FP if the frame can be eliminated. This is determined 1237 // by scanning the callee-save registers to see if any is used. 1238 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(); 1239 for (unsigned i = 0; CSRegs[i]; ++i) { 1240 unsigned Reg = CSRegs[i]; 1241 bool Spilled = false; 1242 if (MF.getRegInfo().isPhysRegOrOverlapUsed(Reg)) { 1243 Spilled = true; 1244 CanEliminateFrame = false; 1245 } 1246 1247 if (!ARM::GPRRegisterClass->contains(Reg)) 1248 continue; 1249 1250 if (Spilled) { 1251 NumGPRSpills++; 1252 1253 if (!STI.isTargetIOS()) { 1254 if (Reg == ARM::LR) 1255 LRSpilled = true; 1256 CS1Spilled = true; 1257 continue; 1258 } 1259 1260 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 1261 switch (Reg) { 1262 case ARM::LR: 1263 LRSpilled = true; 1264 // Fallthrough 1265 case ARM::R4: case ARM::R5: 1266 case ARM::R6: case ARM::R7: 1267 CS1Spilled = true; 1268 break; 1269 default: 1270 break; 1271 } 1272 } else { 1273 if (!STI.isTargetIOS()) { 1274 UnspilledCS1GPRs.push_back(Reg); 1275 continue; 1276 } 1277 1278 switch (Reg) { 1279 case ARM::R4: case ARM::R5: 1280 case ARM::R6: case ARM::R7: 1281 case ARM::LR: 1282 UnspilledCS1GPRs.push_back(Reg); 1283 break; 1284 default: 1285 UnspilledCS2GPRs.push_back(Reg); 1286 break; 1287 } 1288 } 1289 } 1290 1291 bool ForceLRSpill = false; 1292 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 1293 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 1294 // Force LR to be spilled if the Thumb function size is > 2048. This enables 1295 // use of BL to implement far jump. If it turns out that it's not needed 1296 // then the branch fix up path will undo it. 1297 if (FnSize >= (1 << 11)) { 1298 CanEliminateFrame = false; 1299 ForceLRSpill = true; 1300 } 1301 } 1302 1303 // If any of the stack slot references may be out of range of an immediate 1304 // offset, make sure a register (or a spill slot) is available for the 1305 // register scavenger. Note that if we're indexing off the frame pointer, the 1306 // effective stack size is 4 bytes larger since the FP points to the stack 1307 // slot of the previous FP. Also, if we have variable sized objects in the 1308 // function, stack slot references will often be negative, and some of 1309 // our instructions are positive-offset only, so conservatively consider 1310 // that case to want a spill slot (or register) as well. Similarly, if 1311 // the function adjusts the stack pointer during execution and the 1312 // adjustments aren't already part of our stack size estimate, our offset 1313 // calculations may be off, so be conservative. 1314 // FIXME: We could add logic to be more precise about negative offsets 1315 // and which instructions will need a scratch register for them. Is it 1316 // worth the effort and added fragility? 1317 bool BigStack = 1318 (RS && 1319 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= 1320 estimateRSStackSizeLimit(MF, this))) 1321 || MFI->hasVarSizedObjects() 1322 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 1323 1324 bool ExtraCSSpill = false; 1325 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { 1326 AFI->setHasStackFrame(true); 1327 1328 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1329 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1330 if (!LRSpilled && CS1Spilled) { 1331 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1332 NumGPRSpills++; 1333 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1334 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1335 ForceLRSpill = false; 1336 ExtraCSSpill = true; 1337 } 1338 1339 if (hasFP(MF)) { 1340 MF.getRegInfo().setPhysRegUsed(FramePtr); 1341 NumGPRSpills++; 1342 } 1343 1344 // If stack and double are 8-byte aligned and we are spilling an odd number 1345 // of GPRs, spill one extra callee save GPR so we won't have to pad between 1346 // the integer and double callee save areas. 1347 unsigned TargetAlign = getStackAlignment(); 1348 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1349 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1350 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1351 unsigned Reg = UnspilledCS1GPRs[i]; 1352 // Don't spill high register if the function is thumb1 1353 if (!AFI->isThumb1OnlyFunction() || 1354 isARMLowRegister(Reg) || Reg == ARM::LR) { 1355 MF.getRegInfo().setPhysRegUsed(Reg); 1356 if (!RegInfo->isReservedReg(MF, Reg)) 1357 ExtraCSSpill = true; 1358 break; 1359 } 1360 } 1361 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { 1362 unsigned Reg = UnspilledCS2GPRs.front(); 1363 MF.getRegInfo().setPhysRegUsed(Reg); 1364 if (!RegInfo->isReservedReg(MF, Reg)) 1365 ExtraCSSpill = true; 1366 } 1367 } 1368 1369 // Estimate if we might need to scavenge a register at some point in order 1370 // to materialize a stack offset. If so, either spill one additional 1371 // callee-saved register or reserve a special spill slot to facilitate 1372 // register scavenging. Thumb1 needs a spill slot for stack pointer 1373 // adjustments also, even when the frame itself is small. 1374 if (BigStack && !ExtraCSSpill) { 1375 // If any non-reserved CS register isn't spilled, just spill one or two 1376 // extra. That should take care of it! 1377 unsigned NumExtras = TargetAlign / 4; 1378 SmallVector<unsigned, 2> Extras; 1379 while (NumExtras && !UnspilledCS1GPRs.empty()) { 1380 unsigned Reg = UnspilledCS1GPRs.back(); 1381 UnspilledCS1GPRs.pop_back(); 1382 if (!RegInfo->isReservedReg(MF, Reg) && 1383 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 1384 Reg == ARM::LR)) { 1385 Extras.push_back(Reg); 1386 NumExtras--; 1387 } 1388 } 1389 // For non-Thumb1 functions, also check for hi-reg CS registers 1390 if (!AFI->isThumb1OnlyFunction()) { 1391 while (NumExtras && !UnspilledCS2GPRs.empty()) { 1392 unsigned Reg = UnspilledCS2GPRs.back(); 1393 UnspilledCS2GPRs.pop_back(); 1394 if (!RegInfo->isReservedReg(MF, Reg)) { 1395 Extras.push_back(Reg); 1396 NumExtras--; 1397 } 1398 } 1399 } 1400 if (Extras.size() && NumExtras == 0) { 1401 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1402 MF.getRegInfo().setPhysRegUsed(Extras[i]); 1403 } 1404 } else if (!AFI->isThumb1OnlyFunction()) { 1405 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 1406 // closest to SP or frame pointer. 1407 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 1408 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1409 RC->getAlignment(), 1410 false)); 1411 } 1412 } 1413 } 1414 1415 if (ForceLRSpill) { 1416 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1417 AFI->setLRIsSpilledForFarJump(true); 1418 } 1419 } 1420
