1 //=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes an abstract interface used to get information about a 11 // target machines register file. This information is used for a variety of 12 // purposed, especially register allocation. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_MC_MCREGISTERINFO_H 17 #define LLVM_MC_MCREGISTERINFO_H 18 19 #include "llvm/ADT/DenseMap.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include <cassert> 22 23 namespace llvm { 24 25 /// MCRegisterClass - Base class of TargetRegisterClass. 26 class MCRegisterClass { 27 public: 28 typedef const uint16_t* iterator; 29 typedef const uint16_t* const_iterator; 30 31 const char *Name; 32 const iterator RegsBegin; 33 const uint8_t *const RegSet; 34 const uint16_t RegsSize; 35 const uint16_t RegSetSize; 36 const uint16_t ID; 37 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 38 const int8_t CopyCost; 39 const bool Allocatable; 40 41 /// getID() - Return the register class ID number. 42 /// 43 unsigned getID() const { return ID; } 44 45 /// getName() - Return the register class name for debugging. 46 /// 47 const char *getName() const { return Name; } 48 49 /// begin/end - Return all of the registers in this class. 50 /// 51 iterator begin() const { return RegsBegin; } 52 iterator end() const { return RegsBegin + RegsSize; } 53 54 /// getNumRegs - Return the number of registers in this class. 55 /// 56 unsigned getNumRegs() const { return RegsSize; } 57 58 /// getRegister - Return the specified register in the class. 59 /// 60 unsigned getRegister(unsigned i) const { 61 assert(i < getNumRegs() && "Register number out of range!"); 62 return RegsBegin[i]; 63 } 64 65 /// contains - Return true if the specified register is included in this 66 /// register class. This does not include virtual registers. 67 bool contains(unsigned Reg) const { 68 unsigned InByte = Reg % 8; 69 unsigned Byte = Reg / 8; 70 if (Byte >= RegSetSize) 71 return false; 72 return (RegSet[Byte] & (1 << InByte)) != 0; 73 } 74 75 /// contains - Return true if both registers are in this class. 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 78 } 79 80 /// getSize - Return the size of the register in bytes, which is also the size 81 /// of a stack slot allocated to hold a spilled copy of this register. 82 unsigned getSize() const { return RegSize; } 83 84 /// getAlignment - Return the minimum required alignment for a register of 85 /// this class. 86 unsigned getAlignment() const { return Alignment; } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96 }; 97 98 /// MCRegisterDesc - This record contains all of the information known about 99 /// a particular register. The Overlaps field contains a pointer to a zero 100 /// terminated array of registers that this register aliases, starting with 101 /// itself. This is needed for architectures like X86 which have AL alias AX 102 /// alias EAX. The SubRegs field is a zero terminated array of registers that 103 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 104 /// AX. The SuperRegs field is a zero terminated array of registers that are 105 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers 106 /// of AX. 107 /// 108 struct MCRegisterDesc { 109 const char *Name; // Printable name for the reg (for debugging) 110 uint32_t Overlaps; // Overlapping registers, described above 111 uint32_t SubRegs; // Sub-register set, described above 112 uint32_t SuperRegs; // Super-register set, described above 113 }; 114 115 /// MCRegisterInfo base class - We assume that the target defines a static 116 /// array of MCRegisterDesc objects that represent all of the machine 117 /// registers that the target has. As such, we simply have to track a pointer 118 /// to this array so that we can turn register number into a register 119 /// descriptor. 120 /// 121 /// Note this class is designed to be a base class of TargetRegisterInfo, which 122 /// is the interface used by codegen. However, specific targets *should never* 123 /// specialize this class. MCRegisterInfo should only contain getters to access 124 /// TableGen generated physical register data. It must not be extended with 125 /// virtual methods. 126 /// 127 class MCRegisterInfo { 128 public: 129 typedef const MCRegisterClass *regclass_iterator; 130 131 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 132 /// performed with a binary search. 133 struct DwarfLLVMRegPair { 134 unsigned FromReg; 135 unsigned ToReg; 136 137 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 138 }; 139 private: 140 const MCRegisterDesc *Desc; // Pointer to the descriptor array 141 unsigned NumRegs; // Number of entries in the array 142 unsigned RAReg; // Return address register 143 const MCRegisterClass *Classes; // Pointer to the regclass array 144 unsigned NumClasses; // Number of entries in the array 145 const uint16_t *RegLists; // Pointer to the reglists array 146 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 147 // array. 148 unsigned NumSubRegIndices; // Number of subreg indices. 149 150 unsigned L2DwarfRegsSize; 151 unsigned EHL2DwarfRegsSize; 152 unsigned Dwarf2LRegsSize; 153 unsigned EHDwarf2LRegsSize; 154 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 155 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 156 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 157 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 158 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 159 160 public: 161 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 162 /// auto-generated routines. *DO NOT USE*. 163 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 164 const MCRegisterClass *C, unsigned NC, 165 const uint16_t *RL, 166 const uint16_t *SubIndices, 167 unsigned NumIndices) { 168 Desc = D; 169 NumRegs = NR; 170 RAReg = RA; 171 Classes = C; 172 RegLists = RL; 173 NumClasses = NC; 174 SubRegIndices = SubIndices; 175 NumSubRegIndices = NumIndices; 176 } 177 178 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf 179 /// register number mapping. Called by TableGen auto-generated routines. 180 /// *DO NOT USE*. 181 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 182 bool isEH) { 183 if (isEH) { 184 EHL2DwarfRegs = Map; 185 EHL2DwarfRegsSize = Size; 186 } else { 187 L2DwarfRegs = Map; 188 L2DwarfRegsSize = Size; 189 } 190 } 191 192 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM 193 /// register number mapping. Called by TableGen auto-generated routines. 194 /// *DO NOT USE*. 195 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 196 bool isEH) { 197 if (isEH) { 198 EHDwarf2LRegs = Map; 199 EHDwarf2LRegsSize = Size; 200 } else { 201 Dwarf2LRegs = Map; 202 Dwarf2LRegsSize = Size; 203 } 204 } 205 206 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 207 /// number mapping. By default the SEH register number is just the same 208 /// as the LLVM register number. 209 /// FIXME: TableGen these numbers. Currently this requires target specific 210 /// initialization code. 211 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 212 L2SEHRegs[LLVMReg] = SEHReg; 213 } 214 215 /// getRARegister - This method should return the register where the return 216 /// address can be found. 217 unsigned getRARegister() const { 218 return RAReg; 219 } 220 221 const MCRegisterDesc &operator[](unsigned RegNo) const { 222 assert(RegNo < NumRegs && 223 "Attempting to access record for invalid register number!"); 224 return Desc[RegNo]; 225 } 226 227 /// Provide a get method, equivalent to [], but more useful if we have a 228 /// pointer to this object. 229 /// 230 const MCRegisterDesc &get(unsigned RegNo) const { 231 return operator[](RegNo); 232 } 233 234 /// getAliasSet - Return the set of registers aliased by the specified 235 /// register, or a null list of there are none. The list returned is zero 236 /// terminated. 237 /// 238 const uint16_t *getAliasSet(unsigned RegNo) const { 239 // The Overlaps set always begins with Reg itself. 240 return RegLists + get(RegNo).Overlaps + 1; 241 } 242 243 /// getOverlaps - Return a list of registers that overlap Reg, including 244 /// itself. This is the same as the alias set except Reg is included in the 245 /// list. 246 /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 247 /// 248 const uint16_t *getOverlaps(unsigned RegNo) const { 249 return RegLists + get(RegNo).Overlaps; 250 } 251 252 /// getSubRegisters - Return the list of registers that are sub-registers of 253 /// the specified register, or a null list of there are none. The list 254 /// returned is zero terminated and sorted according to super-sub register 255 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 256 /// 257 const uint16_t *getSubRegisters(unsigned RegNo) const { 258 return RegLists + get(RegNo).SubRegs; 259 } 260 261 /// getSubReg - Returns the physical register number of sub-register "Index" 262 /// for physical register RegNo. Return zero if the sub-register does not 263 /// exist. 264 unsigned getSubReg(unsigned Reg, unsigned Idx) const { 265 return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1); 266 } 267 268 /// getMatchingSuperReg - Return a super-register of the specified register 269 /// Reg so its sub-register of index SubIdx is Reg. 270 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 271 const MCRegisterClass *RC) const { 272 for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 273 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 274 return SR; 275 return 0; 276 } 277 278 /// getSubRegIndex - For a given register pair, return the sub-register index 279 /// if the second register is a sub-register of the first. Return zero 280 /// otherwise. 281 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { 282 for (unsigned I = 1; I <= NumSubRegIndices; ++I) 283 if (getSubReg(RegNo, I) == SubRegNo) 284 return I; 285 return 0; 286 } 287 288 /// getSuperRegisters - Return the list of registers that are super-registers 289 /// of the specified register, or a null list of there are none. The list 290 /// returned is zero terminated and sorted according to super-sub register 291 /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. 292 /// 293 const uint16_t *getSuperRegisters(unsigned RegNo) const { 294 return RegLists + get(RegNo).SuperRegs; 295 } 296 297 /// getName - Return the human-readable symbolic target-specific name for the 298 /// specified physical register. 299 const char *getName(unsigned RegNo) const { 300 return get(RegNo).Name; 301 } 302 303 /// getNumRegs - Return the number of registers this target has (useful for 304 /// sizing arrays holding per register information) 305 unsigned getNumRegs() const { 306 return NumRegs; 307 } 308 309 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 310 /// number. Returns -1 if there is no equivalent value. The second 311 /// parameter allows targets to use different numberings for EH info and 312 /// debugging info. 313 int getDwarfRegNum(unsigned RegNum, bool isEH) const { 314 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs; 315 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize; 316 317 DwarfLLVMRegPair Key = { RegNum, 0 }; 318 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 319 if (I == M+Size || I->FromReg != RegNum) 320 return -1; 321 return I->ToReg; 322 } 323 324 /// getLLVMRegNum - Map a dwarf register back to a target register. 325 /// 326 int getLLVMRegNum(unsigned RegNum, bool isEH) const { 327 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; 328 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize; 329 330 DwarfLLVMRegPair Key = { RegNum, 0 }; 331 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); 332 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); 333 return I->ToReg; 334 } 335 336 /// getSEHRegNum - Map a target register to an equivalent SEH register 337 /// number. Returns LLVM register number if there is no equivalent value. 338 int getSEHRegNum(unsigned RegNum) const { 339 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); 340 if (I == L2SEHRegs.end()) return (int)RegNum; 341 return I->second; 342 } 343 344 regclass_iterator regclass_begin() const { return Classes; } 345 regclass_iterator regclass_end() const { return Classes+NumClasses; } 346 347 unsigned getNumRegClasses() const { 348 return (unsigned)(regclass_end()-regclass_begin()); 349 } 350 351 /// getRegClass - Returns the register class associated with the enumeration 352 /// value. See class MCOperandInfo. 353 const MCRegisterClass getRegClass(unsigned i) const { 354 assert(i < getNumRegClasses() && "Register Class ID out of range"); 355 return Classes[i]; 356 } 357 }; 358 359 } // End llvm namespace 360 361 #endif 362
