| /external/llvm/lib/Target/PTX/ |
| PTXRegisterInfo.h | 42 BitVector Reserved(getNumRegs());
|
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 24 UsedPhysRegs.resize(TRI.getNumRegs());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
59 if (NewRC->getNumRegs() < MinNumRegs)
|
| RegisterClassInfo.cpp | 51 CSRNum.resize(TRI->getNumRegs(), 0);
78 unsigned NumRegs = RC->getNumRegs();
|
| CriticalAntiDepBreaker.cpp | 36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
37 KillIndices(TRI->getNumRegs(), 0),
38 DefIndices(TRI->getNumRegs(), 0),
39 KeepRegs(TRI->getNumRegs(), false) {}
46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
134 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
260 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
464 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
518 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
|
| RegisterScavenging.cpp | 83 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
93 NumPhysRegs = TRI->getNumRegs();
251 BitVector Mask(TRI->getNumRegs());
|
| ExecutionDepsFix.cpp | 149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
647 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
667 AliasMap.resize(TRI->getNumRegs(), -1);
668 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
|
| AggressiveAntiDepBreaker.cpp | 149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
515 BitVector BV(TRI->getNumRegs(), false);
767 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
[all...] |
| CallingConvLower.cpp | 36 UsedRegs.resize((TRI.getNumRegs()+31)/32);
|
| InterferenceCache.cpp | 33 PhysRegEntries.assign(TRI->getNumRegs(), 0);
|
| VirtRegMap.cpp | 206 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
|
| PostRASchedulerList.cpp | 203 LiveRegs(TRI->getNumRegs())
490 BitVector killedRegs(TRI->getNumRegs());
|
| RegAllocBase.cpp | 108 const unsigned NumRegs = TRI->getNumRegs();
|
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 37 else if (TRI && Reg < TRI->getNumRegs())
81 BitVector Allocatable(getNumRegs());
|
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmLexer.cpp | 41 unsigned numRegs = info->getNumRegs();
|
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize; }
61 assert(i < getNumRegs() && "Register number out of range!");
303 /// getNumRegs - Return the number of registers this target has (useful for
305 unsigned getNumRegs() const {
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 63 /// getNumRegs - Return the number of registers in this class.
65 unsigned getNumRegs() const { return MC->getNumRegs(); }
194 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
369 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmLexer.cpp | 43 unsigned numRegs = info->getNumRegs();
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeRegisterInfo.cpp | 72 BitVector Reserved(getNumRegs());
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 43 BitVector Reserved(getNumRegs());
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 35 UsedRegs.resize((TRI.getNumRegs()+31)/32);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 78 BitVector Reserved(getNumRegs());
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 96 BitVector Reserved(getNumRegs());
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 115 LiveRegDefs.resize(TRI->getNumRegs(), NULL);
116 LiveRegCycles.resize(TRI->getNumRegs(), 0);
|
| /external/llvm/lib/MC/MCDisassembler/ |
| EDDisassembler.cpp | 255 unsigned numRegisters = registerInfo.getNumRegs();
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 231 BitVector Reserved(getNumRegs());
|
