| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 197 /// index DefIdx can be bypassed when it's read by an instruction of
199 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
203 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
205 if (Forwardings[FirstDefIdx + DefIdx] == 0)
213 return Forwardings[FirstDefIdx + DefIdx] ==
220 int getOperandLatency(unsigned DefClass, unsigned DefIdx,
225 int DefCycle = getOperandCycle(DefClass, DefIdx);
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
|
| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 65 const MachineInstr *DefMI, unsigned DefIdx,
72 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
86 unsigned DefIdx) const {
91 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 211 const MachineInstr *DefMI, unsigned DefIdx,
215 SDNode *DefNode, unsigned DefIdx,
219 const MachineInstr *DefMI, unsigned DefIdx,
233 unsigned DefIdx, unsigned DefAlign) const;
237 unsigned DefIdx, unsigned DefAlign) const;
248 unsigned DefIdx, unsigned DefAlign,
260 const MachineInstr *DefMI, unsigned DefIdx,
263 const MachineInstr *DefMI, unsigned DefIdx) const;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 140 unsigned DefIdx;
158 return DefIdx-1;
|
| ScheduleDAGSDNodes.cpp | 515 DefIdx = 0;
521 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
529 for (;DefIdx < NodeNumDefs; ++DefIdx) {
530 if (!Node->hasAnyUseOfValue(DefIdx))
532 ValueType = Node->getValueType(DefIdx);
533 ++DefIdx;
595 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
599 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
|
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 111 SlotIndex DefIdx;
113 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
115 DefIdx = RM.ParentVNI->def;
116 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
125 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
|
| RegisterCoalescer.cpp | 628 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
629 assert(DefIdx != -1);
631 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
738 SlotIndex DefIdx = UseIdx.getRegSlot();
739 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
742 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
743 assert(DVNI->def == DefIdx);
[all...] |
| ScheduleDAGInstrs.cpp | 765 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
766 if (DefIdx != -1) {
767 const MachineOperand &MO = DefMI->getOperand(DefIdx);
769 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
778 DefIdx = Op2;
792 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
801 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
[all...] |
| MachineInstr.cpp | [all...] |
| TargetInstrInfoImpl.cpp | 514 SDNode *DefNode, unsigned DefIdx,
524 return ItinData->getOperandCycle(DefClass, DefIdx);
526 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
| InlineSpiller.cpp | 890 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
[all...] |
| MachineVerifier.cpp | 765 unsigned defIdx;
766 if (MI->isRegTiedToDefOperand(MONum, &defIdx)) {
768 unsigned DefReg = MI->getOperand(defIdx).getReg();
844 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI).getRegSlot();
847 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
849 if (VNI->def != DefIdx && !MO->isEarlyClobber()) {
852 << DefIdx << " in " << LI << '\n';
856 *OS << DefIdx << " is not live in " << LI << '\n';
[all...] |
| MachineLICM.cpp | 200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
[all...] |
| RegAllocFast.cpp | 725 unsigned DefIdx = 0;
726 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
728 << DefIdx << ".\n");
[all...] |
| LiveIntervalAnalysis.cpp | 399 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
400 if (DefIdx != -1) {
401 if (mi->isRegTiedToUseOperand(DefIdx)) {
403 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
531 SlotIndex defIdx = getMBBStartIdx(MBB);
532 assert(getInstructionFromIndex(defIdx) == 0 &&
534 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 661 const MachineInstr *DefMI, unsigned DefIdx,
665 SDNode *DefNode, unsigned DefIdx,
672 const MachineInstr *DefMI, unsigned DefIdx,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 363 const MachineInstr *DefMI, unsigned DefIdx,
|
| X86InstrInfo.cpp | [all...] |
