| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 28 namespace RegState {
63 flags & RegState::Define,
64 flags & RegState::Implicit,
65 flags & RegState::Kill,
66 flags & RegState::Dead,
67 flags & RegState::Undef,
68 flags & RegState::EarlyClobber,
70 flags & RegState::Debug));
201 .addReg(DestReg, RegState::Define);
215 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 219 .addReg(StackReg, RegState::Kill)
226 .addReg(TmpReg, RegState::Kill)
229 .addReg(StackReg, RegState::Kill)
325 .addReg(Reg, RegState::Kill)
326 .addReg(PPC::X1, RegState::Define)
330 .addReg(PPC::X0, RegState::Kill)
331 .addReg(PPC::X1, RegState::Define)
343 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
346 .addReg(Reg, RegState::Kill)
347 .addReg(PPC::R1, RegState::Define
[all...] |
| PPCFrameLowering.cpp | 141 .addReg(SrcReg, RegState::Kill)
150 .addReg(SrcReg, RegState::Kill)
159 .addReg(SrcReg, RegState::Kill)
163 .addReg(DstReg, RegState::Kill)
367 .addReg(PPC::R0, RegState::Kill)
370 .addReg(PPC::R1, RegState::Kill)
371 .addReg(PPC::R1, RegState::Define)
382 .addReg(PPC::R0, RegState::Kill)
385 .addReg(PPC::R1, RegState::Kill)
386 .addReg(PPC::R1, RegState::Define
[all...] |
| PPCInstrInfo.cpp | 161 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 621 .addReg(Reg, RegState::Debug).addImm(Offset)
655 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
[all...] |
| SelectionDAGISel.cpp | 408 .addReg(LDI->second, RegState::Debug)
429 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 122 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
247 .addReg(BaseReg, RegState::Kill))
292 .addReg(DestReg, RegState::Kill)
361 .addReg(DestReg, RegState::Kill));
560 .addReg(ARM::R12, RegState::Define)
561 .addReg(Reg, RegState::Kill));
590 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill))
[all...] |
| ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
521 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
523 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
525 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
527 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead))
[all...] |
| ARMFrameLowering.cpp | 292 .addReg(ARM::SP, RegState::Kill)
302 .addReg(ARM::SP, RegState::Kill));
305 .addReg(ARM::R4, RegState::Kill)
308 .addReg(ARM::R4, RegState::Kill));
450 addReg(JumpTarget.getReg(), RegState::Kill);
698 .addReg(ARM::SP, RegState::Define)
771 .addReg(ARM::R4, RegState::Kill)
797 .addReg(ARM::R4, RegState::Kill).addImm(16)
799 .addReg(SupReg, RegState::ImplicitKill));
815 .addReg(SupReg, RegState::ImplicitKill))
[all...] |
| Thumb2InstrInfo.cpp | 209 .addReg(BaseReg, RegState::Kill)
210 .addReg(DestReg, RegState::Kill)
215 .addReg(DestReg, RegState::Kill)
216 .addReg(BaseReg, RegState::Kill)
281 .addReg(BaseReg, RegState::Kill)
|
| ARMFastISel.cpp | 305 .addReg(Op0, Op0IsKill * RegState::Kill));
308 .addReg(Op0, Op0IsKill * RegState::Kill));
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill));
348 .addReg(Op0, Op0IsKill * RegState::Kill)
349 .addReg(Op1, Op1IsKill * RegState::Kill)
350 .addReg(Op2, Op2IsKill * RegState::Kill));
353 .addReg(Op0, Op0IsKill * RegState::Kill
[all...] |
| Thumb1FrameLowering.cpp | 276 .addReg(ARM::R3, RegState::Define);
282 .addReg(ARM::R3, RegState::Kill);
|
| ARMBaseInstrInfo.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
944 .addReg(Base, RegState::Define)
949 .addReg(Base, RegState::Define)
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 227 .addReg(ScratchReg, RegState::Kill);
233 .addReg(ScratchReg, RegState::Kill);
238 .addReg(ScratchReg, RegState::Kill);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill);
200 .addReg(Reg, RegState::Kill);
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 736 .addReg(FramePtr, RegState::Kill)
873 .addReg(X86::EAX, RegState::Kill)
894 .addReg(StackPtr, RegState::Define | RegState::Implicit)
895 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
[all...] |
| X86FloatingPoint.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.cpp | 303 .addReg(tmpReg, RegState::Kill)
|
| /external/llvm/lib/CodeGen/ |
| RegAllocFast.cpp | 93 // RegState - Track the state of a physical register.
94 enum RegState {
113 // PhysRegState - One of the RegState enums, or a virtreg.
160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
236 "Broken RegState mapping");
266 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
395 RegState NewState) {
[all...] |
| TargetInstrInfoImpl.cpp | 106 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead), SubReg0)
|
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 162 MIB.addReg(DestReg, RegState::Define);
|
