1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the pass which converts floating point instructions from 11 // pseudo registers into register stack instructions. This pass uses live 12 // variable information to indicate where the FPn registers are used and their 13 // lifetimes. 14 // 15 // The x87 hardware tracks liveness of the stack registers, so it is necessary 16 // to implement exact liveness tracking between basic blocks. The CFG edges are 17 // partitioned into bundles where the same FP registers must be live in 18 // identical stack positions. Instructions are inserted at the end of each basic 19 // block to rearrange the live registers to match the outgoing bundle. 20 // 21 // This approach avoids splitting critical edges at the potential cost of more 22 // live register shuffling instructions when critical edges are present. 23 // 24 //===----------------------------------------------------------------------===// 25 26 #define DEBUG_TYPE "x86-codegen" 27 #include "X86.h" 28 #include "X86InstrInfo.h" 29 #include "llvm/InlineAsm.h" 30 #include "llvm/ADT/DepthFirstIterator.h" 31 #include "llvm/ADT/SmallPtrSet.h" 32 #include "llvm/ADT/SmallVector.h" 33 #include "llvm/ADT/Statistic.h" 34 #include "llvm/ADT/STLExtras.h" 35 #include "llvm/CodeGen/EdgeBundles.h" 36 #include "llvm/CodeGen/MachineFunctionPass.h" 37 #include "llvm/CodeGen/MachineInstrBuilder.h" 38 #include "llvm/CodeGen/MachineRegisterInfo.h" 39 #include "llvm/CodeGen/Passes.h" 40 #include "llvm/Support/Debug.h" 41 #include "llvm/Support/ErrorHandling.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/Target/TargetInstrInfo.h" 44 #include "llvm/Target/TargetMachine.h" 45 #include <algorithm> 46 using namespace llvm; 47 48 STATISTIC(NumFXCH, "Number of fxch instructions inserted"); 49 STATISTIC(NumFP , "Number of floating point instructions"); 50 51 namespace { 52 struct FPS : public MachineFunctionPass { 53 static char ID; 54 FPS() : MachineFunctionPass(ID) { 55 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry()); 56 // This is really only to keep valgrind quiet. 57 // The logic in isLive() is too much for it. 58 memset(Stack, 0, sizeof(Stack)); 59 memset(RegMap, 0, sizeof(RegMap)); 60 } 61 62 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 63 AU.setPreservesCFG(); 64 AU.addRequired<EdgeBundles>(); 65 AU.addPreservedID(MachineLoopInfoID); 66 AU.addPreservedID(MachineDominatorsID); 67 MachineFunctionPass::getAnalysisUsage(AU); 68 } 69 70 virtual bool runOnMachineFunction(MachineFunction &MF); 71 72 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 73 74 private: 75 const TargetInstrInfo *TII; // Machine instruction info. 76 77 // Two CFG edges are related if they leave the same block, or enter the same 78 // block. The transitive closure of an edge under this relation is a 79 // LiveBundle. It represents a set of CFG edges where the live FP stack 80 // registers must be allocated identically in the x87 stack. 81 // 82 // A LiveBundle is usually all the edges leaving a block, or all the edges 83 // entering a block, but it can contain more edges if critical edges are 84 // present. 85 // 86 // The set of live FP registers in a LiveBundle is calculated by bundleCFG, 87 // but the exact mapping of FP registers to stack slots is fixed later. 88 struct LiveBundle { 89 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c. 90 unsigned Mask; 91 92 // Number of pre-assigned live registers in FixStack. This is 0 when the 93 // stack order has not yet been fixed. 94 unsigned FixCount; 95 96 // Assigned stack order for live-in registers. 97 // FixStack[i] == getStackEntry(i) for all i < FixCount. 98 unsigned char FixStack[8]; 99 100 LiveBundle() : Mask(0), FixCount(0) {} 101 102 // Have the live registers been assigned a stack order yet? 103 bool isFixed() const { return !Mask || FixCount; } 104 }; 105 106 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges 107 // with no live FP registers. 108 SmallVector<LiveBundle, 8> LiveBundles; 109 110 // The edge bundle analysis provides indices into the LiveBundles vector. 111 EdgeBundles *Bundles; 112 113 // Return a bitmask of FP registers in block's live-in list. 114 unsigned calcLiveInMask(MachineBasicBlock *MBB) { 115 unsigned Mask = 0; 116 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 117 E = MBB->livein_end(); I != E; ++I) { 118 unsigned Reg = *I - X86::FP0; 119 if (Reg < 8) 120 Mask |= 1 << Reg; 121 } 122 return Mask; 123 } 124 125 // Partition all the CFG edges into LiveBundles. 126 void bundleCFG(MachineFunction &MF); 127 128 MachineBasicBlock *MBB; // Current basic block 129 130 // The hardware keeps track of how many FP registers are live, so we have 131 // to model that exactly. Usually, each live register corresponds to an 132 // FP<n> register, but when dealing with calls, returns, and inline 133 // assembly, it is sometimes neccesary to have live scratch registers. 134 unsigned Stack[8]; // FP<n> Registers in each stack slot... 135 unsigned StackTop; // The current top of the FP stack. 136 137 enum { 138 NumFPRegs = 16 // Including scratch pseudo-registers. 139 }; 140 141 // For each live FP<n> register, point to its Stack[] entry. 142 // The first entries correspond to FP0-FP6, the rest are scratch registers 143 // used when we need slightly different live registers than what the 144 // register allocator thinks. 145 unsigned RegMap[NumFPRegs]; 146 147 // Pending fixed registers - Inline assembly needs FP registers to appear 148 // in fixed stack slot positions. This is handled by copying FP registers 149 // to ST registers before the instruction, and copying back after the 150 // instruction. 151 // 152 // This is modeled with pending ST registers. NumPendingSTs is the number 153 // of ST registers (ST0-STn) we are tracking. PendingST[n] points to an FP 154 // register that holds the ST value. The ST registers are not moved into 155 // place until immediately before the instruction that needs them. 156 // 157 // It can happen that we need an ST register to be live when no FP register 158 // holds the value: 159 // 160 // %ST0 = COPY %FP4<kill> 161 // 162 // When that happens, we allocate a scratch FP register to hold the ST 163 // value. That means every register in PendingST must be live. 164 165 unsigned NumPendingSTs; 166 unsigned char PendingST[8]; 167 168 // Set up our stack model to match the incoming registers to MBB. 169 void setupBlockStack(); 170 171 // Shuffle live registers to match the expectations of successor blocks. 172 void finishBlockStack(); 173 174 void dumpStack() const { 175 dbgs() << "Stack contents:"; 176 for (unsigned i = 0; i != StackTop; ++i) { 177 dbgs() << " FP" << Stack[i]; 178 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 179 } 180 for (unsigned i = 0; i != NumPendingSTs; ++i) 181 dbgs() << ", ST" << i << " in FP" << unsigned(PendingST[i]); 182 dbgs() << "\n"; 183 } 184 185 /// getSlot - Return the stack slot number a particular register number is 186 /// in. 187 unsigned getSlot(unsigned RegNo) const { 188 assert(RegNo < NumFPRegs && "Regno out of range!"); 189 return RegMap[RegNo]; 190 } 191 192 /// isLive - Is RegNo currently live in the stack? 193 bool isLive(unsigned RegNo) const { 194 unsigned Slot = getSlot(RegNo); 195 return Slot < StackTop && Stack[Slot] == RegNo; 196 } 197 198 /// getScratchReg - Return an FP register that is not currently in use. 199 unsigned getScratchReg() { 200 for (int i = NumFPRegs - 1; i >= 8; --i) 201 if (!isLive(i)) 202 return i; 203 llvm_unreachable("Ran out of scratch FP registers"); 204 } 205 206 /// isScratchReg - Returns trus if RegNo is a scratch FP register. 207 bool isScratchReg(unsigned RegNo) { 208 return RegNo > 8 && RegNo < NumFPRegs; 209 } 210 211 /// getStackEntry - Return the X86::FP<n> register in register ST(i). 212 unsigned getStackEntry(unsigned STi) const { 213 if (STi >= StackTop) 214 report_fatal_error("Access past stack top!"); 215 return Stack[StackTop-1-STi]; 216 } 217 218 /// getSTReg - Return the X86::ST(i) register which contains the specified 219 /// FP<RegNo> register. 220 unsigned getSTReg(unsigned RegNo) const { 221 return StackTop - 1 - getSlot(RegNo) + X86::ST0; 222 } 223 224 // pushReg - Push the specified FP<n> register onto the stack. 225 void pushReg(unsigned Reg) { 226 assert(Reg < NumFPRegs && "Register number out of range!"); 227 if (StackTop >= 8) 228 report_fatal_error("Stack overflow!"); 229 Stack[StackTop] = Reg; 230 RegMap[Reg] = StackTop++; 231 } 232 233 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 234 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { 235 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 236 if (isAtTop(RegNo)) return; 237 238 unsigned STReg = getSTReg(RegNo); 239 unsigned RegOnTop = getStackEntry(0); 240 241 // Swap the slots the regs are in. 242 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 243 244 // Swap stack slot contents. 245 if (RegMap[RegOnTop] >= StackTop) 246 report_fatal_error("Access past stack top!"); 247 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 248 249 // Emit an fxch to update the runtime processors version of the state. 250 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 251 ++NumFXCH; 252 } 253 254 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { 255 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 256 unsigned STReg = getSTReg(RegNo); 257 pushReg(AsReg); // New register on top of stack 258 259 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 260 } 261 262 /// duplicatePendingSTBeforeKill - The instruction at I is about to kill 263 /// RegNo. If any PendingST registers still need the RegNo value, duplicate 264 /// them to new scratch registers. 265 void duplicatePendingSTBeforeKill(unsigned RegNo, MachineInstr *I) { 266 for (unsigned i = 0; i != NumPendingSTs; ++i) { 267 if (PendingST[i] != RegNo) 268 continue; 269 unsigned SR = getScratchReg(); 270 DEBUG(dbgs() << "Duplicating pending ST" << i 271 << " in FP" << RegNo << " to FP" << SR << '\n'); 272 duplicateToTop(RegNo, SR, I); 273 PendingST[i] = SR; 274 } 275 } 276 277 /// popStackAfter - Pop the current value off of the top of the FP stack 278 /// after the specified instruction. 279 void popStackAfter(MachineBasicBlock::iterator &I); 280 281 /// freeStackSlotAfter - Free the specified register from the register 282 /// stack, so that it is no longer in a register. If the register is 283 /// currently at the top of the stack, we just pop the current instruction, 284 /// otherwise we store the current top-of-stack into the specified slot, 285 /// then pop the top of stack. 286 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 287 288 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted 289 /// instruction. 290 MachineBasicBlock::iterator 291 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo); 292 293 /// Adjust the live registers to be the set in Mask. 294 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I); 295 296 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is 297 /// st(0), FP reg FixStack[1] is st(1) etc. 298 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount, 299 MachineBasicBlock::iterator I); 300 301 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 302 303 void handleZeroArgFP(MachineBasicBlock::iterator &I); 304 void handleOneArgFP(MachineBasicBlock::iterator &I); 305 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 306 void handleTwoArgFP(MachineBasicBlock::iterator &I); 307 void handleCompareFP(MachineBasicBlock::iterator &I); 308 void handleCondMovFP(MachineBasicBlock::iterator &I); 309 void handleSpecialFP(MachineBasicBlock::iterator &I); 310 311 // Check if a COPY instruction is using FP registers. 312 bool isFPCopy(MachineInstr *MI) { 313 unsigned DstReg = MI->getOperand(0).getReg(); 314 unsigned SrcReg = MI->getOperand(1).getReg(); 315 316 return X86::RFP80RegClass.contains(DstReg) || 317 X86::RFP80RegClass.contains(SrcReg); 318 } 319 }; 320 char FPS::ID = 0; 321 } 322 323 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 324 325 /// getFPReg - Return the X86::FPx register number for the specified operand. 326 /// For example, this returns 3 for X86::FP3. 327 static unsigned getFPReg(const MachineOperand &MO) { 328 assert(MO.isReg() && "Expected an FP register!"); 329 unsigned Reg = MO.getReg(); 330 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 331 return Reg - X86::FP0; 332 } 333 334 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 335 /// register references into FP stack references. 336 /// 337 bool FPS::runOnMachineFunction(MachineFunction &MF) { 338 // We only need to run this pass if there are any FP registers used in this 339 // function. If it is all integer, there is nothing for us to do! 340 bool FPIsUsed = false; 341 342 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 343 for (unsigned i = 0; i <= 6; ++i) 344 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { 345 FPIsUsed = true; 346 break; 347 } 348 349 // Early exit. 350 if (!FPIsUsed) return false; 351 352 Bundles = &getAnalysis<EdgeBundles>(); 353 TII = MF.getTarget().getInstrInfo(); 354 355 // Prepare cross-MBB liveness. 356 bundleCFG(MF); 357 358 StackTop = 0; 359 360 // Process the function in depth first order so that we process at least one 361 // of the predecessors for every reachable block in the function. 362 SmallPtrSet<MachineBasicBlock*, 8> Processed; 363 MachineBasicBlock *Entry = MF.begin(); 364 365 bool Changed = false; 366 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> > 367 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 368 I != E; ++I) 369 Changed |= processBasicBlock(MF, **I); 370 371 // Process any unreachable blocks in arbitrary order now. 372 if (MF.size() != Processed.size()) 373 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) 374 if (Processed.insert(BB)) 375 Changed |= processBasicBlock(MF, *BB); 376 377 LiveBundles.clear(); 378 379 return Changed; 380 } 381 382 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and 383 /// live-out sets for the FP registers. Consistent means that the set of 384 /// registers live-out from a block is identical to the live-in set of all 385 /// successors. This is not enforced by the normal live-in lists since 386 /// registers may be implicitly defined, or not used by all successors. 387 void FPS::bundleCFG(MachineFunction &MF) { 388 assert(LiveBundles.empty() && "Stale data in LiveBundles"); 389 LiveBundles.resize(Bundles->getNumBundles()); 390 391 // Gather the actual live-in masks for all MBBs. 392 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { 393 MachineBasicBlock *MBB = I; 394 const unsigned Mask = calcLiveInMask(MBB); 395 if (!Mask) 396 continue; 397 // Update MBB ingoing bundle mask. 398 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)].Mask |= Mask; 399 } 400 } 401 402 /// processBasicBlock - Loop over all of the instructions in the basic block, 403 /// transforming FP instructions into their stack form. 404 /// 405 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 406 bool Changed = false; 407 MBB = &BB; 408 NumPendingSTs = 0; 409 410 setupBlockStack(); 411 412 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 413 MachineInstr *MI = I; 414 uint64_t Flags = MI->getDesc().TSFlags; 415 416 unsigned FPInstClass = Flags & X86II::FPTypeMask; 417 if (MI->isInlineAsm()) 418 FPInstClass = X86II::SpecialFP; 419 420 if (MI->isCopy() && isFPCopy(MI)) 421 FPInstClass = X86II::SpecialFP; 422 423 if (MI->isImplicitDef() && 424 X86::RFP80RegClass.contains(MI->getOperand(0).getReg())) 425 FPInstClass = X86II::SpecialFP; 426 427 if (FPInstClass == X86II::NotFP) 428 continue; // Efficiently ignore non-fp insts! 429 430 MachineInstr *PrevMI = 0; 431 if (I != BB.begin()) 432 PrevMI = prior(I); 433 434 ++NumFP; // Keep track of # of pseudo instrs 435 DEBUG(dbgs() << "\nFPInst:\t" << *MI); 436 437 // Get dead variables list now because the MI pointer may be deleted as part 438 // of processing! 439 SmallVector<unsigned, 8> DeadRegs; 440 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 441 const MachineOperand &MO = MI->getOperand(i); 442 if (MO.isReg() && MO.isDead()) 443 DeadRegs.push_back(MO.getReg()); 444 } 445 446 switch (FPInstClass) { 447 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 448 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 449 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 450 case X86II::TwoArgFP: handleTwoArgFP(I); break; 451 case X86II::CompareFP: handleCompareFP(I); break; 452 case X86II::CondMovFP: handleCondMovFP(I); break; 453 case X86II::SpecialFP: handleSpecialFP(I); break; 454 default: llvm_unreachable("Unknown FP Type!"); 455 } 456 457 // Check to see if any of the values defined by this instruction are dead 458 // after definition. If so, pop them. 459 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { 460 unsigned Reg = DeadRegs[i]; 461 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 462 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 463 freeStackSlotAfter(I, Reg-X86::FP0); 464 } 465 } 466 467 // Print out all of the instructions expanded to if -debug 468 DEBUG( 469 MachineBasicBlock::iterator PrevI(PrevMI); 470 if (I == PrevI) { 471 dbgs() << "Just deleted pseudo instruction\n"; 472 } else { 473 MachineBasicBlock::iterator Start = I; 474 // Rewind to first instruction newly inserted. 475 while (Start != BB.begin() && prior(Start) != PrevI) --Start; 476 dbgs() << "Inserted instructions:\n\t"; 477 Start->print(dbgs(), &MF.getTarget()); 478 while (++Start != llvm::next(I)) {} 479 } 480 dumpStack(); 481 ); 482 (void)PrevMI; 483 484 Changed = true; 485 } 486 487 finishBlockStack(); 488 489 return Changed; 490 } 491 492 /// setupBlockStack - Use the live bundles to set up our model of the stack 493 /// to match predecessors' live out stack. 494 void FPS::setupBlockStack() { 495 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber() 496 << " derived from " << MBB->getName() << ".\n"); 497 StackTop = 0; 498 // Get the live-in bundle for MBB. 499 const LiveBundle &Bundle = 500 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)]; 501 502 if (!Bundle.Mask) { 503 DEBUG(dbgs() << "Block has no FP live-ins.\n"); 504 return; 505 } 506 507 // Depth-first iteration should ensure that we always have an assigned stack. 508 assert(Bundle.isFixed() && "Reached block before any predecessors"); 509 510 // Push the fixed live-in registers. 511 for (unsigned i = Bundle.FixCount; i > 0; --i) { 512 MBB->addLiveIn(X86::ST0+i-1); 513 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP" 514 << unsigned(Bundle.FixStack[i-1]) << '\n'); 515 pushReg(Bundle.FixStack[i-1]); 516 } 517 518 // Kill off unwanted live-ins. This can happen with a critical edge. 519 // FIXME: We could keep these live registers around as zombies. They may need 520 // to be revived at the end of a short block. It might save a few instrs. 521 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin()); 522 DEBUG(MBB->dump()); 523 } 524 525 /// finishBlockStack - Revive live-outs that are implicitly defined out of 526 /// MBB. Shuffle live registers to match the expected fixed stack of any 527 /// predecessors, and ensure that all predecessors are expecting the same 528 /// stack. 529 void FPS::finishBlockStack() { 530 // The RET handling below takes care of return blocks for us. 531 if (MBB->succ_empty()) 532 return; 533 534 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber() 535 << " derived from " << MBB->getName() << ".\n"); 536 537 // Get MBB's live-out bundle. 538 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true); 539 LiveBundle &Bundle = LiveBundles[BundleIdx]; 540 541 // We may need to kill and define some registers to match successors. 542 // FIXME: This can probably be combined with the shuffle below. 543 MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); 544 adjustLiveRegs(Bundle.Mask, Term); 545 546 if (!Bundle.Mask) { 547 DEBUG(dbgs() << "No live-outs.\n"); 548 return; 549 } 550 551 // Has the stack order been fixed yet? 552 DEBUG(dbgs() << "LB#" << BundleIdx << ": "); 553 if (Bundle.isFixed()) { 554 DEBUG(dbgs() << "Shuffling stack to match.\n"); 555 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term); 556 } else { 557 // Not fixed yet, we get to choose. 558 DEBUG(dbgs() << "Fixing stack order now.\n"); 559 Bundle.FixCount = StackTop; 560 for (unsigned i = 0; i < StackTop; ++i) 561 Bundle.FixStack[i] = getStackEntry(i); 562 } 563 } 564 565 566 //===----------------------------------------------------------------------===// 567 // Efficient Lookup Table Support 568 //===----------------------------------------------------------------------===// 569 570 namespace { 571 struct TableEntry { 572 uint16_t from; 573 uint16_t to; 574 bool operator<(const TableEntry &TE) const { return from < TE.from; } 575 friend bool operator<(const TableEntry &TE, unsigned V) { 576 return TE.from < V; 577 } 578 friend bool LLVM_ATTRIBUTE_USED operator<(unsigned V, 579 const TableEntry &TE) { 580 return V < TE.from; 581 } 582 }; 583 } 584 585 #ifndef NDEBUG 586 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 587 for (unsigned i = 0; i != NumEntries-1; ++i) 588 if (!(Table[i] < Table[i+1])) return false; 589 return true; 590 } 591 #endif 592 593 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 594 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 595 if (I != Table+N && I->from == Opcode) 596 return I->to; 597 return -1; 598 } 599 600 #ifdef NDEBUG 601 #define ASSERT_SORTED(TABLE) 602 #else 603 #define ASSERT_SORTED(TABLE) \ 604 { static bool TABLE##Checked = false; \ 605 if (!TABLE##Checked) { \ 606 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \ 607 "All lookup tables must be sorted for efficient access!"); \ 608 TABLE##Checked = true; \ 609 } \ 610 } 611 #endif 612 613 //===----------------------------------------------------------------------===// 614 // Register File -> Register Stack Mapping Methods 615 //===----------------------------------------------------------------------===// 616 617 // OpcodeTable - Sorted map of register instructions to their stack version. 618 // The first element is an register file pseudo instruction, the second is the 619 // concrete X86 instruction which uses the register stack. 620 // 621 static const TableEntry OpcodeTable[] = { 622 { X86::ABS_Fp32 , X86::ABS_F }, 623 { X86::ABS_Fp64 , X86::ABS_F }, 624 { X86::ABS_Fp80 , X86::ABS_F }, 625 { X86::ADD_Fp32m , X86::ADD_F32m }, 626 { X86::ADD_Fp64m , X86::ADD_F64m }, 627 { X86::ADD_Fp64m32 , X86::ADD_F32m }, 628 { X86::ADD_Fp80m32 , X86::ADD_F32m }, 629 { X86::ADD_Fp80m64 , X86::ADD_F64m }, 630 { X86::ADD_FpI16m32 , X86::ADD_FI16m }, 631 { X86::ADD_FpI16m64 , X86::ADD_FI16m }, 632 { X86::ADD_FpI16m80 , X86::ADD_FI16m }, 633 { X86::ADD_FpI32m32 , X86::ADD_FI32m }, 634 { X86::ADD_FpI32m64 , X86::ADD_FI32m }, 635 { X86::ADD_FpI32m80 , X86::ADD_FI32m }, 636 { X86::CHS_Fp32 , X86::CHS_F }, 637 { X86::CHS_Fp64 , X86::CHS_F }, 638 { X86::CHS_Fp80 , X86::CHS_F }, 639 { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, 640 { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, 641 { X86::CMOVBE_Fp80 , X86::CMOVBE_F }, 642 { X86::CMOVB_Fp32 , X86::CMOVB_F }, 643 { X86::CMOVB_Fp64 , X86::CMOVB_F }, 644 { X86::CMOVB_Fp80 , X86::CMOVB_F }, 645 { X86::CMOVE_Fp32 , X86::CMOVE_F }, 646 { X86::CMOVE_Fp64 , X86::CMOVE_F }, 647 { X86::CMOVE_Fp80 , X86::CMOVE_F }, 648 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, 649 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, 650 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F }, 651 { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, 652 { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, 653 { X86::CMOVNB_Fp80 , X86::CMOVNB_F }, 654 { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, 655 { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, 656 { X86::CMOVNE_Fp80 , X86::CMOVNE_F }, 657 { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, 658 { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, 659 { X86::CMOVNP_Fp80 , X86::CMOVNP_F }, 660 { X86::CMOVP_Fp32 , X86::CMOVP_F }, 661 { X86::CMOVP_Fp64 , X86::CMOVP_F }, 662 { X86::CMOVP_Fp80 , X86::CMOVP_F }, 663 { X86::COS_Fp32 , X86::COS_F }, 664 { X86::COS_Fp64 , X86::COS_F }, 665 { X86::COS_Fp80 , X86::COS_F }, 666 { X86::DIVR_Fp32m , X86::DIVR_F32m }, 667 { X86::DIVR_Fp64m , X86::DIVR_F64m }, 668 { X86::DIVR_Fp64m32 , X86::DIVR_F32m }, 669 { X86::DIVR_Fp80m32 , X86::DIVR_F32m }, 670 { X86::DIVR_Fp80m64 , X86::DIVR_F64m }, 671 { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, 672 { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, 673 { X86::DIVR_FpI16m80, X86::DIVR_FI16m}, 674 { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, 675 { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, 676 { X86::DIVR_FpI32m80, X86::DIVR_FI32m}, 677 { X86::DIV_Fp32m , X86::DIV_F32m }, 678 { X86::DIV_Fp64m , X86::DIV_F64m }, 679 { X86::DIV_Fp64m32 , X86::DIV_F32m }, 680 { X86::DIV_Fp80m32 , X86::DIV_F32m }, 681 { X86::DIV_Fp80m64 , X86::DIV_F64m }, 682 { X86::DIV_FpI16m32 , X86::DIV_FI16m }, 683 { X86::DIV_FpI16m64 , X86::DIV_FI16m }, 684 { X86::DIV_FpI16m80 , X86::DIV_FI16m }, 685 { X86::DIV_FpI32m32 , X86::DIV_FI32m }, 686 { X86::DIV_FpI32m64 , X86::DIV_FI32m }, 687 { X86::DIV_FpI32m80 , X86::DIV_FI32m }, 688 { X86::ILD_Fp16m32 , X86::ILD_F16m }, 689 { X86::ILD_Fp16m64 , X86::ILD_F16m }, 690 { X86::ILD_Fp16m80 , X86::ILD_F16m }, 691 { X86::ILD_Fp32m32 , X86::ILD_F32m }, 692 { X86::ILD_Fp32m64 , X86::ILD_F32m }, 693 { X86::ILD_Fp32m80 , X86::ILD_F32m }, 694 { X86::ILD_Fp64m32 , X86::ILD_F64m }, 695 { X86::ILD_Fp64m64 , X86::ILD_F64m }, 696 { X86::ILD_Fp64m80 , X86::ILD_F64m }, 697 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, 698 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, 699 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m}, 700 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, 701 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, 702 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m}, 703 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, 704 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, 705 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m}, 706 { X86::IST_Fp16m32 , X86::IST_F16m }, 707 { X86::IST_Fp16m64 , X86::IST_F16m }, 708 { X86::IST_Fp16m80 , X86::IST_F16m }, 709 { X86::IST_Fp32m32 , X86::IST_F32m }, 710 { X86::IST_Fp32m64 , X86::IST_F32m }, 711 { X86::IST_Fp32m80 , X86::IST_F32m }, 712 { X86::IST_Fp64m32 , X86::IST_FP64m }, 713 { X86::IST_Fp64m64 , X86::IST_FP64m }, 714 { X86::IST_Fp64m80 , X86::IST_FP64m }, 715 { X86::LD_Fp032 , X86::LD_F0 }, 716 { X86::LD_Fp064 , X86::LD_F0 }, 717 { X86::LD_Fp080 , X86::LD_F0 }, 718 { X86::LD_Fp132 , X86::LD_F1 }, 719 { X86::LD_Fp164 , X86::LD_F1 }, 720 { X86::LD_Fp180 , X86::LD_F1 }, 721 { X86::LD_Fp32m , X86::LD_F32m }, 722 { X86::LD_Fp32m64 , X86::LD_F32m }, 723 { X86::LD_Fp32m80 , X86::LD_F32m }, 724 { X86::LD_Fp64m , X86::LD_F64m }, 725 { X86::LD_Fp64m80 , X86::LD_F64m }, 726 { X86::LD_Fp80m , X86::LD_F80m }, 727 { X86::MUL_Fp32m , X86::MUL_F32m }, 728 { X86::MUL_Fp64m , X86::MUL_F64m }, 729 { X86::MUL_Fp64m32 , X86::MUL_F32m }, 730 { X86::MUL_Fp80m32 , X86::MUL_F32m }, 731 { X86::MUL_Fp80m64 , X86::MUL_F64m }, 732 { X86::MUL_FpI16m32 , X86::MUL_FI16m }, 733 { X86::MUL_FpI16m64 , X86::MUL_FI16m }, 734 { X86::MUL_FpI16m80 , X86::MUL_FI16m }, 735 { X86::MUL_FpI32m32 , X86::MUL_FI32m }, 736 { X86::MUL_FpI32m64 , X86::MUL_FI32m }, 737 { X86::MUL_FpI32m80 , X86::MUL_FI32m }, 738 { X86::SIN_Fp32 , X86::SIN_F }, 739 { X86::SIN_Fp64 , X86::SIN_F }, 740 { X86::SIN_Fp80 , X86::SIN_F }, 741 { X86::SQRT_Fp32 , X86::SQRT_F }, 742 { X86::SQRT_Fp64 , X86::SQRT_F }, 743 { X86::SQRT_Fp80 , X86::SQRT_F }, 744 { X86::ST_Fp32m , X86::ST_F32m }, 745 { X86::ST_Fp64m , X86::ST_F64m }, 746 { X86::ST_Fp64m32 , X86::ST_F32m }, 747 { X86::ST_Fp80m32 , X86::ST_F32m }, 748 { X86::ST_Fp80m64 , X86::ST_F64m }, 749 { X86::ST_FpP80m , X86::ST_FP80m }, 750 { X86::SUBR_Fp32m , X86::SUBR_F32m }, 751 { X86::SUBR_Fp64m , X86::SUBR_F64m }, 752 { X86::SUBR_Fp64m32 , X86::SUBR_F32m }, 753 { X86::SUBR_Fp80m32 , X86::SUBR_F32m }, 754 { X86::SUBR_Fp80m64 , X86::SUBR_F64m }, 755 { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, 756 { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, 757 { X86::SUBR_FpI16m80, X86::SUBR_FI16m}, 758 { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, 759 { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, 760 { X86::SUBR_FpI32m80, X86::SUBR_FI32m}, 761 { X86::SUB_Fp32m , X86::SUB_F32m }, 762 { X86::SUB_Fp64m , X86::SUB_F64m }, 763 { X86::SUB_Fp64m32 , X86::SUB_F32m }, 764 { X86::SUB_Fp80m32 , X86::SUB_F32m }, 765 { X86::SUB_Fp80m64 , X86::SUB_F64m }, 766 { X86::SUB_FpI16m32 , X86::SUB_FI16m }, 767 { X86::SUB_FpI16m64 , X86::SUB_FI16m }, 768 { X86::SUB_FpI16m80 , X86::SUB_FI16m }, 769 { X86::SUB_FpI32m32 , X86::SUB_FI32m }, 770 { X86::SUB_FpI32m64 , X86::SUB_FI32m }, 771 { X86::SUB_FpI32m80 , X86::SUB_FI32m }, 772 { X86::TST_Fp32 , X86::TST_F }, 773 { X86::TST_Fp64 , X86::TST_F }, 774 { X86::TST_Fp80 , X86::TST_F }, 775 { X86::UCOM_FpIr32 , X86::UCOM_FIr }, 776 { X86::UCOM_FpIr64 , X86::UCOM_FIr }, 777 { X86::UCOM_FpIr80 , X86::UCOM_FIr }, 778 { X86::UCOM_Fpr32 , X86::UCOM_Fr }, 779 { X86::UCOM_Fpr64 , X86::UCOM_Fr }, 780 { X86::UCOM_Fpr80 , X86::UCOM_Fr }, 781 }; 782 783 static unsigned getConcreteOpcode(unsigned Opcode) { 784 ASSERT_SORTED(OpcodeTable); 785 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode); 786 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 787 return Opc; 788 } 789 790 //===----------------------------------------------------------------------===// 791 // Helper Methods 792 //===----------------------------------------------------------------------===// 793 794 // PopTable - Sorted map of instructions to their popping version. The first 795 // element is an instruction, the second is the version which pops. 796 // 797 static const TableEntry PopTable[] = { 798 { X86::ADD_FrST0 , X86::ADD_FPrST0 }, 799 800 { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, 801 { X86::DIV_FrST0 , X86::DIV_FPrST0 }, 802 803 { X86::IST_F16m , X86::IST_FP16m }, 804 { X86::IST_F32m , X86::IST_FP32m }, 805 806 { X86::MUL_FrST0 , X86::MUL_FPrST0 }, 807 808 { X86::ST_F32m , X86::ST_FP32m }, 809 { X86::ST_F64m , X86::ST_FP64m }, 810 { X86::ST_Frr , X86::ST_FPrr }, 811 812 { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, 813 { X86::SUB_FrST0 , X86::SUB_FPrST0 }, 814 815 { X86::UCOM_FIr , X86::UCOM_FIPr }, 816 817 { X86::UCOM_FPr , X86::UCOM_FPPr }, 818 { X86::UCOM_Fr , X86::UCOM_FPr }, 819 }; 820 821 /// popStackAfter - Pop the current value off of the top of the FP stack after 822 /// the specified instruction. This attempts to be sneaky and combine the pop 823 /// into the instruction itself if possible. The iterator is left pointing to 824 /// the last instruction, be it a new pop instruction inserted, or the old 825 /// instruction if it was modified in place. 826 /// 827 void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 828 MachineInstr* MI = I; 829 DebugLoc dl = MI->getDebugLoc(); 830 ASSERT_SORTED(PopTable); 831 if (StackTop == 0) 832 report_fatal_error("Cannot pop empty stack!"); 833 RegMap[Stack[--StackTop]] = ~0; // Update state 834 835 // Check to see if there is a popping version of this instruction... 836 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode()); 837 if (Opcode != -1) { 838 I->setDesc(TII->get(Opcode)); 839 if (Opcode == X86::UCOM_FPPr) 840 I->RemoveOperand(0); 841 } else { // Insert an explicit pop 842 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 843 } 844 } 845 846 /// freeStackSlotAfter - Free the specified register from the register stack, so 847 /// that it is no longer in a register. If the register is currently at the top 848 /// of the stack, we just pop the current instruction, otherwise we store the 849 /// current top-of-stack into the specified slot, then pop the top of stack. 850 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 851 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 852 popStackAfter(I); 853 return; 854 } 855 856 // Otherwise, store the top of stack into the dead slot, killing the operand 857 // without having to add in an explicit xchg then pop. 858 // 859 I = freeStackSlotBefore(++I, FPRegNo); 860 } 861 862 /// freeStackSlotBefore - Free the specified register without trying any 863 /// folding. 864 MachineBasicBlock::iterator 865 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) { 866 unsigned STReg = getSTReg(FPRegNo); 867 unsigned OldSlot = getSlot(FPRegNo); 868 unsigned TopReg = Stack[StackTop-1]; 869 Stack[OldSlot] = TopReg; 870 RegMap[TopReg] = OldSlot; 871 RegMap[FPRegNo] = ~0; 872 Stack[--StackTop] = ~0; 873 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg); 874 } 875 876 /// adjustLiveRegs - Kill and revive registers such that exactly the FP 877 /// registers with a bit in Mask are live. 878 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { 879 unsigned Defs = Mask; 880 unsigned Kills = 0; 881 for (unsigned i = 0; i < StackTop; ++i) { 882 unsigned RegNo = Stack[i]; 883 if (!(Defs & (1 << RegNo))) 884 // This register is live, but we don't want it. 885 Kills |= (1 << RegNo); 886 else 887 // We don't need to imp-def this live register. 888 Defs &= ~(1 << RegNo); 889 } 890 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?"); 891 892 // Produce implicit-defs for free by using killed registers. 893 while (Kills && Defs) { 894 unsigned KReg = CountTrailingZeros_32(Kills); 895 unsigned DReg = CountTrailingZeros_32(Defs); 896 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n"); 897 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); 898 std::swap(RegMap[KReg], RegMap[DReg]); 899 Kills &= ~(1 << KReg); 900 Defs &= ~(1 << DReg); 901 } 902 903 // Kill registers by popping. 904 if (Kills && I != MBB->begin()) { 905 MachineBasicBlock::iterator I2 = llvm::prior(I); 906 while (StackTop) { 907 unsigned KReg = getStackEntry(0); 908 if (!(Kills & (1 << KReg))) 909 break; 910 DEBUG(dbgs() << "Popping %FP" << KReg << "\n"); 911 popStackAfter(I2); 912 Kills &= ~(1 << KReg); 913 } 914 } 915 916 // Manually kill the rest. 917 while (Kills) { 918 unsigned KReg = CountTrailingZeros_32(Kills); 919 DEBUG(dbgs() << "Killing %FP" << KReg << "\n"); 920 freeStackSlotBefore(I, KReg); 921 Kills &= ~(1 << KReg); 922 } 923 924 // Load zeros for all the imp-defs. 925 while(Defs) { 926 unsigned DReg = CountTrailingZeros_32(Defs); 927 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n"); 928 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); 929 pushReg(DReg); 930 Defs &= ~(1 << DReg); 931 } 932 933 // Now we should have the correct registers live. 934 DEBUG(dumpStack()); 935 assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch"); 936 } 937 938 /// shuffleStackTop - emit fxch instructions before I to shuffle the top 939 /// FixCount entries into the order given by FixStack. 940 /// FIXME: Is there a better algorithm than insertion sort? 941 void FPS::shuffleStackTop(const unsigned char *FixStack, 942 unsigned FixCount, 943 MachineBasicBlock::iterator I) { 944 // Move items into place, starting from the desired stack bottom. 945 while (FixCount--) { 946 // Old register at position FixCount. 947 unsigned OldReg = getStackEntry(FixCount); 948 // Desired register at position FixCount. 949 unsigned Reg = FixStack[FixCount]; 950 if (Reg == OldReg) 951 continue; 952 // (Reg st0) (OldReg st0) = (Reg OldReg st0) 953 moveToTop(Reg, I); 954 if (FixCount > 0) 955 moveToTop(OldReg, I); 956 } 957 DEBUG(dumpStack()); 958 } 959 960 961 //===----------------------------------------------------------------------===// 962 // Instruction transformation implementation 963 //===----------------------------------------------------------------------===// 964 965 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 966 /// 967 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 968 MachineInstr *MI = I; 969 unsigned DestReg = getFPReg(MI->getOperand(0)); 970 971 // Change from the pseudo instruction to the concrete instruction. 972 MI->RemoveOperand(0); // Remove the explicit ST(0) operand 973 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 974 975 // Result gets pushed on the stack. 976 pushReg(DestReg); 977 } 978 979 /// handleOneArgFP - fst <mem>, ST(0) 980 /// 981 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 982 MachineInstr *MI = I; 983 unsigned NumOps = MI->getDesc().getNumOperands(); 984 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) && 985 "Can only handle fst* & ftst instructions!"); 986 987 // Is this the last use of the source register? 988 unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); 989 bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 990 991 if (KillsSrc) 992 duplicatePendingSTBeforeKill(Reg, I); 993 994 // FISTP64m is strange because there isn't a non-popping versions. 995 // If we have one _and_ we don't want to pop the operand, duplicate the value 996 // on the stack instead of moving it. This ensure that popping the value is 997 // always ok. 998 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m. 999 // 1000 if (!KillsSrc && 1001 (MI->getOpcode() == X86::IST_Fp64m32 || 1002 MI->getOpcode() == X86::ISTT_Fp16m32 || 1003 MI->getOpcode() == X86::ISTT_Fp32m32 || 1004 MI->getOpcode() == X86::ISTT_Fp64m32 || 1005 MI->getOpcode() == X86::IST_Fp64m64 || 1006 MI->getOpcode() == X86::ISTT_Fp16m64 || 1007 MI->getOpcode() == X86::ISTT_Fp32m64 || 1008 MI->getOpcode() == X86::ISTT_Fp64m64 || 1009 MI->getOpcode() == X86::IST_Fp64m80 || 1010 MI->getOpcode() == X86::ISTT_Fp16m80 || 1011 MI->getOpcode() == X86::ISTT_Fp32m80 || 1012 MI->getOpcode() == X86::ISTT_Fp64m80 || 1013 MI->getOpcode() == X86::ST_FpP80m)) { 1014 duplicateToTop(Reg, getScratchReg(), I); 1015 } else { 1016 moveToTop(Reg, I); // Move to the top of the stack... 1017 } 1018 1019 // Convert from the pseudo instruction to the concrete instruction. 1020 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand 1021 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1022 1023 if (MI->getOpcode() == X86::IST_FP64m || 1024 MI->getOpcode() == X86::ISTT_FP16m || 1025 MI->getOpcode() == X86::ISTT_FP32m || 1026 MI->getOpcode() == X86::ISTT_FP64m || 1027 MI->getOpcode() == X86::ST_FP80m) { 1028 if (StackTop == 0) 1029 report_fatal_error("Stack empty??"); 1030 --StackTop; 1031 } else if (KillsSrc) { // Last use of operand? 1032 popStackAfter(I); 1033 } 1034 } 1035 1036 1037 /// handleOneArgFPRW: Handle instructions that read from the top of stack and 1038 /// replace the value with a newly computed value. These instructions may have 1039 /// non-fp operands after their FP operands. 1040 /// 1041 /// Examples: 1042 /// R1 = fchs R2 1043 /// R1 = fadd R2, [mem] 1044 /// 1045 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 1046 MachineInstr *MI = I; 1047 #ifndef NDEBUG 1048 unsigned NumOps = MI->getDesc().getNumOperands(); 1049 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); 1050 #endif 1051 1052 // Is this the last use of the source register? 1053 unsigned Reg = getFPReg(MI->getOperand(1)); 1054 bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 1055 1056 if (KillsSrc) { 1057 duplicatePendingSTBeforeKill(Reg, I); 1058 // If this is the last use of the source register, just make sure it's on 1059 // the top of the stack. 1060 moveToTop(Reg, I); 1061 if (StackTop == 0) 1062 report_fatal_error("Stack cannot be empty!"); 1063 --StackTop; 1064 pushReg(getFPReg(MI->getOperand(0))); 1065 } else { 1066 // If this is not the last use of the source register, _copy_ it to the top 1067 // of the stack. 1068 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 1069 } 1070 1071 // Change from the pseudo instruction to the concrete instruction. 1072 MI->RemoveOperand(1); // Drop the source operand. 1073 MI->RemoveOperand(0); // Drop the destination operand. 1074 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1075 } 1076 1077 1078 //===----------------------------------------------------------------------===// 1079 // Define tables of various ways to map pseudo instructions 1080 // 1081 1082 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 1083 static const TableEntry ForwardST0Table[] = { 1084 { X86::ADD_Fp32 , X86::ADD_FST0r }, 1085 { X86::ADD_Fp64 , X86::ADD_FST0r }, 1086 { X86::ADD_Fp80 , X86::ADD_FST0r }, 1087 { X86::DIV_Fp32 , X86::DIV_FST0r }, 1088 { X86::DIV_Fp64 , X86::DIV_FST0r }, 1089 { X86::DIV_Fp80 , X86::DIV_FST0r }, 1090 { X86::MUL_Fp32 , X86::MUL_FST0r }, 1091 { X86::MUL_Fp64 , X86::MUL_FST0r }, 1092 { X86::MUL_Fp80 , X86::MUL_FST0r }, 1093 { X86::SUB_Fp32 , X86::SUB_FST0r }, 1094 { X86::SUB_Fp64 , X86::SUB_FST0r }, 1095 { X86::SUB_Fp80 , X86::SUB_FST0r }, 1096 }; 1097 1098 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 1099 static const TableEntry ReverseST0Table[] = { 1100 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative 1101 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative 1102 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative 1103 { X86::DIV_Fp32 , X86::DIVR_FST0r }, 1104 { X86::DIV_Fp64 , X86::DIVR_FST0r }, 1105 { X86::DIV_Fp80 , X86::DIVR_FST0r }, 1106 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative 1107 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative 1108 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative 1109 { X86::SUB_Fp32 , X86::SUBR_FST0r }, 1110 { X86::SUB_Fp64 , X86::SUBR_FST0r }, 1111 { X86::SUB_Fp80 , X86::SUBR_FST0r }, 1112 }; 1113 1114 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 1115 static const TableEntry ForwardSTiTable[] = { 1116 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative 1117 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative 1118 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative 1119 { X86::DIV_Fp32 , X86::DIVR_FrST0 }, 1120 { X86::DIV_Fp64 , X86::DIVR_FrST0 }, 1121 { X86::DIV_Fp80 , X86::DIVR_FrST0 }, 1122 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative 1123 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative 1124 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative 1125 { X86::SUB_Fp32 , X86::SUBR_FrST0 }, 1126 { X86::SUB_Fp64 , X86::SUBR_FrST0 }, 1127 { X86::SUB_Fp80 , X86::SUBR_FrST0 }, 1128 }; 1129 1130 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 1131 static const TableEntry ReverseSTiTable[] = { 1132 { X86::ADD_Fp32 , X86::ADD_FrST0 }, 1133 { X86::ADD_Fp64 , X86::ADD_FrST0 }, 1134 { X86::ADD_Fp80 , X86::ADD_FrST0 }, 1135 { X86::DIV_Fp32 , X86::DIV_FrST0 }, 1136 { X86::DIV_Fp64 , X86::DIV_FrST0 }, 1137 { X86::DIV_Fp80 , X86::DIV_FrST0 }, 1138 { X86::MUL_Fp32 , X86::MUL_FrST0 }, 1139 { X86::MUL_Fp64 , X86::MUL_FrST0 }, 1140 { X86::MUL_Fp80 , X86::MUL_FrST0 }, 1141 { X86::SUB_Fp32 , X86::SUB_FrST0 }, 1142 { X86::SUB_Fp64 , X86::SUB_FrST0 }, 1143 { X86::SUB_Fp80 , X86::SUB_FrST0 }, 1144 }; 1145 1146 1147 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 1148 /// instructions which need to be simplified and possibly transformed. 1149 /// 1150 /// Result: ST(0) = fsub ST(0), ST(i) 1151 /// ST(i) = fsub ST(0), ST(i) 1152 /// ST(0) = fsubr ST(0), ST(i) 1153 /// ST(i) = fsubr ST(0), ST(i) 1154 /// 1155 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 1156 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 1157 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 1158 MachineInstr *MI = I; 1159 1160 unsigned NumOperands = MI->getDesc().getNumOperands(); 1161 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 1162 unsigned Dest = getFPReg(MI->getOperand(0)); 1163 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 1164 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 1165 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 1166 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1167 DebugLoc dl = MI->getDebugLoc(); 1168 1169 unsigned TOS = getStackEntry(0); 1170 1171 // One of our operands must be on the top of the stack. If neither is yet, we 1172 // need to move one. 1173 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1174 // We can choose to move either operand to the top of the stack. If one of 1175 // the operands is killed by this instruction, we want that one so that we 1176 // can update right on top of the old version. 1177 if (KillsOp0) { 1178 moveToTop(Op0, I); // Move dead operand to TOS. 1179 TOS = Op0; 1180 } else if (KillsOp1) { 1181 moveToTop(Op1, I); 1182 TOS = Op1; 1183 } else { 1184 // All of the operands are live after this instruction executes, so we 1185 // cannot update on top of any operand. Because of this, we must 1186 // duplicate one of the stack elements to the top. It doesn't matter 1187 // which one we pick. 1188 // 1189 duplicateToTop(Op0, Dest, I); 1190 Op0 = TOS = Dest; 1191 KillsOp0 = true; 1192 } 1193 } else if (!KillsOp0 && !KillsOp1) { 1194 // If we DO have one of our operands at the top of the stack, but we don't 1195 // have a dead operand, we must duplicate one of the operands to a new slot 1196 // on the stack. 1197 duplicateToTop(Op0, Dest, I); 1198 Op0 = TOS = Dest; 1199 KillsOp0 = true; 1200 } 1201 1202 // Now we know that one of our operands is on the top of the stack, and at 1203 // least one of our operands is killed by this instruction. 1204 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 1205 "Stack conditions not set up right!"); 1206 1207 // We decide which form to use based on what is on the top of the stack, and 1208 // which operand is killed by this instruction. 1209 const TableEntry *InstTable; 1210 bool isForward = TOS == Op0; 1211 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 1212 if (updateST0) { 1213 if (isForward) 1214 InstTable = ForwardST0Table; 1215 else 1216 InstTable = ReverseST0Table; 1217 } else { 1218 if (isForward) 1219 InstTable = ForwardSTiTable; 1220 else 1221 InstTable = ReverseSTiTable; 1222 } 1223 1224 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table), 1225 MI->getOpcode()); 1226 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 1227 1228 // NotTOS - The register which is not on the top of stack... 1229 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 1230 1231 // Replace the old instruction with a new instruction 1232 MBB->remove(I++); 1233 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); 1234 1235 // If both operands are killed, pop one off of the stack in addition to 1236 // overwriting the other one. 1237 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 1238 assert(!updateST0 && "Should have updated other operand!"); 1239 popStackAfter(I); // Pop the top of stack 1240 } 1241 1242 // Update stack information so that we know the destination register is now on 1243 // the stack. 1244 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 1245 assert(UpdatedSlot < StackTop && Dest < 7); 1246 Stack[UpdatedSlot] = Dest; 1247 RegMap[Dest] = UpdatedSlot; 1248 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction 1249 } 1250 1251 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 1252 /// register arguments and no explicit destinations. 1253 /// 1254 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 1255 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 1256 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 1257 MachineInstr *MI = I; 1258 1259 unsigned NumOperands = MI->getDesc().getNumOperands(); 1260 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 1261 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 1262 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 1263 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 1264 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1265 1266 // Make sure the first operand is on the top of stack, the other one can be 1267 // anywhere. 1268 moveToTop(Op0, I); 1269 1270 // Change from the pseudo instruction to the concrete instruction. 1271 MI->getOperand(0).setReg(getSTReg(Op1)); 1272 MI->RemoveOperand(1); 1273 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1274 1275 // If any of the operands are killed by this instruction, free them. 1276 if (KillsOp0) freeStackSlotAfter(I, Op0); 1277 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 1278 } 1279 1280 /// handleCondMovFP - Handle two address conditional move instructions. These 1281 /// instructions move a st(i) register to st(0) iff a condition is true. These 1282 /// instructions require that the first operand is at the top of the stack, but 1283 /// otherwise don't modify the stack at all. 1284 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 1285 MachineInstr *MI = I; 1286 1287 unsigned Op0 = getFPReg(MI->getOperand(0)); 1288 unsigned Op1 = getFPReg(MI->getOperand(2)); 1289 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1290 1291 // The first operand *must* be on the top of the stack. 1292 moveToTop(Op0, I); 1293 1294 // Change the second operand to the stack register that the operand is in. 1295 // Change from the pseudo instruction to the concrete instruction. 1296 MI->RemoveOperand(0); 1297 MI->RemoveOperand(1); 1298 MI->getOperand(0).setReg(getSTReg(Op1)); 1299 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1300 1301 // If we kill the second operand, make sure to pop it from the stack. 1302 if (Op0 != Op1 && KillsOp1) { 1303 // Get this value off of the register stack. 1304 freeStackSlotAfter(I, Op1); 1305 } 1306 } 1307 1308 1309 /// handleSpecialFP - Handle special instructions which behave unlike other 1310 /// floating point instructions. This is primarily intended for use by pseudo 1311 /// instructions. 1312 /// 1313 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 1314 MachineInstr *MI = I; 1315 switch (MI->getOpcode()) { 1316 default: llvm_unreachable("Unknown SpecialFP instruction!"); 1317 case TargetOpcode::COPY: { 1318 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP. 1319 const MachineOperand &MO1 = MI->getOperand(1); 1320 const MachineOperand &MO0 = MI->getOperand(0); 1321 unsigned DstST = MO0.getReg() - X86::ST0; 1322 unsigned SrcST = MO1.getReg() - X86::ST0; 1323 bool KillsSrc = MI->killsRegister(MO1.getReg()); 1324 1325 // ST = COPY FP. Set up a pending ST register. 1326 if (DstST < 8) { 1327 unsigned SrcFP = getFPReg(MO1); 1328 assert(isLive(SrcFP) && "Cannot copy dead register"); 1329 assert(!MO0.isDead() && "Cannot copy to dead ST register"); 1330 1331 // Unallocated STs are marked as the nonexistent FP255. 1332 while (NumPendingSTs <= DstST) 1333 PendingST[NumPendingSTs++] = NumFPRegs; 1334 1335 // STi could still be live from a previous inline asm. 1336 if (isScratchReg(PendingST[DstST])) { 1337 DEBUG(dbgs() << "Clobbering old ST in FP" << unsigned(PendingST[DstST]) 1338 << '\n'); 1339 freeStackSlotBefore(MI, PendingST[DstST]); 1340 } 1341 1342 // When the source is killed, allocate a scratch FP register. 1343 if (KillsSrc) { 1344 duplicatePendingSTBeforeKill(SrcFP, I); 1345 unsigned Slot = getSlot(SrcFP); 1346 unsigned SR = getScratchReg(); 1347 PendingST[DstST] = SR; 1348 Stack[Slot] = SR; 1349 RegMap[SR] = Slot; 1350 } else 1351 PendingST[DstST] = SrcFP; 1352 break; 1353 } 1354 1355 // FP = COPY ST. Extract fixed stack value. 1356 // Any instruction defining ST registers must have assigned them to a 1357 // scratch register. 1358 if (SrcST < 8) { 1359 unsigned DstFP = getFPReg(MO0); 1360 assert(!isLive(DstFP) && "Cannot copy ST to live FP register"); 1361 assert(NumPendingSTs > SrcST && "Cannot copy from dead ST register"); 1362 unsigned SrcFP = PendingST[SrcST]; 1363 assert(isScratchReg(SrcFP) && "Expected ST in a scratch register"); 1364 assert(isLive(SrcFP) && "Scratch holding ST is dead"); 1365 1366 // DstFP steals the stack slot from SrcFP. 1367 unsigned Slot = getSlot(SrcFP); 1368 Stack[Slot] = DstFP; 1369 RegMap[DstFP] = Slot; 1370 1371 // Always treat the ST as killed. 1372 PendingST[SrcST] = NumFPRegs; 1373 while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs) 1374 --NumPendingSTs; 1375 break; 1376 } 1377 1378 // FP <- FP copy. 1379 unsigned DstFP = getFPReg(MO0); 1380 unsigned SrcFP = getFPReg(MO1); 1381 assert(isLive(SrcFP) && "Cannot copy dead register"); 1382 if (KillsSrc) { 1383 // If the input operand is killed, we can just change the owner of the 1384 // incoming stack slot into the result. 1385 unsigned Slot = getSlot(SrcFP); 1386 Stack[Slot] = DstFP; 1387 RegMap[DstFP] = Slot; 1388 } else { 1389 // For COPY we just duplicate the specified value to a new stack slot. 1390 // This could be made better, but would require substantial changes. 1391 duplicateToTop(SrcFP, DstFP, I); 1392 } 1393 break; 1394 } 1395 1396 case TargetOpcode::IMPLICIT_DEF: { 1397 // All FP registers must be explicitly defined, so load a 0 instead. 1398 unsigned Reg = MI->getOperand(0).getReg() - X86::FP0; 1399 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n'); 1400 BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0)); 1401 pushReg(Reg); 1402 break; 1403 } 1404 1405 case X86::FpPOP_RETVAL: { 1406 // The FpPOP_RETVAL instruction is used after calls that return a value on 1407 // the floating point stack. We cannot model this with ST defs since CALL 1408 // instructions have fixed clobber lists. This instruction is interpreted 1409 // to mean that there is one more live register on the stack than we 1410 // thought. 1411 // 1412 // This means that StackTop does not match the hardware stack between a 1413 // call and the FpPOP_RETVAL instructions. We do tolerate FP instructions 1414 // between CALL and FpPOP_RETVAL as long as they don't overflow the 1415 // hardware stack. 1416 unsigned DstFP = getFPReg(MI->getOperand(0)); 1417 1418 // Move existing stack elements up to reflect reality. 1419 assert(StackTop < 8 && "Stack overflowed before FpPOP_RETVAL"); 1420 if (StackTop) { 1421 std::copy_backward(Stack, Stack + StackTop, Stack + StackTop + 1); 1422 for (unsigned i = 0; i != NumFPRegs; ++i) 1423 ++RegMap[i]; 1424 } 1425 ++StackTop; 1426 1427 // DstFP is the new bottom of the stack. 1428 Stack[0] = DstFP; 1429 RegMap[DstFP] = 0; 1430 1431 // DstFP will be killed by processBasicBlock if this was a dead def. 1432 break; 1433 } 1434 1435 case TargetOpcode::INLINEASM: { 1436 // The inline asm MachineInstr currently only *uses* FP registers for the 1437 // 'f' constraint. These should be turned into the current ST(x) register 1438 // in the machine instr. 1439 // 1440 // There are special rules for x87 inline assembly. The compiler must know 1441 // exactly how many registers are popped and pushed implicitly by the asm. 1442 // Otherwise it is not possible to restore the stack state after the inline 1443 // asm. 1444 // 1445 // There are 3 kinds of input operands: 1446 // 1447 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A 1448 // popped input operand must be in a fixed stack slot, and it is either 1449 // tied to an output operand, or in the clobber list. The MI has ST use 1450 // and def operands for these inputs. 1451 // 1452 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are 1453 // preserved by the inline asm. The fixed stack slots must be STn-STm 1454 // following the popped inputs. A fixed input operand cannot be tied to 1455 // an output or appear in the clobber list. The MI has ST use operands 1456 // and no defs for these inputs. 1457 // 1458 // 3. Preserved inputs. These inputs use the "f" constraint which is 1459 // represented as an FP register. The inline asm won't change these 1460 // stack slots. 1461 // 1462 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered 1463 // registers do not count as output operands. The inline asm changes the 1464 // stack as if it popped all the popped inputs and then pushed all the 1465 // output operands. 1466 1467 // Scan the assembly for ST registers used, defined and clobbered. We can 1468 // only tell clobbers from defs by looking at the asm descriptor. 1469 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0; 1470 unsigned NumOps = 0; 1471 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands(); 1472 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) { 1473 unsigned Flags = MI->getOperand(i).getImm(); 1474 NumOps = InlineAsm::getNumOperandRegisters(Flags); 1475 if (NumOps != 1) 1476 continue; 1477 const MachineOperand &MO = MI->getOperand(i + 1); 1478 if (!MO.isReg()) 1479 continue; 1480 unsigned STReg = MO.getReg() - X86::ST0; 1481 if (STReg >= 8) 1482 continue; 1483 1484 switch (InlineAsm::getKind(Flags)) { 1485 case InlineAsm::Kind_RegUse: 1486 STUses |= (1u << STReg); 1487 break; 1488 case InlineAsm::Kind_RegDef: 1489 case InlineAsm::Kind_RegDefEarlyClobber: 1490 STDefs |= (1u << STReg); 1491 if (MO.isDead()) 1492 STDeadDefs |= (1u << STReg); 1493 break; 1494 case InlineAsm::Kind_Clobber: 1495 STClobbers |= (1u << STReg); 1496 break; 1497 default: 1498 break; 1499 } 1500 } 1501 1502 if (STUses && !isMask_32(STUses)) 1503 MI->emitError("fixed input regs must be last on the x87 stack"); 1504 unsigned NumSTUses = CountTrailingOnes_32(STUses); 1505 1506 // Defs must be contiguous from the stack top. ST0-STn. 1507 if (STDefs && !isMask_32(STDefs)) { 1508 MI->emitError("output regs must be last on the x87 stack"); 1509 STDefs = NextPowerOf2(STDefs) - 1; 1510 } 1511 unsigned NumSTDefs = CountTrailingOnes_32(STDefs); 1512 1513 // So must the clobbered stack slots. ST0-STm, m >= n. 1514 if (STClobbers && !isMask_32(STDefs | STClobbers)) 1515 MI->emitError("clobbers must be last on the x87 stack"); 1516 1517 // Popped inputs are the ones that are also clobbered or defined. 1518 unsigned STPopped = STUses & (STDefs | STClobbers); 1519 if (STPopped && !isMask_32(STPopped)) 1520 MI->emitError("implicitly popped regs must be last on the x87 stack"); 1521 unsigned NumSTPopped = CountTrailingOnes_32(STPopped); 1522 1523 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops " 1524 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n"); 1525 1526 // Scan the instruction for FP uses corresponding to "f" constraints. 1527 // Collect FP registers to kill afer the instruction. 1528 // Always kill all the scratch regs. 1529 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff; 1530 unsigned FPUsed = 0; 1531 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1532 MachineOperand &Op = MI->getOperand(i); 1533 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1534 continue; 1535 if (!Op.isUse()) 1536 MI->emitError("illegal \"f\" output constraint"); 1537 unsigned FPReg = getFPReg(Op); 1538 FPUsed |= 1U << FPReg; 1539 1540 // If we kill this operand, make sure to pop it from the stack after the 1541 // asm. We just remember it for now, and pop them all off at the end in 1542 // a batch. 1543 if (Op.isKill()) 1544 FPKills |= 1U << FPReg; 1545 } 1546 1547 // The popped inputs will be killed by the instruction, so duplicate them 1548 // if the FP register needs to be live after the instruction, or if it is 1549 // used in the instruction itself. We effectively treat the popped inputs 1550 // as early clobbers. 1551 for (unsigned i = 0; i < NumSTPopped; ++i) { 1552 if ((FPKills & ~FPUsed) & (1u << PendingST[i])) 1553 continue; 1554 unsigned SR = getScratchReg(); 1555 duplicateToTop(PendingST[i], SR, I); 1556 DEBUG(dbgs() << "Duplicating ST" << i << " in FP" 1557 << unsigned(PendingST[i]) << " to avoid clobbering it.\n"); 1558 PendingST[i] = SR; 1559 } 1560 1561 // Make sure we have a unique live register for every fixed use. Some of 1562 // them could be undef uses, and we need to emit LD_F0 instructions. 1563 for (unsigned i = 0; i < NumSTUses; ++i) { 1564 if (i < NumPendingSTs && PendingST[i] < NumFPRegs) { 1565 // Check for shared assignments. 1566 for (unsigned j = 0; j < i; ++j) { 1567 if (PendingST[j] != PendingST[i]) 1568 continue; 1569 // STi and STj are inn the same register, create a copy. 1570 unsigned SR = getScratchReg(); 1571 duplicateToTop(PendingST[i], SR, I); 1572 DEBUG(dbgs() << "Duplicating ST" << i << " in FP" 1573 << unsigned(PendingST[i]) 1574 << " to avoid collision with ST" << j << '\n'); 1575 PendingST[i] = SR; 1576 } 1577 continue; 1578 } 1579 unsigned SR = getScratchReg(); 1580 DEBUG(dbgs() << "Emitting LD_F0 for ST" << i << " in FP" << SR << '\n'); 1581 BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0)); 1582 pushReg(SR); 1583 PendingST[i] = SR; 1584 if (NumPendingSTs == i) 1585 ++NumPendingSTs; 1586 } 1587 assert(NumPendingSTs >= NumSTUses && "Fixed registers should be assigned"); 1588 1589 // Now we can rearrange the live registers to match what was requested. 1590 shuffleStackTop(PendingST, NumPendingSTs, I); 1591 DEBUG({dbgs() << "Before asm: "; dumpStack();}); 1592 1593 // With the stack layout fixed, rewrite the FP registers. 1594 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1595 MachineOperand &Op = MI->getOperand(i); 1596 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1597 continue; 1598 unsigned FPReg = getFPReg(Op); 1599 Op.setReg(getSTReg(FPReg)); 1600 } 1601 1602 // Simulate the inline asm popping its inputs and pushing its outputs. 1603 StackTop -= NumSTPopped; 1604 1605 // Hold the fixed output registers in scratch FP registers. They will be 1606 // transferred to real FP registers by copies. 1607 NumPendingSTs = 0; 1608 for (unsigned i = 0; i < NumSTDefs; ++i) { 1609 unsigned SR = getScratchReg(); 1610 pushReg(SR); 1611 FPKills &= ~(1u << SR); 1612 } 1613 for (unsigned i = 0; i < NumSTDefs; ++i) 1614 PendingST[NumPendingSTs++] = getStackEntry(i); 1615 DEBUG({dbgs() << "After asm: "; dumpStack();}); 1616 1617 // If any of the ST defs were dead, pop them immediately. Our caller only 1618 // handles dead FP defs. 1619 MachineBasicBlock::iterator InsertPt = MI; 1620 for (unsigned i = 0; STDefs & (1u << i); ++i) { 1621 if (!(STDeadDefs & (1u << i))) 1622 continue; 1623 freeStackSlotAfter(InsertPt, PendingST[i]); 1624 PendingST[i] = NumFPRegs; 1625 } 1626 while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs) 1627 --NumPendingSTs; 1628 1629 // If this asm kills any FP registers (is the last use of them) we must 1630 // explicitly emit pop instructions for them. Do this now after the asm has 1631 // executed so that the ST(x) numbers are not off (which would happen if we 1632 // did this inline with operand rewriting). 1633 // 1634 // Note: this might be a non-optimal pop sequence. We might be able to do 1635 // better by trying to pop in stack order or something. 1636 while (FPKills) { 1637 unsigned FPReg = CountTrailingZeros_32(FPKills); 1638 if (isLive(FPReg)) 1639 freeStackSlotAfter(InsertPt, FPReg); 1640 FPKills &= ~(1U << FPReg); 1641 } 1642 // Don't delete the inline asm! 1643 return; 1644 } 1645 1646 case X86::WIN_FTOL_32: 1647 case X86::WIN_FTOL_64: { 1648 // Push the operand into ST0. 1649 MachineOperand &Op = MI->getOperand(0); 1650 assert(Op.isUse() && Op.isReg() && 1651 Op.getReg() >= X86::FP0 && Op.getReg() <= X86::FP6); 1652 unsigned FPReg = getFPReg(Op); 1653 if (Op.isKill()) 1654 moveToTop(FPReg, I); 1655 else 1656 duplicateToTop(FPReg, FPReg, I); 1657 1658 // Emit the call. This will pop the operand. 1659 BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::CALLpcrel32)) 1660 .addExternalSymbol("_ftol2") 1661 .addReg(X86::ST0, RegState::ImplicitKill) 1662 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 1663 .addReg(X86::EDX, RegState::Define | RegState::Implicit) 1664 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 1665 --StackTop; 1666 1667 break; 1668 } 1669 1670 case X86::RET: 1671 case X86::RETI: 1672 // If RET has an FP register use operand, pass the first one in ST(0) and 1673 // the second one in ST(1). 1674 1675 // Find the register operands. 1676 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; 1677 unsigned LiveMask = 0; 1678 1679 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1680 MachineOperand &Op = MI->getOperand(i); 1681 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1682 continue; 1683 // FP Register uses must be kills unless there are two uses of the same 1684 // register, in which case only one will be a kill. 1685 assert(Op.isUse() && 1686 (Op.isKill() || // Marked kill. 1687 getFPReg(Op) == FirstFPRegOp || // Second instance. 1688 MI->killsRegister(Op.getReg())) && // Later use is marked kill. 1689 "Ret only defs operands, and values aren't live beyond it"); 1690 1691 if (FirstFPRegOp == ~0U) 1692 FirstFPRegOp = getFPReg(Op); 1693 else { 1694 assert(SecondFPRegOp == ~0U && "More than two fp operands!"); 1695 SecondFPRegOp = getFPReg(Op); 1696 } 1697 LiveMask |= (1 << getFPReg(Op)); 1698 1699 // Remove the operand so that later passes don't see it. 1700 MI->RemoveOperand(i); 1701 --i, --e; 1702 } 1703 1704 // We may have been carrying spurious live-ins, so make sure only the returned 1705 // registers are left live. 1706 adjustLiveRegs(LiveMask, MI); 1707 if (!LiveMask) return; // Quick check to see if any are possible. 1708 1709 // There are only four possibilities here: 1710 // 1) we are returning a single FP value. In this case, it has to be in 1711 // ST(0) already, so just declare success by removing the value from the 1712 // FP Stack. 1713 if (SecondFPRegOp == ~0U) { 1714 // Assert that the top of stack contains the right FP register. 1715 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) && 1716 "Top of stack not the right register for RET!"); 1717 1718 // Ok, everything is good, mark the value as not being on the stack 1719 // anymore so that our assertion about the stack being empty at end of 1720 // block doesn't fire. 1721 StackTop = 0; 1722 return; 1723 } 1724 1725 // Otherwise, we are returning two values: 1726 // 2) If returning the same value for both, we only have one thing in the FP 1727 // stack. Consider: RET FP1, FP1 1728 if (StackTop == 1) { 1729 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&& 1730 "Stack misconfiguration for RET!"); 1731 1732 // Duplicate the TOS so that we return it twice. Just pick some other FPx 1733 // register to hold it. 1734 unsigned NewReg = getScratchReg(); 1735 duplicateToTop(FirstFPRegOp, NewReg, MI); 1736 FirstFPRegOp = NewReg; 1737 } 1738 1739 /// Okay we know we have two different FPx operands now: 1740 assert(StackTop == 2 && "Must have two values live!"); 1741 1742 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently 1743 /// in ST(1). In this case, emit an fxch. 1744 if (getStackEntry(0) == SecondFPRegOp) { 1745 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live"); 1746 moveToTop(FirstFPRegOp, MI); 1747 } 1748 1749 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in 1750 /// ST(1). Just remove both from our understanding of the stack and return. 1751 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live"); 1752 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live"); 1753 StackTop = 0; 1754 return; 1755 } 1756 1757 I = MBB->erase(I); // Remove the pseudo instruction 1758 1759 // We want to leave I pointing to the previous instruction, but what if we 1760 // just erased the first instruction? 1761 if (I == MBB->begin()) { 1762 DEBUG(dbgs() << "Inserting dummy KILL\n"); 1763 I = BuildMI(*MBB, I, DebugLoc(), TII->get(TargetOpcode::KILL)); 1764 } else 1765 --I; 1766 } 1767