| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 198 /// itinerary class UseClass, operand index UseIdx.
200 unsigned UseClass, unsigned UseIdx) const {
210 if ((FirstUseIdx + UseIdx) >= LastUseIdx)
214 Forwardings[FirstUseIdx + UseIdx];
221 unsigned UseClass, unsigned UseIdx) const {
229 int UseCycle = getOperandCycle(UseClass, UseIdx);
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
|
| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 66 const MachineInstr *UseMI, unsigned UseIdx) const {
72 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 77 /// OrigIdx are also available with the same value at UseIdx.
80 SlotIndex UseIdx) {
82 UseIdx = UseIdx.getRegSlot(true);
95 if (OVNI != li.getVNInfoAt(UseIdx))
102 SlotIndex UseIdx,
125 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
|
| SplitKit.h | 313 /// defFromParent - Define Reg from ParentVNI at UseIdx using either
317 SlotIndex UseIdx,
|
| InlineSpiller.cpp | 837 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
838 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
847 DEBUG(dbgs() << UseIdx << '\t' << *MI);
859 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
861 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
872 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
[all...] |
| TargetInstrInfoImpl.cpp | 515 SDNode *UseNode, unsigned UseIdx) const {
526 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
|
| MachineVerifier.cpp | 791 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI).getRegSlot(true);
794 if (!LI.liveAt(UseIdx)) {
796 *OS << UseIdx << " is not live in " << LI << '\n';
800 if (MO->isKill() && !LI.killedAt(UseIdx.getRegSlot())) {
[all...] |
| LiveIntervalAnalysis.cpp | 825 SlotIndex UseIdx) const {
826 VNInfo *UValNo = li.getVNInfoAt(UseIdx);
853 SlotIndex UseIdx = getInstructionIndex(UseMI);
854 if (li.getVNInfoAt(UseIdx) != ValNo)
856 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
[all...] |
| RegisterCoalescer.cpp | 667 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
668 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
720 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
721 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
738 SlotIndex DefIdx = UseIdx.getRegSlot();
[all...] |
| ScheduleDAGInstrs.cpp | 439 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
441 VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
[all...] |
| SplitKit.cpp | 426 SlotIndex UseIdx,
439 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 212 const MachineInstr *UseMI, unsigned UseIdx) const;
216 SDNode *UseNode, unsigned UseIdx) const;
241 unsigned UseIdx, unsigned UseAlign) const;
245 unsigned UseIdx, unsigned UseAlign) const;
250 unsigned UseIdx, unsigned UseAlign) const;
261 const MachineInstr *UseMI, unsigned UseIdx) const;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 84 /// OrigIdx are also available with the same value at UseIdx.
86 SlotIndex UseIdx);
157 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
160 SlotIndex UseIdx,
|
| LiveIntervalAnalysis.h | 388 SlotIndex UseIdx) const;
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 662 const MachineInstr *UseMI, unsigned UseIdx) const;
666 SDNode *UseNode, unsigned UseIdx) const = 0;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 364 const MachineInstr *UseMI, unsigned UseIdx) const;
|
| X86InstrInfo.cpp | [all...] |
