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      1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines a pattern matching instruction selector for the Cell SPU,
     11 // converting from a legalized dag to a SPU-target dag.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "SPU.h"
     16 #include "SPUTargetMachine.h"
     17 #include "SPUHazardRecognizers.h"
     18 #include "SPUFrameLowering.h"
     19 #include "SPUTargetMachine.h"
     20 #include "llvm/CodeGen/MachineConstantPool.h"
     21 #include "llvm/CodeGen/MachineInstrBuilder.h"
     22 #include "llvm/CodeGen/MachineFunction.h"
     23 #include "llvm/CodeGen/SelectionDAG.h"
     24 #include "llvm/CodeGen/SelectionDAGISel.h"
     25 #include "llvm/Target/TargetOptions.h"
     26 #include "llvm/ADT/Statistic.h"
     27 #include "llvm/Constants.h"
     28 #include "llvm/GlobalValue.h"
     29 #include "llvm/Intrinsics.h"
     30 #include "llvm/LLVMContext.h"
     31 #include "llvm/Support/Debug.h"
     32 #include "llvm/Support/ErrorHandling.h"
     33 #include "llvm/Support/MathExtras.h"
     34 #include "llvm/Support/Compiler.h"
     35 #include "llvm/Support/raw_ostream.h"
     36 
     37 using namespace llvm;
     38 
     39 namespace {
     40   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
     41   bool
     42   isI32IntS10Immediate(ConstantSDNode *CN)
     43   {
     44     return isInt<10>(CN->getSExtValue());
     45   }
     46 
     47   //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
     48   bool
     49   isI32IntU10Immediate(ConstantSDNode *CN)
     50   {
     51     return isUInt<10>(CN->getSExtValue());
     52   }
     53 
     54   //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
     55   bool
     56   isI16IntS10Immediate(ConstantSDNode *CN)
     57   {
     58     return isInt<10>(CN->getSExtValue());
     59   }
     60 
     61   //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
     62   bool
     63   isI16IntU10Immediate(ConstantSDNode *CN)
     64   {
     65     return isUInt<10>((short) CN->getZExtValue());
     66   }
     67 
     68   //! ConstantSDNode predicate for signed 16-bit values
     69   /*!
     70     \arg CN The constant SelectionDAG node holding the value
     71     \arg Imm The returned 16-bit value, if returning true
     72 
     73     This predicate tests the value in \a CN to see whether it can be
     74     represented as a 16-bit, sign-extended quantity. Returns true if
     75     this is the case.
     76    */
     77   bool
     78   isIntS16Immediate(ConstantSDNode *CN, short &Imm)
     79   {
     80     EVT vt = CN->getValueType(0);
     81     Imm = (short) CN->getZExtValue();
     82     if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
     83       return true;
     84     } else if (vt == MVT::i32) {
     85       int32_t i_val = (int32_t) CN->getZExtValue();
     86       short s_val = (short) i_val;
     87       return i_val == s_val;
     88     } else {
     89       int64_t i_val = (int64_t) CN->getZExtValue();
     90       short s_val = (short) i_val;
     91       return i_val == s_val;
     92     }
     93   }
     94 
     95   //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
     96   static bool
     97   isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
     98   {
     99     EVT vt = FPN->getValueType(0);
    100     if (vt == MVT::f32) {
    101       int val = FloatToBits(FPN->getValueAPF().convertToFloat());
    102       int sval = (int) ((val << 16) >> 16);
    103       Imm = (short) val;
    104       return val == sval;
    105     }
    106 
    107     return false;
    108   }
    109 
    110   //! Generate the carry-generate shuffle mask.
    111   SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
    112     SmallVector<SDValue, 16 > ShufBytes;
    113 
    114     // Create the shuffle mask for "rotating" the borrow up one register slot
    115     // once the borrow is generated.
    116     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
    117     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
    118     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
    119     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
    120 
    121     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
    122                        &ShufBytes[0], ShufBytes.size());
    123   }
    124 
    125   //! Generate the borrow-generate shuffle mask
    126   SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
    127     SmallVector<SDValue, 16 > ShufBytes;
    128 
    129     // Create the shuffle mask for "rotating" the borrow up one register slot
    130     // once the borrow is generated.
    131     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
    132     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
    133     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
    134     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
    135 
    136     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
    137                        &ShufBytes[0], ShufBytes.size());
    138   }
    139 
    140   //===------------------------------------------------------------------===//
    141   /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
    142   /// instructions for SelectionDAG operations.
    143   ///
    144   class SPUDAGToDAGISel :
    145     public SelectionDAGISel
    146   {
    147     const SPUTargetMachine &TM;
    148     const SPUTargetLowering &SPUtli;
    149     unsigned GlobalBaseReg;
    150 
    151   public:
    152     explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
    153       SelectionDAGISel(tm),
    154       TM(tm),
    155       SPUtli(*tm.getTargetLowering())
    156     { }
    157 
    158     virtual bool runOnMachineFunction(MachineFunction &MF) {
    159       // Make sure we re-emit a set of the global base reg if necessary
    160       GlobalBaseReg = 0;
    161       SelectionDAGISel::runOnMachineFunction(MF);
    162       return true;
    163     }
    164 
    165     /// getI32Imm - Return a target constant with the specified value, of type
    166     /// i32.
    167     inline SDValue getI32Imm(uint32_t Imm) {
    168       return CurDAG->getTargetConstant(Imm, MVT::i32);
    169     }
    170 
    171     /// getSmallIPtrImm - Return a target constant of pointer type.
    172     inline SDValue getSmallIPtrImm(unsigned Imm) {
    173       return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
    174     }
    175 
    176     SDNode *emitBuildVector(SDNode *bvNode) {
    177       EVT vecVT = bvNode->getValueType(0);
    178       DebugLoc dl = bvNode->getDebugLoc();
    179 
    180       // Check to see if this vector can be represented as a CellSPU immediate
    181       // constant by invoking all of the instruction selection predicates:
    182       if (((vecVT == MVT::v8i16) &&
    183            (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
    184           ((vecVT == MVT::v4i32) &&
    185            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
    186             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
    187             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
    188             (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
    189           ((vecVT == MVT::v2i64) &&
    190            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
    191             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
    192             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
    193         HandleSDNode Dummy(SDValue(bvNode, 0));
    194         if (SDNode *N = Select(bvNode))
    195           return N;
    196         return Dummy.getValue().getNode();
    197       }
    198 
    199       // No, need to emit a constant pool spill:
    200       std::vector<Constant*> CV;
    201 
    202       for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
    203         ConstantSDNode *V = cast<ConstantSDNode > (bvNode->getOperand(i));
    204         CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
    205       }
    206 
    207       const Constant *CP = ConstantVector::get(CV);
    208       SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
    209       unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
    210       SDValue CGPoolOffset =
    211               SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
    212 
    213       HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
    214                                          CurDAG->getEntryNode(), CGPoolOffset,
    215                                          MachinePointerInfo::getConstantPool(),
    216                                          false, false, false, Alignment));
    217       CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
    218       if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
    219         return N;
    220       return Dummy.getValue().getNode();
    221     }
    222 
    223     /// Select - Convert the specified operand from a target-independent to a
    224     /// target-specific node if it hasn't already been changed.
    225     SDNode *Select(SDNode *N);
    226 
    227     //! Emit the instruction sequence for i64 shl
    228     SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
    229 
    230     //! Emit the instruction sequence for i64 srl
    231     SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
    232 
    233     //! Emit the instruction sequence for i64 sra
    234     SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
    235 
    236     //! Emit the necessary sequence for loading i64 constants:
    237     SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
    238 
    239     //! Alternate instruction emit sequence for loading i64 constants
    240     SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
    241 
    242     //! Returns true if the address N is an A-form (local store) address
    243     bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
    244                          SDValue &Index);
    245 
    246     //! D-form address predicate
    247     bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
    248                          SDValue &Index);
    249 
    250     /// Alternate D-form address using i7 offset predicate
    251     bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
    252                           SDValue &Base);
    253 
    254     /// D-form address selection workhorse
    255     bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
    256                                SDValue &Base, int minOffset, int maxOffset);
    257 
    258     //! Address predicate if N can be expressed as an indexed [r+r] operation.
    259     bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
    260                          SDValue &Index);
    261 
    262     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
    263     /// inline asm expressions.
    264     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
    265                                               char ConstraintCode,
    266                                               std::vector<SDValue> &OutOps) {
    267       SDValue Op0, Op1;
    268       switch (ConstraintCode) {
    269       default: return true;
    270       case 'm':   // memory
    271         if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
    272             && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
    273           SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
    274         break;
    275       case 'o':   // offsetable
    276         if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
    277             && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
    278           Op0 = Op;
    279           Op1 = getSmallIPtrImm(0);
    280         }
    281         break;
    282       case 'v':   // not offsetable
    283 #if 1
    284         llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
    285 #else
    286         SelectAddrIdxOnly(Op, Op, Op0, Op1);
    287         break;
    288 #endif
    289       }
    290 
    291       OutOps.push_back(Op0);
    292       OutOps.push_back(Op1);
    293       return false;
    294     }
    295 
    296     virtual const char *getPassName() const {
    297       return "Cell SPU DAG->DAG Pattern Instruction Selection";
    298     }
    299 
    300   private:
    301     SDValue getRC( MVT );
    302 
    303     // Include the pieces autogenerated from the target description.
    304 #include "SPUGenDAGISel.inc"
    305   };
    306 }
    307 
    308 /*!
    309  \arg Op The ISD instruction operand
    310  \arg N The address to be tested
    311  \arg Base The base address
    312  \arg Index The base address index
    313  */
    314 bool
    315 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
    316                     SDValue &Index) {
    317   // These match the addr256k operand type:
    318   EVT OffsVT = MVT::i16;
    319   SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
    320   int64_t val;
    321 
    322   switch (N.getOpcode()) {
    323   case ISD::Constant:
    324     val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue();
    325     Base = CurDAG->getTargetConstant( val , MVT::i32);
    326     Index = Zero;
    327     return true;
    328   case ISD::ConstantPool:
    329   case ISD::GlobalAddress:
    330     report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
    331     /*NOTREACHED*/
    332 
    333   case ISD::TargetConstant:
    334   case ISD::TargetGlobalAddress:
    335   case ISD::TargetJumpTable:
    336     report_fatal_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
    337                       "not wrapped as A-form address.");
    338     /*NOTREACHED*/
    339 
    340   case SPUISD::AFormAddr:
    341     // Just load from memory if there's only a single use of the location,
    342     // otherwise, this will get handled below with D-form offset addresses
    343     if (N.hasOneUse()) {
    344       SDValue Op0 = N.getOperand(0);
    345       switch (Op0.getOpcode()) {
    346       case ISD::TargetConstantPool:
    347       case ISD::TargetJumpTable:
    348         Base = Op0;
    349         Index = Zero;
    350         return true;
    351 
    352       case ISD::TargetGlobalAddress: {
    353         GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
    354         const GlobalValue *GV = GSDN->getGlobal();
    355         if (GV->getAlignment() == 16) {
    356           Base = Op0;
    357           Index = Zero;
    358           return true;
    359         }
    360         break;
    361       }
    362       }
    363     }
    364     break;
    365   }
    366   return false;
    367 }
    368 
    369 bool
    370 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
    371                                   SDValue &Base) {
    372   const int minDForm2Offset = -(1 << 7);
    373   const int maxDForm2Offset = (1 << 7) - 1;
    374   return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
    375                                maxDForm2Offset);
    376 }
    377 
    378 /*!
    379   \arg Op The ISD instruction (ignored)
    380   \arg N The address to be tested
    381   \arg Base Base address register/pointer
    382   \arg Index Base address index
    383 
    384   Examine the input address by a base register plus a signed 10-bit
    385   displacement, [r+I10] (D-form address).
    386 
    387   \return true if \a N is a D-form address with \a Base and \a Index set
    388   to non-empty SDValue instances.
    389 */
    390 bool
    391 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
    392                                  SDValue &Index) {
    393   return DFormAddressPredicate(Op, N, Base, Index,
    394                                SPUFrameLowering::minFrameOffset(),
    395                                SPUFrameLowering::maxFrameOffset());
    396 }
    397 
    398 bool
    399 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
    400                                       SDValue &Index, int minOffset,
    401                                       int maxOffset) {
    402   unsigned Opc = N.getOpcode();
    403   EVT PtrTy = SPUtli.getPointerTy();
    404 
    405   if (Opc == ISD::FrameIndex) {
    406     // Stack frame index must be less than 512 (divided by 16):
    407     FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(N);
    408     int FI = int(FIN->getIndex());
    409     DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
    410                << FI << "\n");
    411     if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
    412       Base = CurDAG->getTargetConstant(0, PtrTy);
    413       Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
    414       return true;
    415     }
    416   } else if (Opc == ISD::ADD) {
    417     // Generated by getelementptr
    418     const SDValue Op0 = N.getOperand(0);
    419     const SDValue Op1 = N.getOperand(1);
    420 
    421     if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
    422         || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
    423       Base = CurDAG->getTargetConstant(0, PtrTy);
    424       Index = N;
    425       return true;
    426     } else if (Op1.getOpcode() == ISD::Constant
    427                || Op1.getOpcode() == ISD::TargetConstant) {
    428       ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
    429       int32_t offset = int32_t(CN->getSExtValue());
    430 
    431       if (Op0.getOpcode() == ISD::FrameIndex) {
    432         FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op0);
    433         int FI = int(FIN->getIndex());
    434         DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
    435                    << " frame index = " << FI << "\n");
    436 
    437         if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
    438           Base = CurDAG->getTargetConstant(offset, PtrTy);
    439           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
    440           return true;
    441         }
    442       } else if (offset > minOffset && offset < maxOffset) {
    443         Base = CurDAG->getTargetConstant(offset, PtrTy);
    444         Index = Op0;
    445         return true;
    446       }
    447     } else if (Op0.getOpcode() == ISD::Constant
    448                || Op0.getOpcode() == ISD::TargetConstant) {
    449       ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
    450       int32_t offset = int32_t(CN->getSExtValue());
    451 
    452       if (Op1.getOpcode() == ISD::FrameIndex) {
    453         FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op1);
    454         int FI = int(FIN->getIndex());
    455         DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
    456                    << " frame index = " << FI << "\n");
    457 
    458         if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
    459           Base = CurDAG->getTargetConstant(offset, PtrTy);
    460           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
    461           return true;
    462         }
    463       } else if (offset > minOffset && offset < maxOffset) {
    464         Base = CurDAG->getTargetConstant(offset, PtrTy);
    465         Index = Op1;
    466         return true;
    467       }
    468     }
    469   } else if (Opc == SPUISD::IndirectAddr) {
    470     // Indirect with constant offset -> D-Form address
    471     const SDValue Op0 = N.getOperand(0);
    472     const SDValue Op1 = N.getOperand(1);
    473 
    474     if (Op0.getOpcode() == SPUISD::Hi
    475         && Op1.getOpcode() == SPUISD::Lo) {
    476       // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
    477       Base = CurDAG->getTargetConstant(0, PtrTy);
    478       Index = N;
    479       return true;
    480     } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
    481       int32_t offset = 0;
    482       SDValue idxOp;
    483 
    484       if (isa<ConstantSDNode>(Op1)) {
    485         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
    486         offset = int32_t(CN->getSExtValue());
    487         idxOp = Op0;
    488       } else if (isa<ConstantSDNode>(Op0)) {
    489         ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
    490         offset = int32_t(CN->getSExtValue());
    491         idxOp = Op1;
    492       }
    493 
    494       if (offset >= minOffset && offset <= maxOffset) {
    495         Base = CurDAG->getTargetConstant(offset, PtrTy);
    496         Index = idxOp;
    497         return true;
    498       }
    499     }
    500   } else if (Opc == SPUISD::AFormAddr) {
    501     Base = CurDAG->getTargetConstant(0, N.getValueType());
    502     Index = N;
    503     return true;
    504   } else if (Opc == SPUISD::LDRESULT) {
    505     Base = CurDAG->getTargetConstant(0, N.getValueType());
    506     Index = N;
    507     return true;
    508   } else if (Opc == ISD::Register
    509            ||Opc == ISD::CopyFromReg
    510            ||Opc == ISD::UNDEF
    511            ||Opc == ISD::Constant) {
    512     unsigned OpOpc = Op->getOpcode();
    513 
    514     if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
    515       // Direct load/store without getelementptr
    516       SDValue Offs;
    517 
    518       Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
    519 
    520       if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
    521         if (Offs.getOpcode() == ISD::UNDEF)
    522           Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
    523 
    524         Base = Offs;
    525         Index = N;
    526         return true;
    527       }
    528     } else {
    529       /* If otherwise unadorned, default to D-form address with 0 offset: */
    530       if (Opc == ISD::CopyFromReg) {
    531         Index = N.getOperand(1);
    532       } else {
    533         Index = N;
    534       }
    535 
    536       Base = CurDAG->getTargetConstant(0, Index.getValueType());
    537       return true;
    538     }
    539   }
    540 
    541   return false;
    542 }
    543 
    544 /*!
    545   \arg Op The ISD instruction operand
    546   \arg N The address operand
    547   \arg Base The base pointer operand
    548   \arg Index The offset/index operand
    549 
    550   If the address \a N can be expressed as an A-form or D-form address, returns
    551   false.  Otherwise, creates two operands, Base and Index that will become the
    552   (r)(r) X-form address.
    553 */
    554 bool
    555 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
    556                                  SDValue &Index) {
    557   if (!SelectAFormAddr(Op, N, Base, Index)
    558       && !SelectDFormAddr(Op, N, Base, Index)) {
    559     // If the address is neither A-form or D-form, punt and use an X-form
    560     // address:
    561     Base = N.getOperand(1);
    562     Index = N.getOperand(0);
    563     return true;
    564   }
    565 
    566   return false;
    567 }
    568 
    569 /*!
    570  Utility function to use with COPY_TO_REGCLASS instructions. Returns a SDValue
    571  to be used as the last parameter of a
    572 CurDAG->getMachineNode(COPY_TO_REGCLASS,..., ) function call
    573  \arg VT the value type for which we want a register class
    574 */
    575 SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
    576   switch( VT.SimpleTy ) {
    577   case MVT::i8:
    578     return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32);
    579   case MVT::i16:
    580     return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32);
    581   case MVT::i32:
    582     return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
    583   case MVT::f32:
    584     return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32);
    585   case MVT::i64:
    586     return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
    587   case MVT::i128:
    588     return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32);
    589   case MVT::v16i8:
    590   case MVT::v8i16:
    591   case MVT::v4i32:
    592   case MVT::v4f32:
    593   case MVT::v2i64:
    594   case MVT::v2f64:
    595     return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
    596   default:
    597     assert( false && "add a new case here" );
    598     return SDValue();
    599   }
    600 }
    601 
    602 //! Convert the operand from a target-independent to a target-specific node
    603 /*!
    604  */
    605 SDNode *
    606 SPUDAGToDAGISel::Select(SDNode *N) {
    607   unsigned Opc = N->getOpcode();
    608   int n_ops = -1;
    609   unsigned NewOpc = 0;
    610   EVT OpVT = N->getValueType(0);
    611   SDValue Ops[8];
    612   DebugLoc dl = N->getDebugLoc();
    613 
    614   if (N->isMachineOpcode())
    615     return NULL;   // Already selected.
    616 
    617   if (Opc == ISD::FrameIndex) {
    618     int FI = cast<FrameIndexSDNode>(N)->getIndex();
    619     SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
    620     SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
    621 
    622     if (FI < 128) {
    623       NewOpc = SPU::AIr32;
    624       Ops[0] = TFI;
    625       Ops[1] = Imm0;
    626       n_ops = 2;
    627     } else {
    628       NewOpc = SPU::Ar32;
    629       Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
    630       Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
    631                                               N->getValueType(0), TFI),
    632                        0);
    633       n_ops = 2;
    634     }
    635   } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
    636     // Catch the i64 constants that end up here. Note: The backend doesn't
    637     // attempt to legalize the constant (it's useless because DAGCombiner
    638     // will insert 64-bit constants and we can't stop it).
    639     return SelectI64Constant(N, OpVT, N->getDebugLoc());
    640   } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
    641              && OpVT == MVT::i64) {
    642     SDValue Op0 = N->getOperand(0);
    643     EVT Op0VT = Op0.getValueType();
    644     EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
    645                                     Op0VT, (128 / Op0VT.getSizeInBits()));
    646     EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
    647                                    OpVT, (128 / OpVT.getSizeInBits()));
    648     SDValue shufMask;
    649 
    650     switch (Op0VT.getSimpleVT().SimpleTy) {
    651     default:
    652       report_fatal_error("CellSPU Select: Unhandled zero/any extend EVT");
    653       /*NOTREACHED*/
    654     case MVT::i32:
    655       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
    656                                  CurDAG->getConstant(0x80808080, MVT::i32),
    657                                  CurDAG->getConstant(0x00010203, MVT::i32),
    658                                  CurDAG->getConstant(0x80808080, MVT::i32),
    659                                  CurDAG->getConstant(0x08090a0b, MVT::i32));
    660       break;
    661 
    662     case MVT::i16:
    663       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
    664                                  CurDAG->getConstant(0x80808080, MVT::i32),
    665                                  CurDAG->getConstant(0x80800203, MVT::i32),
    666                                  CurDAG->getConstant(0x80808080, MVT::i32),
    667                                  CurDAG->getConstant(0x80800a0b, MVT::i32));
    668       break;
    669 
    670     case MVT::i8:
    671       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
    672                                  CurDAG->getConstant(0x80808080, MVT::i32),
    673                                  CurDAG->getConstant(0x80808003, MVT::i32),
    674                                  CurDAG->getConstant(0x80808080, MVT::i32),
    675                                  CurDAG->getConstant(0x8080800b, MVT::i32));
    676       break;
    677     }
    678 
    679     SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
    680 
    681     HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
    682                                                Op0VecVT, Op0));
    683 
    684     SDValue PromScalar;
    685     if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
    686       PromScalar = SDValue(N, 0);
    687     else
    688       PromScalar = PromoteScalar.getValue();
    689 
    690     SDValue zextShuffle =
    691             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
    692                             PromScalar, PromScalar,
    693                             SDValue(shufMaskLoad, 0));
    694 
    695     HandleSDNode Dummy2(zextShuffle);
    696     if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
    697       zextShuffle = SDValue(N, 0);
    698     else
    699       zextShuffle = Dummy2.getValue();
    700     HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
    701                                        zextShuffle));
    702 
    703     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
    704     SelectCode(Dummy.getValue().getNode());
    705     return Dummy.getValue().getNode();
    706   } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
    707     SDNode *CGLoad =
    708             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
    709 
    710     HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
    711                                        N->getOperand(0), N->getOperand(1),
    712                                        SDValue(CGLoad, 0)));
    713 
    714     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
    715     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
    716       return N;
    717     return Dummy.getValue().getNode();
    718   } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
    719     SDNode *CGLoad =
    720             emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
    721 
    722     HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
    723                                        N->getOperand(0), N->getOperand(1),
    724                                        SDValue(CGLoad, 0)));
    725 
    726     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
    727     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
    728       return N;
    729     return Dummy.getValue().getNode();
    730   } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
    731     SDNode *CGLoad =
    732             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
    733 
    734     HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
    735                                        N->getOperand(0), N->getOperand(1),
    736                                        SDValue(CGLoad, 0)));
    737     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
    738     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
    739       return N;
    740     return Dummy.getValue().getNode();
    741   } else if (Opc == ISD::TRUNCATE) {
    742     SDValue Op0 = N->getOperand(0);
    743     if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
    744         && OpVT == MVT::i32
    745         && Op0.getValueType() == MVT::i64) {
    746       // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
    747       //
    748       // Take advantage of the fact that the upper 32 bits are in the
    749       // i32 preferred slot and avoid shuffle gymnastics:
    750       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
    751       if (CN != 0) {
    752         unsigned shift_amt = unsigned(CN->getZExtValue());
    753 
    754         if (shift_amt >= 32) {
    755           SDNode *hi32 =
    756                   CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
    757                                          Op0.getOperand(0), getRC(MVT::i32));
    758 
    759           shift_amt -= 32;
    760           if (shift_amt > 0) {
    761             // Take care of the additional shift, if present:
    762             SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
    763             unsigned Opc = SPU::ROTMAIr32_i32;
    764 
    765             if (Op0.getOpcode() == ISD::SRL)
    766               Opc = SPU::ROTMr32;
    767 
    768             hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
    769                                           shift);
    770           }
    771 
    772           return hi32;
    773         }
    774       }
    775     }
    776   } else if (Opc == ISD::SHL) {
    777     if (OpVT == MVT::i64)
    778       return SelectSHLi64(N, OpVT);
    779   } else if (Opc == ISD::SRL) {
    780     if (OpVT == MVT::i64)
    781       return SelectSRLi64(N, OpVT);
    782   } else if (Opc == ISD::SRA) {
    783     if (OpVT == MVT::i64)
    784       return SelectSRAi64(N, OpVT);
    785   } else if (Opc == ISD::FNEG
    786              && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
    787     DebugLoc dl = N->getDebugLoc();
    788     // Check if the pattern is a special form of DFNMS:
    789     // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
    790     SDValue Op0 = N->getOperand(0);
    791     if (Op0.getOpcode() == ISD::FSUB) {
    792       SDValue Op00 = Op0.getOperand(0);
    793       if (Op00.getOpcode() == ISD::FMUL) {
    794         unsigned Opc = SPU::DFNMSf64;
    795         if (OpVT == MVT::v2f64)
    796           Opc = SPU::DFNMSv2f64;
    797 
    798         return CurDAG->getMachineNode(Opc, dl, OpVT,
    799                                       Op00.getOperand(0),
    800                                       Op00.getOperand(1),
    801                                       Op0.getOperand(1));
    802       }
    803     }
    804 
    805     SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
    806     SDNode *signMask = 0;
    807     unsigned Opc = SPU::XORfneg64;
    808 
    809     if (OpVT == MVT::f64) {
    810       signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
    811     } else if (OpVT == MVT::v2f64) {
    812       Opc = SPU::XORfnegvec;
    813       signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
    814                                                  MVT::v2i64,
    815                                                  negConst, negConst).getNode());
    816     }
    817 
    818     return CurDAG->getMachineNode(Opc, dl, OpVT,
    819                                   N->getOperand(0), SDValue(signMask, 0));
    820   } else if (Opc == ISD::FABS) {
    821     if (OpVT == MVT::f64) {
    822       SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
    823       return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
    824                                     N->getOperand(0), SDValue(signMask, 0));
    825     } else if (OpVT == MVT::v2f64) {
    826       SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
    827       SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
    828                                        absConst, absConst);
    829       SDNode *signMask = emitBuildVector(absVec.getNode());
    830       return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
    831                                     N->getOperand(0), SDValue(signMask, 0));
    832     }
    833   } else if (Opc == SPUISD::LDRESULT) {
    834     // Custom select instructions for LDRESULT
    835     EVT VT = N->getValueType(0);
    836     SDValue Arg = N->getOperand(0);
    837     SDValue Chain = N->getOperand(1);
    838     SDNode *Result;
    839 
    840     Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT,
    841                                     MVT::Other, Arg,
    842                                     getRC( VT.getSimpleVT()), Chain);
    843     return Result;
    844 
    845   } else if (Opc == SPUISD::IndirectAddr) {
    846     // Look at the operands: SelectCode() will catch the cases that aren't
    847     // specifically handled here.
    848     //
    849     // SPUInstrInfo catches the following patterns:
    850     // (SPUindirect (SPUhi ...), (SPUlo ...))
    851     // (SPUindirect $sp, imm)
    852     EVT VT = N->getValueType(0);
    853     SDValue Op0 = N->getOperand(0);
    854     SDValue Op1 = N->getOperand(1);
    855     RegisterSDNode *RN;
    856 
    857     if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
    858         || (Op0.getOpcode() == ISD::Register
    859             && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
    860                 && RN->getReg() != SPU::R1))) {
    861       NewOpc = SPU::Ar32;
    862       Ops[1] = Op1;
    863       if (Op1.getOpcode() == ISD::Constant) {
    864         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
    865         Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
    866         if (isInt<10>(CN->getSExtValue())) {
    867           NewOpc = SPU::AIr32;
    868           Ops[1] = Op1;
    869         } else {
    870           Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
    871                                                   N->getValueType(0),
    872                                                   Op1),
    873                            0);
    874         }
    875       }
    876       Ops[0] = Op0;
    877       n_ops = 2;
    878     }
    879   }
    880 
    881   if (n_ops > 0) {
    882     if (N->hasOneUse())
    883       return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
    884     else
    885       return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
    886   } else
    887     return SelectCode(N);
    888 }
    889 
    890 /*!
    891  * Emit the instruction sequence for i64 left shifts. The basic algorithm
    892  * is to fill the bottom two word slots with zeros so that zeros are shifted
    893  * in as the entire quadword is shifted left.
    894  *
    895  * \note This code could also be used to implement v2i64 shl.
    896  *
    897  * @param Op The shl operand
    898  * @param OpVT Op's machine value value type (doesn't need to be passed, but
    899  * makes life easier.)
    900  * @return The SDNode with the entire instruction sequence
    901  */
    902 SDNode *
    903 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
    904   SDValue Op0 = N->getOperand(0);
    905   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
    906                                OpVT, (128 / OpVT.getSizeInBits()));
    907   SDValue ShiftAmt = N->getOperand(1);
    908   EVT ShiftAmtVT = ShiftAmt.getValueType();
    909   SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
    910   SDValue SelMaskVal;
    911   DebugLoc dl = N->getDebugLoc();
    912 
    913   VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
    914                                   Op0, getRC(MVT::v2i64) );
    915   SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
    916   SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
    917   ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
    918                                     CurDAG->getTargetConstant(0, OpVT));
    919   VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
    920                                   SDValue(ZeroFill, 0),
    921                                   SDValue(VecOp0, 0),
    922                                   SDValue(SelMask, 0));
    923 
    924   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
    925     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
    926     unsigned bits = unsigned(CN->getZExtValue()) & 7;
    927 
    928     if (bytes > 0) {
    929       Shift =
    930         CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
    931                                SDValue(VecOp0, 0),
    932                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
    933     }
    934 
    935     if (bits > 0) {
    936       Shift =
    937         CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
    938                                SDValue((Shift != 0 ? Shift : VecOp0), 0),
    939                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
    940     }
    941   } else {
    942     SDNode *Bytes =
    943       CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
    944                              ShiftAmt,
    945                              CurDAG->getTargetConstant(3, ShiftAmtVT));
    946     SDNode *Bits =
    947       CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
    948                              ShiftAmt,
    949                              CurDAG->getTargetConstant(7, ShiftAmtVT));
    950     Shift =
    951       CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
    952                              SDValue(VecOp0, 0), SDValue(Bytes, 0));
    953     Shift =
    954       CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
    955                              SDValue(Shift, 0), SDValue(Bits, 0));
    956   }
    957 
    958   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
    959                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
    960 }
    961 
    962 /*!
    963  * Emit the instruction sequence for i64 logical right shifts.
    964  *
    965  * @param Op The shl operand
    966  * @param OpVT Op's machine value value type (doesn't need to be passed, but
    967  * makes life easier.)
    968  * @return The SDNode with the entire instruction sequence
    969  */
    970 SDNode *
    971 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
    972   SDValue Op0 = N->getOperand(0);
    973   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
    974                                OpVT, (128 / OpVT.getSizeInBits()));
    975   SDValue ShiftAmt = N->getOperand(1);
    976   EVT ShiftAmtVT = ShiftAmt.getValueType();
    977   SDNode *VecOp0, *Shift = 0;
    978   DebugLoc dl = N->getDebugLoc();
    979 
    980   VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
    981                                   Op0, getRC(MVT::v2i64) );
    982 
    983   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
    984     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
    985     unsigned bits = unsigned(CN->getZExtValue()) & 7;
    986 
    987     if (bytes > 0) {
    988       Shift =
    989         CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
    990                                SDValue(VecOp0, 0),
    991                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
    992     }
    993 
    994     if (bits > 0) {
    995       Shift =
    996         CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
    997                                SDValue((Shift != 0 ? Shift : VecOp0), 0),
    998                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
    999     }
   1000   } else {
   1001     SDNode *Bytes =
   1002       CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
   1003                              ShiftAmt,
   1004                              CurDAG->getTargetConstant(3, ShiftAmtVT));
   1005     SDNode *Bits =
   1006       CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
   1007                              ShiftAmt,
   1008                              CurDAG->getTargetConstant(7, ShiftAmtVT));
   1009 
   1010     // Ensure that the shift amounts are negated!
   1011     Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
   1012                                    SDValue(Bytes, 0),
   1013                                    CurDAG->getTargetConstant(0, ShiftAmtVT));
   1014 
   1015     Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
   1016                                   SDValue(Bits, 0),
   1017                                   CurDAG->getTargetConstant(0, ShiftAmtVT));
   1018 
   1019     Shift =
   1020       CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
   1021                              SDValue(VecOp0, 0), SDValue(Bytes, 0));
   1022     Shift =
   1023       CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
   1024                              SDValue(Shift, 0), SDValue(Bits, 0));
   1025   }
   1026 
   1027   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
   1028                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
   1029 }
   1030 
   1031 /*!
   1032  * Emit the instruction sequence for i64 arithmetic right shifts.
   1033  *
   1034  * @param Op The shl operand
   1035  * @param OpVT Op's machine value value type (doesn't need to be passed, but
   1036  * makes life easier.)
   1037  * @return The SDNode with the entire instruction sequence
   1038  */
   1039 SDNode *
   1040 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
   1041   // Promote Op0 to vector
   1042   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
   1043                                OpVT, (128 / OpVT.getSizeInBits()));
   1044   SDValue ShiftAmt = N->getOperand(1);
   1045   EVT ShiftAmtVT = ShiftAmt.getValueType();
   1046   DebugLoc dl = N->getDebugLoc();
   1047 
   1048   SDNode *VecOp0 =
   1049     CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
   1050                            VecVT, N->getOperand(0), getRC(MVT::v2i64));
   1051 
   1052   SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
   1053   SDNode *SignRot =
   1054     CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
   1055                            SDValue(VecOp0, 0), SignRotAmt);
   1056   SDNode *UpperHalfSign =
   1057     CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
   1058                            MVT::i32, SDValue(SignRot, 0), getRC(MVT::i32));
   1059 
   1060   SDNode *UpperHalfSignMask =
   1061     CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
   1062   SDNode *UpperLowerMask =
   1063     CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
   1064                            CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
   1065   SDNode *UpperLowerSelect =
   1066     CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
   1067                            SDValue(UpperHalfSignMask, 0),
   1068                            SDValue(VecOp0, 0),
   1069                            SDValue(UpperLowerMask, 0));
   1070 
   1071   SDNode *Shift = 0;
   1072 
   1073   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
   1074     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
   1075     unsigned bits = unsigned(CN->getZExtValue()) & 7;
   1076 
   1077     if (bytes > 0) {
   1078       bytes = 31 - bytes;
   1079       Shift =
   1080         CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
   1081                                SDValue(UpperLowerSelect, 0),
   1082                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
   1083     }
   1084 
   1085     if (bits > 0) {
   1086       bits = 8 - bits;
   1087       Shift =
   1088         CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
   1089                                SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
   1090                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
   1091     }
   1092   } else {
   1093     SDNode *NegShift =
   1094       CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
   1095                              ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
   1096 
   1097     Shift =
   1098       CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
   1099                              SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
   1100     Shift =
   1101       CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
   1102                              SDValue(Shift, 0), SDValue(NegShift, 0));
   1103   }
   1104 
   1105   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
   1106                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
   1107 }
   1108 
   1109 /*!
   1110  Do the necessary magic necessary to load a i64 constant
   1111  */
   1112 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
   1113                                            DebugLoc dl) {
   1114   ConstantSDNode *CN = cast<ConstantSDNode>(N);
   1115   return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
   1116 }
   1117 
   1118 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
   1119                                            DebugLoc dl) {
   1120   EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
   1121   SDValue i64vec =
   1122           SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
   1123 
   1124   // Here's where it gets interesting, because we have to parse out the
   1125   // subtree handed back in i64vec:
   1126 
   1127   if (i64vec.getOpcode() == ISD::BITCAST) {
   1128     // The degenerate case where the upper and lower bits in the splat are
   1129     // identical:
   1130     SDValue Op0 = i64vec.getOperand(0);
   1131 
   1132     ReplaceUses(i64vec, Op0);
   1133     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
   1134                                   SDValue(emitBuildVector(Op0.getNode()), 0),
   1135                                   getRC(MVT::i64));
   1136   } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
   1137     SDValue lhs = i64vec.getOperand(0);
   1138     SDValue rhs = i64vec.getOperand(1);
   1139     SDValue shufmask = i64vec.getOperand(2);
   1140 
   1141     if (lhs.getOpcode() == ISD::BITCAST) {
   1142       ReplaceUses(lhs, lhs.getOperand(0));
   1143       lhs = lhs.getOperand(0);
   1144     }
   1145 
   1146     SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
   1147                        ? lhs.getNode()
   1148                        : emitBuildVector(lhs.getNode()));
   1149 
   1150     if (rhs.getOpcode() == ISD::BITCAST) {
   1151       ReplaceUses(rhs, rhs.getOperand(0));
   1152       rhs = rhs.getOperand(0);
   1153     }
   1154 
   1155     SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
   1156                        ? rhs.getNode()
   1157                        : emitBuildVector(rhs.getNode()));
   1158 
   1159     if (shufmask.getOpcode() == ISD::BITCAST) {
   1160       ReplaceUses(shufmask, shufmask.getOperand(0));
   1161       shufmask = shufmask.getOperand(0);
   1162     }
   1163 
   1164     SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
   1165                             ? shufmask.getNode()
   1166                             : emitBuildVector(shufmask.getNode()));
   1167 
   1168    SDValue shufNode =
   1169             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
   1170                                    SDValue(lhsNode, 0), SDValue(rhsNode, 0),
   1171                                    SDValue(shufMaskNode, 0));
   1172     HandleSDNode Dummy(shufNode);
   1173     SDNode *SN = SelectCode(Dummy.getValue().getNode());
   1174     if (SN == 0) SN = Dummy.getValue().getNode();
   1175 
   1176     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
   1177                                   OpVT, SDValue(SN, 0), getRC(MVT::i64));
   1178   } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
   1179     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
   1180                                   SDValue(emitBuildVector(i64vec.getNode()), 0),
   1181                                   getRC(MVT::i64));
   1182   } else {
   1183     report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
   1184                       "condition");
   1185   }
   1186 }
   1187 
   1188 /// createSPUISelDag - This pass converts a legalized DAG into a
   1189 /// SPU-specific DAG, ready for instruction scheduling.
   1190 ///
   1191 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
   1192   return new SPUDAGToDAGISel(TM);
   1193 }
   1194