| /external/clang/test/CodeGenCXX/ |
| new-overflow.cpp | 15 // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32
37 // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32
61 // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32
87 // CHECK: [[N:%.*]] = sext i16 {{%.*}} to i32
97 // test4 with no sext required.
|
| /external/llvm/lib/Target/X86/ |
| X86InstrExtension.td | 50 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB;
56 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB;
101 [(set GR64:$dst, (sext GR8:$src))], IIC_MOVSX>, TB;
108 [(set GR64:$dst, (sext GR16:$src))], IIC_MOVSX>, TB;
115 [(set GR64:$dst, (sext GR32:$src))], IIC_MOVSX>;
|
| /external/llvm/test/CodeGen/ARM/ |
| vget_lane.ll | 10 %tmp3 = sext i8 %tmp2 to i32
19 %tmp3 = sext i16 %tmp2 to i32
56 %tmp3 = sext i8 %tmp2 to i32
65 %tmp3 = sext i16 %tmp2 to i32
224 %tmp3 = sext i8 %tmp2 to i32
|
| fast-isel.ll | 96 %b3 = sext i8 %b2 to i16
98 %b4 = sext i16 %b3 to i32
116 %c5 = sext i16 %c2 to i32
|
| vector-DAGCombine.ll | 68 %0 = sext <4 x i1> zeroinitializer to <4 x i16>
127 ; constant folding the multiply because the "sext undef" was translated to
131 %1 = sext <8 x i8> undef to <8 x i16>
|
| /external/llvm/test/Transforms/InstCombine/ |
| or.ll | 341 %and.i135 = sext <4 x i1> %and.i1352 to <4 x i32> ; <<4 x i32>> [#uses=2]
397 %sext = sext i1 %tobool to i32
399 %or = or i32 %sext, %x
407 %sext = sext i1 %tobool to i32
409 %or = or i32 %x, %sext
|
| select.ll | 354 ; CHECK-NEXT: sext i32
595 ; CHECK-NEXT: %b = sext i1 %cond to i32
601 %a_ext = sext i32 %a to i64
606 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
613 %a_ext = sext i32 %a to i64
618 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
647 %a_ext = sext i32 %a to i64
652 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
659 %a_ext = sext i32 %a to i64
664 ; CHECK-NEXT: %a_ext = sext i32 %a to i6
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 61 /// (sext (add LHS, RHS)) === (add (sext LHS), (sext RHS))
119 // If we have ADD(XOR(AND(X, 0xFF), 0x80), 0xF..F80), it's a sext.
120 // If we have ADD(XOR(AND(X, 0xFF), 0xF..F80), 0x80), it's a sext.
136 Value *NewShl = Builder->CreateShl(XorLHS, ShAmt, "sext");
298 // Check for (add (sext x), y), see if we can merge this into an
299 // integer add followed by a sext.
301 // (add (sext x), cst) --> (sext (add x, cst')
[all...] |
| /external/llvm/test/Analysis/ScalarEvolution/ |
| nsw.ll | 21 %tmp2 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
25 %tmp6 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
36 %phitmp = sext i32 %tmp8 to i64 ; <i64> [#uses=1]
|
| 2012-03-26-LoadConstant.ll | 27 %idxprom = sext i32 %0 to i64
|
| avoid-infinite-recursion-0.ll | 20 %6 = sext i32 %5 to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64intldst.ll | 22 %conv = sext i8 %0 to i64
35 %conv = sext i16 %0 to i64
48 %conv = sext i32 %0 to i64
|
| /external/llvm/test/Transforms/ConstProp/ |
| calls.ll | 50 %sum1.sext = sext i32 %sum1 to i64
51 %b = icmp eq i64 %sum1.sext, %sum2
|
| /external/llvm/test/CodeGen/Generic/ |
| add-with-overflow-24.ll | 10 %sum32 = sext i24 %sum to i32
|
| vector-casts.ll | 30 %r = sext <2 x i8> %t to <2 x i16>
|
| /external/llvm/test/CodeGen/PowerPC/ |
| select_lt0.ll | 19 %tmp.2 = sext i16 %b to i32 ; <i32> [#uses=1]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| 2009-09-28-ITBlockBug.ll | 106 %conv3707 = sext i16 %tmp3706 to i32 ; <i32> [#uses=1]
110 %conv3726 = sext i16 %tmp3725 to i32 ; <i32> [#uses=1]
119 %conv3747 = sext i16 %tmp3746 to i32 ; <i32> [#uses=1]
123 %conv3767 = sext i16 %tmp3766 to i32 ; <i32> [#uses=1]
|
| /external/llvm/test/CodeGen/X86/ |
| 2008-07-23-VSetCC.ll | 9 sext <4 x i1> %X to <4 x i32>
|
| 2010-01-13-OptExtBug.ll | 27 %tmp29 = sext i16 %tmp2 to i32
|
| 2011-06-19-QuicksortCoalescerBug.ll | 12 %idxprom12 = sext i32 %r.tr to i64
|
| inline-asm-mrv.ll | 11 %tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1]
|
| liveness-local-regalloc.ll | 50 %tmp9 = sext i32 %.04 to i64 ; <i64> [#uses=1]
|
| lsr-redundant-addressing.ll | 40 %tmp217 = sext i32 %tmp216 to i64
|
| select.ll | 23 %tmp7778 = sext i16 %g.0 to i32 ; <i32> [#uses=1]
132 %A = sext i1 %cmp to i64
202 %d = sext i1 %c to i32
212 %d = sext i1 %c to i32
|
| sse1.ll | 18 ; %c = sext <4 x i16> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
|
