/external/llvm/lib/CodeGen/ |
RegAllocBase.cpp | 22 #include "llvm/CodeGen/MachineInstr.h" 198 MachineInstr *MI;
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RegisterScavenging.cpp | 22 #include "llvm/CodeGen/MachineInstr.h" 132 MachineInstr *MI = MBBI;
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RegAllocPBQP.cpp | 260 MachineInstr *rmMI = lis->getInstructionFromIndex(rmIdx); 262 for (MachineInstr::mop_iterator mopItr = rmMI->operands_begin(), 394 const MachineInstr *mi = &*miItr;
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BranchFolding.cpp | 166 MachineInstr *ImpDefMI = &*I; 255 static unsigned HashMachineInstr(const MachineInstr *MI) { [all...] |
PrologEpilogInserter.cpp | 27 #include "llvm/CodeGen/MachineInstr.h" 762 MachineInstr *MI = I; 828 MachineInstr *MI = I;
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IfConversion.cpp | [all...] |
LiveInterval.cpp | 246 " (did you def the same reg twice in a MachineInstr?)"); 713 MachineInstr *MI = MO.getParent();
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/external/llvm/lib/Target/CellSPU/ |
SPURegisterInfo.cpp | 258 MachineInstr &MI = *II;
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/external/llvm/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 215 MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 249 MBlazeTargetLowering::EmitCustomShift(MachineInstr *MI, 348 MBlazeTargetLowering::EmitCustomSelect(MachineInstr *MI, 416 MBlazeTargetLowering::EmitCustomAtomic(MachineInstr *MI, [all...] |
/external/llvm/lib/Target/X86/ |
X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 303 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 552 const MachineInstr &MI) { 611 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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X86RegisterInfo.cpp | 417 MachineInstr *New = 0; 452 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr) 474 MachineInstr &MI = *II;
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X86FastISel.cpp | 73 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo, [all...] |
/external/llvm/include/llvm/Target/ |
TargetLowering.h | 46 class MachineInstr; [all...] |
/external/llvm/include/llvm/CodeGen/ |
LiveInterval.h | 33 class MachineInstr;
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/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | 149 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo, 217 bool isARMNEONPred(const MachineInstr *MI); 218 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); 232 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { 246 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) { 268 MachineInstr *MI = &*MIB; [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PTX/ |
PTXAsmPrinter.cpp | 32 #include "llvm/CodeGen/MachineInstr.h" 262 void PTXAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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/external/llvm/lib/CodeGen/AsmPrinter/ |
DwarfException.cpp | 187 bool DwarfException::CallToNoUnwindFunction(const MachineInstr *MI) {
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DwarfCompileUnit.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.h | 56 class MachineInstr;
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FastISel.cpp | 310 MachineInstr *Dead = &*I; [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | 52 static void RemoveVRSaveCode(MachineInstr *MI) { 98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 783 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |