| /external/llvm/tools/llvm-mc/ |
| Disassembler.cpp | 145 MCSubtargetInfo &STI,
150 OwningPtr<const MCDisassembler> DisAsm(T.createMCDisassembler(STI));
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| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 45 if (STI.isTargetIOS())
186 if (STI.isTargetIOS()) {
273 if (STI.isTargetELF() && hasFP(MF))
432 unsigned TCOpcode = STI.isThumb() ?
433 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
446 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
449 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
584 if (!(Func)(Reg, STI.isTargetIOS())) continue;
655 if (!(Func)(Reg, STI.isTargetIOS())) continue;
661 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps())
[all...] |
| MLxExpansionPass.cpp | 316 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
317 isA9 = STI->isCortexA9();
|
| Thumb2InstrInfo.cpp | 32 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI(*this, STI) {
|
| Thumb1FrameLowering.cpp | 103 if (STI.isTargetIOS()) {
149 if (STI.isTargetELF() && hasFP(MF))
|
| ARMBaseInstrInfo.h | 35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
|
| Thumb2SizeReduction.cpp | 137 const ARMSubtarget *STI;
219 if (!STI->avoidCPSRPartialUpdate())
[all...] |
| ARMLoadStoreOptimizer.cpp | 67 const ARMSubtarget *STI;
[all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| EDDisassembler.h | 140 llvm::OwningPtr<const llvm::MCSubtargetInfo> STI;
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | 41 const MCSubtargetInfo* STI;
45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
49 delete STI;
55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
|
| ARMMCCodeEmitter.cpp | 40 const MCSubtargetInfo &STI;
43 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
45 : MCII(mcii), STI(sti) {
52 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
55 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
58 Triple TT(STI.getTargetTriple());
339 const MCSubtargetInfo &STI,
341 return new ARMMCCodeEmitter(MCII, STI, Ctx);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 266 const MCSubtargetInfo &STI) {
|
| HexagonFrameLowering.cpp | 191 if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPR
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 113 const MCSubtargetInfo &STI) {
|
| /external/llvm/tools/llvm-objdump/ |
| llvm-objdump.cpp | 237 OwningPtr<const MCSubtargetInfo> STI(
240 if (!STI) {
246 TheTarget->createMCDisassembler(*STI));
266 AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
|
| MachODump.cpp | 259 STI(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
260 OwningPtr<const MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
265 *MRI, *STI));
267 if (!InstrAnalysis || !AsmInfo || !STI || !DisAsm || !IP) {
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 122 STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(),
126 TAP(TM.getTarget().createMCAsmParser(*STI, *Parser));
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 38 ARMDisassembler(const MCSubtargetInfo &STI) :
39 MCDisassembler(STI) {
63 ThumbDisassembler(const MCSubtargetInfo &STI) :
64 MCDisassembler(STI) {
335 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
336 return new ARMDisassembler(STI);
339 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
340 return new ThumbDisassembler(STI);
360 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
376 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 34 const MCSubtargetInfo &STI;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
39 : MCII(mcii), STI(sti), Ctx(ctx) {
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
51 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
142 const MCSubtargetInfo &STI,
144 return new X86MCCodeEmitter(MCII, STI, Ctx);
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.h | 27 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.cpp | 122 const MCSubtargetInfo &STI) {
|
| /external/llvm/tools/lto/ |
| LTOModule.cpp | 661 OwningPtr<MCSubtargetInfo> STI(_target->getTarget().
666 TAP(_target->getTarget().createMCAsmParser(*STI, *Parser.get()));
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 34 MCSubtargetInfo &STI;
78 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
81 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
94 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
95 : MCTargetAsmParser(), STI(sti), Parser(parser) {
98 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 80 XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
82 STI(sti) {
|
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 718 const MCSubtargetInfo &STI) {
719 return new MBlazeDisassembler(STI);
|
