1 /* 2 * SdioDrv.h 3 * 4 * Copyright(c) 1998 - 2009 Texas Instruments. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name Texas Instruments nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 #ifndef __OMAP3430_SDIODRV_API_H 36 #define __OMAP3430_SDIODRV_API_H 37 38 #include <asm/types.h> 39 #include <linux/mmc/mmc.h> 40 41 /* Card Common Control Registers (CCCR) */ 42 43 #define CCCR_SDIO_REVISION 0x00 44 #define CCCR_SD_SPECIFICATION_REVISION 0x01 45 #define CCCR_IO_ENABLE 0x02 46 #define CCCR_IO_READY 0x03 47 #define CCCR_INT_ENABLE 0x04 48 #define CCCR_INT_PENDING 0x05 49 #define CCCR_IO_ABORT 0x06 50 #define CCCR_BUS_INTERFACE_CONTOROL 0x07 51 #define CCCR_CARD_CAPABILITY 0x08 52 #define CCCR_COMMON_CIS_POINTER 0x09 /*0x09-0x0B*/ 53 #define CCCR_FNO_BLOCK_SIZE 0x10 /*0x10-0x11*/ 54 #define FN0_CCCR_REG_32 0x64 55 56 /* Pprotocol defined constants */ 57 58 #define SD_IO_GO_IDLE_STATE 0 59 #define SD_IO_SEND_RELATIVE_ADDR 3 60 #define SDIO_CMD5 5 61 #define SD_IO_SELECT_CARD 7 62 #define SDIO_CMD52 52 63 #define SDIO_CMD53 53 64 #define SD_IO_SEND_OP_COND SDIO_CMD5 65 #define SD_IO_RW_DIRECT SDIO_CMD52 66 #define SD_IO_RW_EXTENDED SDIO_CMD53 67 #define SDIO_SHIFT(v,n) (v<<n) 68 #define SDIO_RWFLAG(v) (SDIO_SHIFT(v,31)) 69 #define SDIO_FUNCN(v) (SDIO_SHIFT(v,28)) 70 #define SDIO_RAWFLAG(v) (SDIO_SHIFT(v,27)) 71 #define SDIO_BLKM(v) (SDIO_SHIFT(v,27)) 72 #define SDIO_OPCODE(v) (SDIO_SHIFT(v,26)) 73 #define SDIO_ADDRREG(v) (SDIO_SHIFT(v,9)) 74 75 76 #define VDD_VOLTAGE_WINDOW 0xffffc0 77 #define FN2_OBI_INV 0x0002 78 79 #define MMC_RSP_NONE (0 << 0) 80 #define MMC_RSP_SHORT (1 << 0) 81 #define MMC_RSP_LONG (2 << 0) 82 #define MMC_RSP_MASK (3 << 0) 83 #define MMC_RSP_CRC (1 << 3) 84 #define MMC_RSP_BUSY (1 << 4) 85 86 #define MMC_RSP_R1 (MMC_RSP_SHORT|MMC_RSP_CRC) 87 #define MMC_RSP_R1B (MMC_RSP_SHORT|MMC_RSP_CRC|MMC_RSP_BUSY) 88 #define MMC_RSP_R2 (MMC_RSP_LONG|MMC_RSP_CRC) 89 #define MMC_RSP_R3 (MMC_RSP_SHORT) 90 91 /* HSMMC controller bit definitions 92 * */ 93 #define OMAP_HSMMC_CMD_NO_RESPONSE 0 << 0 94 #define OMAP_HSMMC_CMD_LONG_RESPONSE 1 << 0 95 #define OMAP_HSMMC_CMD_SHORT_RESPONSE 2 << 0 96 97 #define MMC_ERR_NONE 0 98 #define MMC_ERR_TIMEOUT 1 99 #define MMC_ERR_BADCRC 2 100 #define MMC_ERR_FIFO 3 101 #define MMC_ERR_FAILED 4 102 #define MMC_ERR_INVALID 5 103 104 #undef MMC_RSP_R4 105 #define MMC_RSP_R4 OMAP_HSMMC_CMD_SHORT_RESPONSE 106 #undef MMC_RSP_R5 107 #define MMC_RSP_R5 OMAP_HSMMC_CMD_SHORT_RESPONSE 108 #undef MMC_RSP_R6 109 #define MMC_RSP_R6 OMAP_HSMMC_CMD_SHORT_RESPONSE 110 111 /********************************************************************/ 112 /* SDIO driver functions prototypes */ 113 /********************************************************************/ 114 int sdioDrv_ConnectBus (void * fCbFunc, 115 void * hCbArg, 116 unsigned int uBlkSizeShift, 117 unsigned int uSdioThreadPriority); 118 119 int sdioDrv_DisconnectBus (void); 120 121 int sdioDrv_ExecuteCmd (unsigned int uCmd, 122 unsigned int uArg, 123 unsigned int uRespType, 124 void * pResponse, 125 unsigned int uLen); 126 127 int sdioDrv_ReadSync (unsigned int uFunc, 128 unsigned int uHwAddr, 129 void * pData, 130 unsigned int uLen, 131 unsigned int bIncAddr, 132 unsigned int bMore); 133 134 int sdioDrv_ReadAsync (unsigned int uFunc, 135 unsigned int uHwAddr, 136 void * pData, 137 unsigned int uLen, 138 unsigned int bBlkMode, 139 unsigned int bIncAddr, 140 unsigned int bMore); 141 142 int sdioDrv_WriteSync (unsigned int uFunc, 143 unsigned int uHwAddr, 144 void * pData, 145 unsigned int uLen, 146 unsigned int bIncAddr, 147 unsigned int bMore); 148 149 int sdioDrv_WriteAsync (unsigned int uFunc, 150 unsigned int uHwAddr, 151 void * pData, 152 unsigned int uLen, 153 unsigned int bBlkMode, 154 unsigned int bIncAddr, 155 unsigned int bMore); 156 157 int sdioDrv_ReadSyncBytes (unsigned int uFunc, 158 unsigned int uHwAddr, 159 unsigned char *pData, 160 unsigned int uLen, 161 unsigned int bMore); 162 163 int sdioDrv_WriteSyncBytes (unsigned int uFunc, 164 unsigned int uHwAddr, 165 unsigned char *pData, 166 unsigned int uLen, 167 unsigned int bMore); 168 169 void sdioDrv_register_pm(int (*wlanDrvIf_Start)(void), 170 int (*wlanDrvIf_Stop)(void)); 171 172 int sdioDrv_clk_enable(void); 173 void sdioDrv_clk_disable(void); 174 void sdioDrv_start_inact_timer(void); 175 void sdioDrv_cancel_inact_timer(void); 176 177 #endif/* _OMAP3430_SDIODRV_H */ 178
