Lines Matching refs:Default
2494 .Default(0);
2532 .Default(ARM_AM::no_shift);
2668 default: return -1;
2673 default: return -1;
2689 default: return -1;
2725 .Default(~0U);
2817 default: llvm_unreachable("Invalid GPR number!");
2832 default: llvm_unreachable("expected a Q register!");
3302 .Default(~0U);
3359 .Default(~0U);
3426 .Default(~0U);
3457 .Default(~0U);
3475 .Default(~0U);
3561 .Default(-1);
4266 default:
4541 default:
4712 .Default(~0U);
4744 .Default(~0U);
5410 default: llvm_unreachable("unexpected opcode!");
5519 default: llvm_unreachable("unexpected opcode!");
6761 default: llvm_unreachable("unexpected opcode");
6797 default: llvm_unreachable("unexpected opcode!");
6831 default: llvm_unreachable("unexpected opcode!");
6863 default: llvm_unreachable("unexpected opcode!");
6888 default: llvm_unreachable("unexpected opcode!");
7235 default: llvm_unreachable("Illegal opcode!");
7282 default: llvm_unreachable("unexpected opcode!");
7350 default: llvm_unreachable("unexpected opcode");
7389 default: llvm_unreachable("unexpected opcode");
7471 default: break;
