Lines Matching defs:BaseReg
166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
169 if ((BaseReg.getReg() != 0 &&
170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
181 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
184 if ((BaseReg.getReg() != 0 &&
185 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
196 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
199 if ((BaseReg.getReg() != 0 &&
200 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
306 unsigned BaseReg = Base.getReg();
309 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
334 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
337 // If no BaseReg, issue a RIP relative instruction only if the MCE can
349 (!is64BitMode() || BaseReg != 0)) {
351 if (BaseReg == 0) { // [disp32] in X86-32 mode
386 if (BaseReg == 0) {
414 if (BaseReg == 0) {
