/external/llvm/include/llvm/Transforms/Utils/ |
AddrModeMatcher.h | 37 Value *BaseReg; 39 ExtAddrMode() : BaseReg(0), ScaledReg(0) {} 44 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
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/external/llvm/lib/Target/X86/InstPrinter/ |
X86ATTInstPrinter.cpp | 138 const MCOperand &BaseReg = MI->getOperand(Op); 151 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) 158 if (IndexReg.getReg() || BaseReg.getReg()) { 160 if (BaseReg.getReg())
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X86IntelInstPrinter.cpp | 129 const MCOperand &BaseReg = MI->getOperand(Op); 144 if (BaseReg.getReg()) { 164 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
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/external/llvm/lib/CodeGen/ |
LocalStackSlotAllocation.cpp | 290 unsigned BaseReg = 0; 310 BaseReg = RegOffset.first; 319 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); 321 DEBUG(dbgs() << " Materializing base register " << BaseReg << 328 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, 339 std::pair<unsigned, int64_t>(BaseReg, BaseOffset)); 343 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); 347 TRI->resolveFrameIndex(I, BaseReg, Offset);
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/external/llvm/lib/Target/X86/ |
X86AsmPrinter.cpp | 312 const MachineOperand &BaseReg = MI->getOperand(Op); 317 bool HasBaseReg = BaseReg.getReg() != 0; 319 BaseReg.getReg() == X86::RIP)
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X86InstrInfo.cpp | [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
X86MCCodeEmitter.cpp | 166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 169 if ((BaseReg.getReg() != 0 && 170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 181 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 184 if ((BaseReg.getReg() != 0 && 185 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 196 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 199 if ((BaseReg.getReg() != 0 && 200 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 306 unsigned BaseReg = Base.getReg() [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | 192 unsigned BaseReg = MI->getOperand(0).getReg(); 194 if (MI->getOperand(i).getReg() == BaseReg) 201 O << '\t' << getRegisterName(BaseReg); [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb2SizeReduction.cpp | 127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent 380 unsigned BaseReg = MI->getOperand(0).getReg(); 381 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) 388 if (MI->getOperand(i).getReg() == BaseReg) { 402 unsigned BaseReg = MI->getOperand(1).getReg(); 403 if (BaseReg != ARM::SP) 416 unsigned BaseReg = MI->getOperand(1).getReg(); 417 if (BaseReg == ARM::SP && 422 } else if (!isARMLowRegister(BaseReg) || [all...] |
ARMBaseInstrInfo.cpp | 154 unsigned BaseReg = Base.getReg(); 170 .addReg(BaseReg).addImm(Amt) 177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) 182 .addReg(BaseReg).addReg(OffReg) 193 .addReg(BaseReg).addImm(Amt) 198 .addReg(BaseReg).addReg(OffReg) 220 .addReg(BaseReg).addImm(0).addImm(Pred); 224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); [all...] |
ARMConstantIslandPass.cpp | [all...] |
ARMLoadStoreOptimizer.cpp | [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | 191 unsigned BaseReg; 240 return Mem.BaseReg; 469 Res->Mem.BaseReg = 0; 478 unsigned BaseReg, unsigned IndexReg, 483 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!"); 491 Res->Mem.BaseReg = BaseReg; 502 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local 508 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0) 512 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local [all...] |
/external/llvm/lib/Transforms/Scalar/ |
LoopStrengthReduce.cpp | 911 const SCEV *BaseReg = *I; 912 if (VisitedRegs.count(BaseReg)) { 916 RatePrimaryRegister(BaseReg, Regs, L, SE, DT, LoserRegs); [all...] |