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      1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Mips implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsAnalyzeImmediate.h"
     15 #include "MipsInstrInfo.h"
     16 #include "MipsTargetMachine.h"
     17 #include "MipsMachineFunction.h"
     18 #include "InstPrinter/MipsInstPrinter.h"
     19 #include "llvm/CodeGen/MachineInstrBuilder.h"
     20 #include "llvm/CodeGen/MachineRegisterInfo.h"
     21 #include "llvm/Support/ErrorHandling.h"
     22 #include "llvm/Support/TargetRegistry.h"
     23 #include "llvm/ADT/STLExtras.h"
     24 
     25 #define GET_INSTRINFO_CTOR
     26 #include "MipsGenInstrInfo.inc"
     27 
     28 using namespace llvm;
     29 
     30 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
     31   : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     32     TM(tm), UncondBrOpc(UncondBr) {}
     33 
     34 const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) {
     35   if (TM.getSubtargetImpl()->inMips16Mode())
     36     return llvm::createMips16InstrInfo(TM);
     37 
     38   return llvm::createMipsSEInstrInfo(TM);
     39 }
     40 
     41 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
     42   return op.isImm() && op.getImm() == 0;
     43 }
     44 
     45 /// insertNoop - If data hazard condition is found insert the target nop
     46 /// instruction.
     47 void MipsInstrInfo::
     48 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
     49 {
     50   DebugLoc DL;
     51   BuildMI(MBB, MI, DL, get(Mips::NOP));
     52 }
     53 
     54 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
     55                                                 unsigned Flag) const {
     56   MachineFunction &MF = *MBB.getParent();
     57   MachineFrameInfo &MFI = *MF.getFrameInfo();
     58   unsigned Align = MFI.getObjectAlignment(FI);
     59 
     60   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
     61                                  MFI.getObjectSize(FI), Align);
     62 }
     63 
     64 MachineInstr*
     65 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
     66                                         uint64_t Offset, const MDNode *MDPtr,
     67                                         DebugLoc DL) const {
     68   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
     69     .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
     70   return &*MIB;
     71 }
     72 
     73 //===----------------------------------------------------------------------===//
     74 // Branch Analysis
     75 //===----------------------------------------------------------------------===//
     76 
     77 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
     78                                   MachineBasicBlock *&BB,
     79                                   SmallVectorImpl<MachineOperand> &Cond) const {
     80   assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
     81   int NumOp = Inst->getNumExplicitOperands();
     82 
     83   // for both int and fp branches, the last explicit operand is the
     84   // MBB.
     85   BB = Inst->getOperand(NumOp-1).getMBB();
     86   Cond.push_back(MachineOperand::CreateImm(Opc));
     87 
     88   for (int i=0; i<NumOp-1; i++)
     89     Cond.push_back(Inst->getOperand(i));
     90 }
     91 
     92 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
     93                                   MachineBasicBlock *&TBB,
     94                                   MachineBasicBlock *&FBB,
     95                                   SmallVectorImpl<MachineOperand> &Cond,
     96                                   bool AllowModify) const
     97 {
     98   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
     99 
    100   // Skip all the debug instructions.
    101   while (I != REnd && I->isDebugValue())
    102     ++I;
    103 
    104   if (I == REnd || !isUnpredicatedTerminator(&*I)) {
    105     // If this block ends with no branches (it just falls through to its succ)
    106     // just return false, leaving TBB/FBB null.
    107     TBB = FBB = NULL;
    108     return false;
    109   }
    110 
    111   MachineInstr *LastInst = &*I;
    112   unsigned LastOpc = LastInst->getOpcode();
    113 
    114   // Not an analyzable branch (must be an indirect jump).
    115   if (!GetAnalyzableBrOpc(LastOpc))
    116     return true;
    117 
    118   // Get the second to last instruction in the block.
    119   unsigned SecondLastOpc = 0;
    120   MachineInstr *SecondLastInst = NULL;
    121 
    122   if (++I != REnd) {
    123     SecondLastInst = &*I;
    124     SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
    125 
    126     // Not an analyzable branch (must be an indirect jump).
    127     if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
    128       return true;
    129   }
    130 
    131   // If there is only one terminator instruction, process it.
    132   if (!SecondLastOpc) {
    133     // Unconditional branch
    134     if (LastOpc == UncondBrOpc) {
    135       TBB = LastInst->getOperand(0).getMBB();
    136       return false;
    137     }
    138 
    139     // Conditional branch
    140     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
    141     return false;
    142   }
    143 
    144   // If we reached here, there are two branches.
    145   // If there are three terminators, we don't know what sort of block this is.
    146   if (++I != REnd && isUnpredicatedTerminator(&*I))
    147     return true;
    148 
    149   // If second to last instruction is an unconditional branch,
    150   // analyze it and remove the last instruction.
    151   if (SecondLastOpc == UncondBrOpc) {
    152     // Return if the last instruction cannot be removed.
    153     if (!AllowModify)
    154       return true;
    155 
    156     TBB = SecondLastInst->getOperand(0).getMBB();
    157     LastInst->eraseFromParent();
    158     return false;
    159   }
    160 
    161   // Conditional branch followed by an unconditional branch.
    162   // The last one must be unconditional.
    163   if (LastOpc != UncondBrOpc)
    164     return true;
    165 
    166   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
    167   FBB = LastInst->getOperand(0).getMBB();
    168 
    169   return false;
    170 }
    171 
    172 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
    173                                 MachineBasicBlock *TBB, DebugLoc DL,
    174                                 const SmallVectorImpl<MachineOperand>& Cond)
    175   const {
    176   unsigned Opc = Cond[0].getImm();
    177   const MCInstrDesc &MCID = get(Opc);
    178   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
    179 
    180   for (unsigned i = 1; i < Cond.size(); ++i)
    181     MIB.addReg(Cond[i].getReg());
    182 
    183   MIB.addMBB(TBB);
    184 }
    185 
    186 unsigned MipsInstrInfo::
    187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
    188              MachineBasicBlock *FBB,
    189              const SmallVectorImpl<MachineOperand> &Cond,
    190              DebugLoc DL) const {
    191   // Shouldn't be a fall through.
    192   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    193 
    194   // # of condition operands:
    195   //  Unconditional branches: 0
    196   //  Floating point branches: 1 (opc)
    197   //  Int BranchZero: 2 (opc, reg)
    198   //  Int Branch: 3 (opc, reg0, reg1)
    199   assert((Cond.size() <= 3) &&
    200          "# of Mips branch conditions must be <= 3!");
    201 
    202   // Two-way Conditional branch.
    203   if (FBB) {
    204     BuildCondBr(MBB, TBB, DL, Cond);
    205     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
    206     return 2;
    207   }
    208 
    209   // One way branch.
    210   // Unconditional branch.
    211   if (Cond.empty())
    212     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
    213   else // Conditional branch.
    214     BuildCondBr(MBB, TBB, DL, Cond);
    215   return 1;
    216 }
    217 
    218 unsigned MipsInstrInfo::
    219 RemoveBranch(MachineBasicBlock &MBB) const
    220 {
    221   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    222   MachineBasicBlock::reverse_iterator FirstBr;
    223   unsigned removed;
    224 
    225   // Skip all the debug instructions.
    226   while (I != REnd && I->isDebugValue())
    227     ++I;
    228 
    229   FirstBr = I;
    230 
    231   // Up to 2 branches are removed.
    232   // Note that indirect branches are not removed.
    233   for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
    234     if (!GetAnalyzableBrOpc(I->getOpcode()))
    235       break;
    236 
    237   MBB.erase(I.base(), FirstBr.base());
    238 
    239   return removed;
    240 }
    241 
    242 /// ReverseBranchCondition - Return the inverse opcode of the
    243 /// specified Branch instruction.
    244 bool MipsInstrInfo::
    245 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
    246 {
    247   assert( (Cond.size() && Cond.size() <= 3) &&
    248           "Invalid Mips branch condition!");
    249   Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
    250   return false;
    251 }
    252 
    253 /// Return the number of bytes of code the specified instruction may be.
    254 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
    255   switch (MI->getOpcode()) {
    256   default:
    257     return MI->getDesc().getSize();
    258   case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
    259     const MachineFunction *MF = MI->getParent()->getParent();
    260     const char *AsmStr = MI->getOperand(0).getSymbolName();
    261     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
    262   }
    263   }
    264 }
    265