/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/reference/vc/m4p10/src/ |
omxVCM4P10_GetVLCInfo.c | 72 OMX_U32 Mask = 4, RunBefore; 129 Value == -1 ? Mask : 0; 130 Mask >>= 1; 136 Mask = 0; 147 /* Mask becomes zero after entering */ 148 if (Mask && 155 Value == -1 ? Mask : 0; 156 Mask >>= 1; 163 if (Mask) 165 Mask = 0 [all...] |
/external/webkit/Source/JavaScriptCore/tests/mozilla/ecma/Expressions/ |
11.4.8.js | 136 function Mask( b, n ) {
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11.7.1.js | 38 7. Mask out all but the least significant 5 bits of Result(6), that is, 143 function Mask( b, n ) { 214 add = Mask( add, 5 );
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11.7.2.js | 38 7. Mask out all but the least significant 5 bits of Result(6), that is, 157 function Mask( b, n ) { 226 a = Mask( a, 5 );
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11.7.3.js | 39 7. Mask out all but the least significant 5 bits of Result(6), that is, 148 function Mask( b, n ) { 228 a = Mask( a, 5 );
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11.10-1.js | 145 function Mask( b, n ) {
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11.10-2.js | 144 function Mask( b, n ) {
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11.10-3.js | 144 function Mask( b, n ) {
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/external/clang/include/clang/AST/ |
DeclAccessPair.h | 32 enum { Mask = 0x3 }; 42 return (NamedDecl*) (~Mask & (uintptr_t) Ptr); 45 return AccessSpecifier(Mask & (uintptr_t) Ptr);
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/hardware/ti/wlan/wl1271/stad/src/Data_link/ |
GeneralUtil.h | 80 TI_UINT16 Mask;
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/external/llvm/lib/Target/ARM/ |
Thumb2InstrInfo.cpp | 80 unsigned Mask = MBBI->getOperand(1).getImm(); 86 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn); 529 unsigned Mask = (1 << NumBits) - 1; 530 if ((unsigned)Offset <= Mask * Scale) { 546 ImmedOffset = ImmedOffset & Mask; 559 Offset &= ~(Mask*Scale);
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Thumb1RegisterInfo.cpp | 425 unsigned Mask = (1 << NumBits) - 1; 426 if (((Offset / Scale) & ~Mask) == 0) { 461 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask)); 464 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask); 466 Offset = (Offset - Mask * Scale); 496 unsigned Mask = (1 << NumBits) - 1; 498 if ((unsigned)Offset <= Mask * Scale) { 513 Mask = (1 << NumBits) - 1; 521 ImmedOffset = ImmedOffset & Mask; 523 Offset &= ~(Mask * Scale) [all...] |
Thumb2ITBlockPass.cpp | 194 unsigned Mask = 0, Pos = 3; 208 Mask |= (NCC & 1) << Pos; 228 // Finalize IT mask. 229 Mask |= (1 << Pos); 230 // Tag along (firstcond[0] << 4) with the mask. 231 Mask |= (CC & 1) << 4; 232 MIB.addImm(Mask);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsAsmBackend.cpp | 133 uint64_t Mask = ((uint64_t)(-1) >> 135 CurVal |= Value & Mask;
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/external/llvm/lib/Target/X86/ |
X86FloatingPoint.cpp | 89 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c. 90 unsigned Mask; 100 LiveBundle() : Mask(0), FixCount(0) {} 103 bool isFixed() const { return !Mask || FixCount; } 115 unsigned Mask = 0; 120 Mask |= 1 << Reg; 122 return Mask; 295 /// Adjust the live registers to be the set in Mask. 296 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I); 396 const unsigned Mask = calcLiveInMask(MBB) [all...] |
/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/X11/ |
Xdefs.h | 75 typedef unsigned long Mask; 77 typedef CARD32 Mask;
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
Xdefs.h | 75 typedef unsigned long Mask; 77 typedef CARD32 Mask;
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
Xdefs.h | 75 typedef unsigned long Mask; 77 typedef CARD32 Mask;
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/external/llvm/lib/Transforms/InstCombine/ |
InstCombineAddSub.cpp | 129 APInt Mask = APInt::getHighBitsSet(TySizeBits, ExtendAmt); 130 if (!MaskedValueIsZero(XorLHS, Mask)) 252 // in the mask. First, get the rightmost bit. 255 // Form a mask of all bits from the lowest bit added through the top. 258 // See if the and mask includes all of these bits.
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InstCombineVectorOps.cpp | 207 /// elements from either LHS or RHS, return the shuffle mask and true. 210 SmallVectorImpl<Constant*> &Mask) { 216 Mask.assign(NumElts, UndefValue::get(Type::getInt32Ty(V->getContext()))); 222 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), i)); 228 Mask.push_back(ConstantInt::get(Type::getInt32Ty(V->getContext()), 246 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) { 247 // If so, update the mask to reflect the inserted undef. 248 Mask[InsertedIdx] = UndefValue::get(Type::getInt32Ty(V->getContext())); 261 if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) { 262 // If so, update the mask to reflect the inserted value [all...] |
/frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
bitstream_io.cpp | 29 static const UChar Mask[ ] = 372 BitstreamPutBits(stream, restBits, Mask[restBits]); 400 BitstreamPutBits(stream,count,Mask[count]);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 449 SDValue Mask = Op.getOperand(0); 453 assert(VT.isVector() && !Mask.getValueType().isVector() 469 // Generate a mask operand. 473 && "Invalid mask size"); 475 // What is the size of each element in the vector mask. 478 Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask, 482 // Broadcast the mask so that the entire vector is all-one or all zero. 483 SmallVector<SDValue, 8> Ops(NumElem, Mask); 484 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size()) [all...] |
/external/clang/lib/CodeGen/ |
TargetInfo.cpp | 942 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align) [all...] |
/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | 383 /// getCallPreservedMask - Return a mask of call-preserved registers for the 384 /// given calling convention on the current sub-target. The mask should 388 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 390 /// preserved across the function call. The bit mask is expected to be 395 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 397 /// A NULL pointer means that no register mask will be used, and call 402 // The default mask clobbers everything. All targets should override. 776 // iterator will visit a list of pairs (Idx, Mask) corresponding to the 779 // Each bit mask will have at least one set bit, and each set bit in Mask [all...] |
/external/llvm/lib/Analysis/ |
ConstantFolding.cpp | [all...] |