1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the X86 specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86SUBTARGET_H 15 #define X86SUBTARGET_H 16 17 #include "llvm/CallingConv.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Target/TargetSubtargetInfo.h" 20 #include <string> 21 22 #define GET_SUBTARGETINFO_HEADER 23 #include "X86GenSubtargetInfo.inc" 24 25 namespace llvm { 26 class GlobalValue; 27 class StringRef; 28 class TargetMachine; 29 30 /// PICStyles - The X86 backend supports a number of different styles of PIC. 31 /// 32 namespace PICStyles { 33 enum Style { 34 StubPIC, // Used on i386-darwin in -fPIC mode. 35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode. 36 GOT, // Used on many 32-bit unices in -fPIC mode. 37 RIPRel, // Used on X86-64 when not in -static mode. 38 None // Set when in -static mode (not PIC or DynamicNoPIC mode). 39 }; 40 } 41 42 class X86Subtarget : public X86GenSubtargetInfo { 43 protected: 44 enum X86SSEEnum { 45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 46 }; 47 48 enum X863DNowEnum { 49 NoThreeDNow, ThreeDNow, ThreeDNowA 50 }; 51 52 enum X86ProcFamilyEnum { 53 Others, IntelAtom 54 }; 55 56 /// X86ProcFamily - X86 processor family: Intel Atom, and others 57 X86ProcFamilyEnum X86ProcFamily; 58 59 /// PICStyle - Which PIC style to use 60 /// 61 PICStyles::Style PICStyle; 62 63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or 64 /// none supported. 65 X86SSEEnum X86SSELevel; 66 67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported. 68 /// 69 X863DNowEnum X863DNowLevel; 70 71 /// HasCMov - True if this processor has conditional move instructions 72 /// (generally pentium pro+). 73 bool HasCMov; 74 75 /// HasX86_64 - True if the processor supports X86-64 instructions. 76 /// 77 bool HasX86_64; 78 79 /// HasPOPCNT - True if the processor supports POPCNT. 80 bool HasPOPCNT; 81 82 /// HasSSE4A - True if the processor supports SSE4A instructions. 83 bool HasSSE4A; 84 85 /// HasAES - Target has AES instructions 86 bool HasAES; 87 88 /// HasPCLMUL - Target has carry-less multiplication 89 bool HasPCLMUL; 90 91 /// HasFMA - Target has 3-operand fused multiply-add 92 bool HasFMA; 93 94 /// HasFMA4 - Target has 4-operand fused multiply-add 95 bool HasFMA4; 96 97 /// HasXOP - Target has XOP instructions 98 bool HasXOP; 99 100 /// HasMOVBE - True if the processor has the MOVBE instruction. 101 bool HasMOVBE; 102 103 /// HasRDRAND - True if the processor has the RDRAND instruction. 104 bool HasRDRAND; 105 106 /// HasF16C - Processor has 16-bit floating point conversion instructions. 107 bool HasF16C; 108 109 /// HasFSGSBase - Processor has FS/GS base insturctions. 110 bool HasFSGSBase; 111 112 /// HasLZCNT - Processor has LZCNT instruction. 113 bool HasLZCNT; 114 115 /// HasBMI - Processor has BMI1 instructions. 116 bool HasBMI; 117 118 /// HasBMI2 - Processor has BMI2 instructions. 119 bool HasBMI2; 120 121 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. 122 bool IsBTMemSlow; 123 124 /// IsUAMemFast - True if unaligned memory access is fast. 125 bool IsUAMemFast; 126 127 /// HasVectorUAMem - True if SIMD operations can have unaligned memory 128 /// operands. This may require setting a feature bit in the processor. 129 bool HasVectorUAMem; 130 131 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction; 132 /// this is true for most x86-64 chips, but not the first AMD chips. 133 bool HasCmpxchg16b; 134 135 /// UseLeaForSP - True if the LEA instruction should be used for adjusting 136 /// the stack pointer. This is an optimization for Intel Atom processors. 137 bool UseLeaForSP; 138 139 /// HasSlowDivide - True if smaller divides are significantly faster than 140 /// full divides and should be used when possible. 141 bool HasSlowDivide; 142 143 /// PostRAScheduler - True if using post-register-allocation scheduler. 144 bool PostRAScheduler; 145 146 /// stackAlignment - The minimum alignment known to hold of the stack frame on 147 /// entry to the function and which must be maintained by every function. 148 unsigned stackAlignment; 149 150 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. 151 /// 152 unsigned MaxInlineSizeThreshold; 153 154 /// TargetTriple - What processor and OS we're targeting. 155 Triple TargetTriple; 156 157 /// Instruction itineraries for scheduling 158 InstrItineraryData InstrItins; 159 160 private: 161 /// In64BitMode - True if compiling for 64-bit, false for 32-bit. 162 bool In64BitMode; 163 164 public: 165 166 /// This constructor initializes the data members to match that 167 /// of the specified triple. 168 /// 169 X86Subtarget(const std::string &TT, const std::string &CPU, 170 const std::string &FS, 171 unsigned StackAlignOverride, bool is64Bit); 172 173 /// getStackAlignment - Returns the minimum alignment known to hold of the 174 /// stack frame on entry to the function and which must be maintained by every 175 /// function for this subtarget. 176 unsigned getStackAlignment() const { return stackAlignment; } 177 178 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 179 /// that still makes it profitable to inline the call. 180 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } 181 182 /// ParseSubtargetFeatures - Parses features string setting specified 183 /// subtarget options. Definition of function is auto generated by tblgen. 184 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 185 186 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID 187 /// instruction. 188 void AutoDetectSubtargetFeatures(); 189 190 bool is64Bit() const { return In64BitMode; } 191 192 PICStyles::Style getPICStyle() const { return PICStyle; } 193 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } 194 195 bool hasCMov() const { return HasCMov; } 196 bool hasMMX() const { return X86SSELevel >= MMX; } 197 bool hasSSE1() const { return X86SSELevel >= SSE1; } 198 bool hasSSE2() const { return X86SSELevel >= SSE2; } 199 bool hasSSE3() const { return X86SSELevel >= SSE3; } 200 bool hasSSSE3() const { return X86SSELevel >= SSSE3; } 201 bool hasSSE41() const { return X86SSELevel >= SSE41; } 202 bool hasSSE42() const { return X86SSELevel >= SSE42; } 203 bool hasAVX() const { return X86SSELevel >= AVX; } 204 bool hasAVX2() const { return X86SSELevel >= AVX2; } 205 bool hasNoAVX() const { return X86SSELevel < AVX; } 206 bool hasSSE4A() const { return HasSSE4A; } 207 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } 208 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } 209 bool hasPOPCNT() const { return HasPOPCNT; } 210 bool hasAES() const { return HasAES; } 211 bool hasPCLMUL() const { return HasPCLMUL; } 212 bool hasFMA() const { return HasFMA; } 213 // FIXME: Favor FMA when both are enabled. Is this the right thing to do? 214 bool hasFMA4() const { return HasFMA4 && !HasFMA; } 215 bool hasXOP() const { return HasXOP; } 216 bool hasMOVBE() const { return HasMOVBE; } 217 bool hasRDRAND() const { return HasRDRAND; } 218 bool hasF16C() const { return HasF16C; } 219 bool hasFSGSBase() const { return HasFSGSBase; } 220 bool hasLZCNT() const { return HasLZCNT; } 221 bool hasBMI() const { return HasBMI; } 222 bool hasBMI2() const { return HasBMI2; } 223 bool isBTMemSlow() const { return IsBTMemSlow; } 224 bool isUnalignedMemAccessFast() const { return IsUAMemFast; } 225 bool hasVectorUAMem() const { return HasVectorUAMem; } 226 bool hasCmpxchg16b() const { return HasCmpxchg16b; } 227 bool useLeaForSP() const { return UseLeaForSP; } 228 bool hasSlowDivide() const { return HasSlowDivide; } 229 230 bool isAtom() const { return X86ProcFamily == IntelAtom; } 231 232 const Triple &getTargetTriple() const { return TargetTriple; } 233 234 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 235 bool isTargetFreeBSD() const { 236 return TargetTriple.getOS() == Triple::FreeBSD; 237 } 238 bool isTargetSolaris() const { 239 return TargetTriple.getOS() == Triple::Solaris; 240 } 241 242 // ELF is a reasonably sane default and the only other X86 targets we 243 // support are Darwin and Windows. Just use "not those". 244 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 245 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; } 246 bool isTargetNaCl() const { 247 return TargetTriple.getOS() == Triple::NativeClient; 248 } 249 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } 250 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } 251 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; } 252 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; } 253 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; } 254 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } 255 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 256 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); } 257 258 bool isTargetWin64() const { 259 // FIXME: x86_64-cygwin has not been released yet. 260 return In64BitMode && TargetTriple.isOSWindows(); 261 } 262 263 bool isTargetWin32() const { 264 // FIXME: Cygwin is included for isTargetWin64 -- should it be included 265 // here too? 266 return !In64BitMode && (isTargetMingw() || isTargetWindows()); 267 } 268 269 bool isPICStyleSet() const { return PICStyle != PICStyles::None; } 270 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; } 271 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; } 272 273 bool isPICStyleStubPIC() const { 274 return PICStyle == PICStyles::StubPIC; 275 } 276 277 bool isPICStyleStubNoDynamic() const { 278 return PICStyle == PICStyles::StubDynamicNoPIC; 279 } 280 bool isPICStyleStubAny() const { 281 return PICStyle == PICStyles::StubDynamicNoPIC || 282 PICStyle == PICStyles::StubPIC; } 283 284 /// ClassifyGlobalReference - Classify a global variable reference for the 285 /// current subtarget according to how we should reference it in a non-pcrel 286 /// context. 287 unsigned char ClassifyGlobalReference(const GlobalValue *GV, 288 const TargetMachine &TM)const; 289 290 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the 291 /// current subtarget according to how we should reference it in a non-pcrel 292 /// context. 293 unsigned char ClassifyBlockAddressReference() const; 294 295 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls 296 /// to immediate address. 297 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const; 298 299 /// This function returns the name of a function which has an interface 300 /// like the non-standard bzero function, if such a function exists on 301 /// the current subtarget and it is considered prefereable over 302 /// memset with zero passed as the second argument. Otherwise it 303 /// returns null. 304 const char *getBZeroEntry() const; 305 306 /// getSpecialAddressLatency - For targets where it is beneficial to 307 /// backschedule instructions that compute addresses, return a value 308 /// indicating the number of scheduling cycles of backscheduling that 309 /// should be attempted. 310 unsigned getSpecialAddressLatency() const; 311 312 /// enablePostRAScheduler - run for Atom optimization. 313 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 314 TargetSubtargetInfo::AntiDepBreakMode& Mode, 315 RegClassVector& CriticalPathRCs) const; 316 317 bool postRAScheduler() const { return PostRAScheduler; } 318 319 /// getInstrItins = Return the instruction itineraries based on the 320 /// subtarget selection. 321 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 322 }; 323 324 } // End llvm namespace 325 326 #endif 327
