/external/llvm/lib/CodeGen/ |
DFAPacketizer.cpp | 109 MachineDominatorTree &MDT, bool IsPostRA); 116 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 118 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) { 129 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 133 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
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UnreachableBlockElim.cpp | 128 MachineDominatorTree *MDT = getAnalysisIfAvailable<MachineDominatorTree>(); 149 if (MDT && MDT->getNode(BB)) MDT->eraseNode(BB);
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LiveDebugVariables.cpp | 224 /// @param MDT Dominator tree. 228 LiveIntervals &LIS, MachineDominatorTree &MDT, 247 LiveIntervals &LIS, MachineDominatorTree &MDT, 286 MachineDominatorTree *MDT; 488 LiveIntervals &LIS, MachineDominatorTree &MDT, 537 MDT.getNode(MBB)->getChildren(); 623 MachineDominatorTree &MDT, 639 extendDef(Idx, LocNo, 0, 0, 0, LIS, MDT, UVS); 652 extendDef(Idx, LocNo, LI, VNI, &Kills, LIS, MDT, UVS); 663 extendDef(Idx, LocNo, LI, VNI, 0, LIS, MDT, UVS) [all...] |
PostRASchedulerList.cpp | 134 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 197 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, 201 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA), 258 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); 291 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
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SplitKit.h | 215 MachineDominatorTree &MDT;
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LiveRangeCalc.cpp | 23 MachineDominatorTree *MDT, 27 DomTree = MDT;
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MachineBasicBlock.cpp | 733 if (MachineDominatorTree *MDT = 736 MachineDomTreeNode *SucccDTNode = MDT->getNode(Succ); 744 if (!MDT->dominates(SucccDTNode, MDT->getNode(PredBB))) { 751 MachineDomTreeNode *NewDTNode = MDT->addNewBlock(NMBB, this); 757 MDT->changeImmediateDominator(SucccDTNode, NewDTNode); [all...] |
SplitKit.cpp | 328 MachineDominatorTree &mdt) 331 MDT(mdt), 348 LRCalc[0].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, 351 LRCalc[1].reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, 680 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def."); 684 MachineDomTreeNode *DefDomNode = MDT[DefMBB]; 719 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom(); 722 if (!IDom || !MDT.dominates(DefDomNode, IDom)) 782 MDT.findNearestCommonDominator(Dom.first, ValMBB) [all...] |
InlineSpiller.cpp | 59 MachineDominatorTree &MDT; 143 MDT(pass.getAnalysis<MachineDominatorTree>()), 440 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) { [all...] |
MachineScheduler.cpp | 58 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) { 183 MDT = &getAnalysis<MachineDominatorTree>(); 361 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS), [all...] |
ScheduleDAGInstrs.cpp | 44 const MachineDominatorTree &mdt, 47 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), 50 LoopRegs(MDT), FirstDbgValue(0) { [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineScheduler.h | 46 const MachineDominatorTree *MDT;
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ScheduleDAGInstrs.h | 39 const MachineDominatorTree &MDT; 46 LoopDependencies(const MachineDominatorTree &mdt) : MDT(mdt) {} 59 const MachineDomTreeNode *Node = MDT.getNode(Header); 177 const MachineDominatorTree &MDT; 250 const MachineDominatorTree &mdt,
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DFAPacketizer.h | 111 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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/external/v8/test/mjsunit/ |
date-parse.js | 185 // MDT = UT minus 6 hours. 187 'Sat, 01-Jan-2000 02:00:00 MDT', 188 'Sat, 01 Jan 2000 02:00:00 MDT', 189 'Saturday, 01-Jan-00 02:00:00 MDT',
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/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.h | 232 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
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HexagonVLIWPacketizer.cpp | 102 MachineDominatorTree &MDT); 158 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT) 159 : VLIWPacketizerList(MF, MLI, MDT, true){ 165 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); 168 HexagonPacketizerList Packetizer(Fn, MLI, MDT); [all...] |