| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.h | 29 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
33 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum
[all...] |
| ARMInstPrinter.cpp | 51 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
53 unsigned Opcode = MI->getOpcode();
57 switch (MI->getOperand(0).getImm()) {
65 printInstruction(MI, O);
69 printPredicateOperand(MI, 1, O);
79 const MCOperand &Dst = MI->getOperand(0);
80 const MCOperand &MO1 = MI->getOperand(1);
81 const MCOperand &MO2 = MI->getOperand(2);
82 const MCOperand &MO3 = MI->getOperand(3);
85 printSBitModifierOperand(MI, 6, O)
[all...] |
| /external/llvm/lib/Target/Hexagon/InstPrinter/ |
| HexagonInstPrinter.h | 28 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
29 void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot);
31 void printInstruction(const MCInst *MI, raw_ostream &O);
35 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
36 void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
37 void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
38 void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo,
40 void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
42 void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
44 void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O
[all...] |
| HexagonInstPrinter.cpp | 39 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
41 printInst((const HexagonMCInst*)(MI), O, Annot);
44 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,
50 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
52 assert(MI->isEndPacket() && "Loop end must also end the packet");
54 if (MI->isStartPacket()) {
61 Nop.setStartPacket (MI->isStartPacket());
66 if (MI->isEndPacket())
69 printInstruction(MI, O);
73 if (MI->isStartPacket()
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.h | 30 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
37 void printInstruction(const MCInst *MI, raw_ostream &OS);
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
41 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
42 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
45 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
46 printMemReference(MI, OpNo, O);
49 void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)
[all...] |
| X86IntelInstPrinter.h | 31 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
44 printMemReference(MI, OpNo, O);
47 void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
49 printMemReference(MI, OpNo, O)
[all...] |
| X86InstComments.cpp | 29 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
35 switch (MI->getOpcode()) {
37 Src1Name = getRegName(MI->getOperand(0).getReg());
38 Src2Name = getRegName(MI->getOperand(2).getReg());
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
42 DestName = getRegName(MI->getOperand(0).getReg());
43 Src1Name = getRegName(MI->getOperand(1).getReg());
44 Src2Name = getRegName(MI->getOperand(2).getReg());
45 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
49 Src2Name = getRegName(MI->getOperand(2).getReg())
[all...] |
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 54 virtual void Observe(MachineInstr *MI, unsigned Count,
62 void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) {
63 assert (MI->isDebugValue() && "MI is not DBG_VALUE!");
64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
65 MI->getOperand(0).setReg(NewReg);
|
| ExpandPostRAPseudos.cpp | 49 bool LowerSubregToReg(MachineInstr *MI);
50 bool LowerCopy(MachineInstr *MI);
52 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
54 void TransferImplicitDefs(MachineInstr *MI);
64 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
68 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
71 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
74 assert(MII != MI->getParent()->begin() &&
79 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
81 /// operands from MI to the replacement instruction
[all...] |
| TargetInstrInfoImpl.cpp | 61 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
63 const MCInstrDesc &MCID = MI->getDesc();
65 if (HasDef && !MI->getOperand(0).isReg())
69 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
72 Msg << "Don't know how to commute: " << *MI;
76 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
78 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
79 unsigned Reg1 = MI->getOperand(Idx1).getReg();
80 unsigned Reg2 = MI->getOperand(Idx2).getReg()
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 30 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
33 if (MI->getOpcode() == PPC::RLWINM) {
34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
46 printOperand(MI, 0, O);
48 printOperand(MI, 1, O);
56 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
[all...] |
| PPCInstPrinter.h | 36 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
39 void printInstruction(const MCInst *MI, raw_ostream &O);
43 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printPredicateOperand(const MCInst *MI, unsigned OpNo,
48 void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
49 void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
50 void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
51 void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
52 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
53 void printS16X4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 82 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
84 void emitInstruction(const MachineInstr &MI);
101 unsigned getMachineOpValue(const MachineInstr &MI,
104 unsigned getRelocation(const MachineInstr &MI,
107 unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
109 unsigned getBranchTargetOpValue(const MachineInstr &MI,
111 unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
112 unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
113 unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
115 int emitULW(const MachineInstr &MI);
[all...] |
| MipsAsmPrinter.h | 33 void EmitInstrWithMacroNoAT(const MachineInstr *MI);
52 void EmitInstruction(const MachineInstr *MI);
62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
68 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
69 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
70 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
71 void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
72 void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
75 virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.h | 39 virtual void EmitInstruction(const MachineInstr *MI);
43 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
44 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
47 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
55 void printInstruction(const MachineInstr *MI, raw_ostream &O);
57 // void printMachineInstruction(const MachineInstr *MI);
69 void printImmOperand(const MachineInstr *MI, unsigned OpNo,
71 int value = MI->getOperand(OpNo).getImm();
75 void printNegImmOperand(const MachineInstr *MI, unsigned OpNo,
77 int value = MI->getOperand(OpNo).getImm()
[all...] |
| HexagonSplitTFRCondSets.cpp | 83 MachineInstr *MI = MII;
85 switch(MI->getOpcode()) {
89 int DestReg = MI->getOperand(0).getReg();
90 int SrcReg1 = MI->getOperand(2).getReg();
91 int SrcReg2 = MI->getOperand(3).getReg();
93 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
94 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
98 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) {
106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
107 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1)
[all...] |
| HexagonMachineFunctionInfo.h | 45 void addAllocaAdjustInst(MachineInstr* MI) {
46 AllocaAdjustInsts.push_back(MI);
55 void setStartPacket(MachineInstr* MI) {
56 PacketInfo[MI] |= Hexagon::StartPacket;
58 void setEndPacket(MachineInstr* MI) {
59 PacketInfo[MI] |= Hexagon::EndPacket;
61 bool isStartPacket(const MachineInstr* MI) const {
62 return (PacketInfo.count(MI) &&
63 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
65 bool isEndPacket(const MachineInstr* MI) const
[all...] |
| /external/llvm/lib/Target/MBlaze/InstPrinter/ |
| MBlazeInstPrinter.cpp | 28 void MBlazeInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
30 printInstruction(MI, O);
34 void MBlazeInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
37 const MCOperand &Op = MI->getOperand(OpNo);
48 void MBlazeInstPrinter::printFSLImm(const MCInst *MI, int OpNo,
50 const MCOperand &MO = MI->getOperand(OpNo);
54 printOperand(MI, OpNo, O, NULL);
57 void MBlazeInstPrinter::printUnsignedImm(const MCInst *MI, int OpNo,
59 const MCOperand &MO = MI->getOperand(OpNo);
63 printOperand(MI, OpNo, O, NULL)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUAsmPrinter.cpp | 51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);
55 void EmitInstruction(const MachineInstr *MI) {
58 printInstruction(MI, OS);
63 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
64 const MachineOperand &MO = MI->getOperand(OpNo);
74 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
77 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
83 printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
85 unsigned int value = MI->getOperand(OpNo).getImm();
91 printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.h | 47 virtual void EmitInstruction(const MachineInstr *MI);
52 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O,
54 void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
57 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
60 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
64 void printMachineInstruction(const MachineInstr *MI);
65 void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O);
66 void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
68 void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
71 void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCodeEmitter.cpp | 53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
60 unsigned getMachineOpValue(const MachineInstr &MI,
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
67 unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
68 unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
69 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
114 const MachineInstr &MI = *I
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 39 * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
41 * virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
57 virtual bool isMoveInstr(const MachineInstr &MI,
60 bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
61 bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
62 bool isReadSpecialReg(MachineInstr &MI) const;
64 virtual bool CanTailMerge(const MachineInstr *MI) const ;
75 unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
76 return MI.getOperand(2).getImm();
|
| /external/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 40 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
41 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
43 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
45 virtual void EmitInstruction(const MachineInstr *MI) {
48 printInstruction(MI, OS);
51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
54 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
57 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
61 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
66 virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 38 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
40 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
42 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
44 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
46 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
48 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
50 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
55 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
60 uint64_t getBinaryCodeForInstr(const MCInst &MI,
62 void EncodeInstruction(const MCInst &MI, raw_ostream &OS
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
53 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
56 bool PrintAsmMemoryOperand(const MachineInstr *MI,
59 void EmitInstruction(const MachineInstr *MI);
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
66 const MachineOperand &MO = MI->getOperand(OpNum);
111 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum,
113 const MachineOperand &Base = MI->getOperand(OpNum);
114 const MachineOperand &Disp = MI->getOperand(OpNum+1)
[all...] |
