| /external/llvm/utils/TableGen/ |
| AsmWriterInst.h | 11 // the string into operands, which can be literal strings (the constant bits of
12 // the string), actual operands (i.e., operands from the MachineInstr), and
87 std::vector<AsmWriterOperand> Operands;
104 if (!Operands.empty() &&
105 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
106 Operands.back().Str.append(Str);
108 Operands.push_back(AsmWriterOperand(Str));
|
| FastISelEmitter.cpp | 72 /// types. It has utility methods for emitting text based on the operands.
116 SmallVector<OpKind, 3> Operands;
119 return Operands < O.Operands;
122 return Operands == O.Operands;
125 bool empty() const { return Operands.empty(); }
128 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
129 if (Operands[i].isImm() && Operands[i].getImmCode() != 0
[all...] |
| AsmWriterInst.cpp | 86 Operands.push_back(
118 Operands.push_back(
195 Operands.push_back(AsmWriterOperand("PrintSpecial",
201 unsigned OpNo = CGI.Operands.getOperandNamed(VarName);
202 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
205 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
212 Operands.push_back(AsmWriterOperand("return;",
221 if (Operands.size() != Other.Operands.size()) return ~1;
224 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
[all...] |
| PseudoLoweringEmitter.cpp | 88 // Normal operands should always have the same type, or we have a
92 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
96 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
100 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
102 OpsAdded += Insn.Operands[i].MINumOperands;
108 // Just add the operands recursively. This is almost certainly
145 if (Insn.Operands.size() != Dag->getNumArgs())
150 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
151 NumMIOperands += Insn.Operands[i].MINumOperands;
157 // If there are more operands that weren't in the DAG, they have t
[all...] |
| InstrInfoEmitter.cpp | 74 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
75 // Handle aggregate operands and normal operands the same way by expanding
76 // either case into a list of operands for this op.
80 // registers in their multi-operand operands. It may also be an anonymous
83 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
87 OperandList.push_back(Inst.Operands[i]);
89 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
90 OperandList.push_back(Inst.Operands[i]);
118 // Predicate operands. Check to see if the original unexpanded operan
[all...] |
| AsmWriterEmitter.cpp | 65 // Check to see if any other operands are identical in this list, and if so,
108 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
111 O << " " << FirstInst.Operands[i].getCode();
119 FirstInst.Operands[i]));
125 AWI.Operands[i]));
155 if (Inst->Operands.empty())
158 Command = " " + Inst->Operands[0].getCode() + "\n";
193 // If this instruction has no more operands, we isn't anything to merge
197 if (!FirstInst || FirstInst->Operands.size() == Op)
203 // Keep track of the maximum, number of operands or an
[all...] |
| CodeEmitterGen.cpp | 128 // operand number. Non-matching operands are assumed to be in
131 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
133 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
134 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
139 while (CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
144 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
145 std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
151 // sub-operands, if there are more than one, so only
216 // operands to the instruction.
|
| CodeGenInstruction.cpp | 89 // If we have MIOpInfo, then we have #operands equal to number of entries
291 : TheDef(R), Operands(R), InferredFrom(0) {
305 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable");
334 ParseConstraints(R->getValueAsString("Constraints"), Operands);
337 Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding"));
431 // For register operands, the source register class can be a subclass
472 // Handle "zero_reg" for optional def operands.
476 // Tied operands where the source is a sub-operand of a complex operand
477 // need to represent both operands in the alias destination instruction.
479 // the MC representation of things doesn't use tied operands at all
[all...] |
| /dalvik/vm/compiler/codegen/x86/libenc/ |
| encoder.inl | 62 inline static void add_r(EncoderBase::Operands & args, const R_Opnd & r, Opnd_Size sz, OpndExt ext = OpndExt_None) {
73 inline static void add_m(EncoderBase::Operands & args, const M_Opnd & m, Opnd_Size sz, OpndExt ext = OpndExt_None) {
80 inline static void add_rm(EncoderBase::Operands & args, const RM_Opnd & rm, Opnd_Size sz, OpndExt ext = OpndExt_None) {
84 inline static void add_xmm(EncoderBase::Operands & args, const XMM_Opnd & xmm, bool dbl) {
94 inline static void add_fp(EncoderBase::Operands & args, unsigned i, bool dbl) {
98 inline static void add_imm(EncoderBase::Operands & args, const Imm_Opnd & imm) {
111 EncoderBase::Operands args;
117 EncoderBase::Operands args;
128 EncoderBase::Operands args;
135 EncoderBase::Operands args
[all...] |
| enc_base.h | 63 class Operands;
70 * @param opnds - operands for the instruction
73 static char * encode(char * stream, Mnemonic mn, const Operands& opnds);
173 * @brief Description of operands' roles in instruction.
177 * @brief Total number of operands in the operation.
191 * A bit-packed info about operands' roles. Each operand's role is
207 * The order of operands is left-to-right, i.e. for MOV, it
217 * @brief Info about single opcode - its opcode bytes, operands,
218 * operands' roles.
236 * @brief Info about opcode's operands
[all...] |
| enc_wrapper.cpp | 45 inline void add_r(EncoderBase::Operands & args, int physicalReg, OpndSize sz, OpndExt ext = OpndExt_None) {
52 inline void add_m(EncoderBase::Operands & args, int baseReg, int disp, OpndSize sz, OpndExt ext = OpndExt_None) {
58 inline void add_m_scale(EncoderBase::Operands & args, int baseReg, int indexReg, int scale,
65 inline void add_m_disp_scale(EncoderBase::Operands & args, int baseReg, int disp, int indexReg, int scale,
73 inline void add_fp(EncoderBase::Operands & args, unsigned i, bool dbl) {
76 inline void add_imm(EncoderBase::Operands & args, OpndSize sz, int value, bool is_signed) {
113 //TODO: the order of operands
127 printOperand(decInst.operands[decInst.argc-1-k]);
131 void printOperands(EncoderBase::Operands& opnds) {
142 void printEncoderInst(Mnemonic m, EncoderBase::Operands& opnds)
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCTargetAsmParser.h | 63 /// \param Operands [out] - The list of parsed operands, this returns
67 SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
81 /// MatchInstruction - Recognize a series of operands of a parsed instruction
89 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
97 /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
105 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
115 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
| MCInst.h | 31 /// MCOperand - Instances of this class represent operands of the MCInst class.
153 SmallVector<MCOperand, 8> Operands;
163 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
164 MCOperand &getOperand(unsigned i) { return Operands[i]; }
165 unsigned getNumOperands() const { return Operands.size(); }
168 Operands.push_back(Op);
171 void clear() { Operands.clear(); }
172 size_t size() { return Operands.size(); }
175 iterator begin() { return Operands.begin(); }
176 iterator end() { return Operands.end();
[all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 37 MBlazeOperand *ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
41 MBlazeOperand* ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
48 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
60 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
62 return getMCInstOperandNumImpl(Kind, Inst, Operands, OperandNum,
71 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
192 assert(N == 1 && "Invalid number of operands!");
197 assert(N == 1 && "Invalid number of operands!");
202 assert(N == 1 && "Invalid number of operands!");
207 assert(N == 2 && "Invalid number of operands!");
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 45 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
51 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
54 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
63 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
71 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
159 assert(N == 1 && "Invalid number of operands!");
174 assert(N == 1 && "Invalid number of operands!");
180 assert(N == 2 && "Invalid number of operands!");
266 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
278 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 67 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
77 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
79 return getMCInstOperandNumImpl(Kind, Inst, Operands, OperandNum,
118 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
382 assert(N == 1 && "Invalid number of operands!");
387 assert(N == 1 && "Invalid number of operands!");
426 assert((N == 5) && "Invalid number of operands!");
435 assert((N == 1) && "Invalid number of operands!");
988 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
[all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| EDInst.cpp | 12 // individual tokens, and operands for a single instruction.
42 unsigned int numOperands = Operands.size();
45 delete Operands[index];
124 Operands.push_back(operand);
151 return Operands.size();
158 if (index >= Operands.size())
161 operand = Operands[index];
|
| EDInst.h | 12 // representation, individual tokens and operands for a single instruction.
59 /// string representation, as well as its operands and tokens
74 /// The order in which operands from the InstInfo's operand information appear
81 /// The instruction's operands
82 opvec_t Operands;
132 /// parseOperands - populates the Operands member of the instruction,
145 /// numOperands - returns the number of operands available to retrieve, or -1
|
| /external/llvm/lib/Analysis/ |
| ScalarEvolutionNormalization.cpp | 109 SmallVector<const SCEV *, 8> Operands;
111 // The addrec conceptually uses its operands at loop entry.
116 Operands.push_back(TransformSubExpr(*I, LUser, 0));
119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap);
160 SmallVector<const SCEV *, 8> Operands;
168 Operands.push_back(N);
173 case scAddExpr: return SE.getAddExpr(Operands);
174 case scMulExpr: return SE.getMulExpr(Operands);
175 case scSMaxExpr: return SE.getSMaxExpr(Operands);
176 case scUMaxExpr: return SE.getUMaxExpr(Operands);
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 227 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
257 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
263 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
267 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
269 return getMCInstOperandNumImpl(Kind, Inst, Operands, OperandNum, NumMCOperands);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | 216 // Register operands don't have target flags.
520 /// MCID NULL and no operands.
539 /// implicit operands. It reserves space for the number of operands specified by
547 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
562 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
578 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
594 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
607 Operands.reserve(MI.getNumOperands());
609 // Add operands
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 81 std::vector<MachineOperand> Operands; // the operands
98 /// MCID NULL and no operands.
106 /// implicit operands. It reserves space for the number of operands specified
116 /// implicit operands. It reserves space for number of operands specified by
260 /// Access to explicit operands of the instruction.
262 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
266 return Operands[i]
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ConstantFolding.h | 11 // operands are constants, for example "sub i32 1, 0" -> "1".
36 /// Note that this fails if not all of the operands are constant. Otherwise,
50 /// specified operands. If successful, the constant result is returned, if not,
61 /// instruction (icmp/fcmp) with the specified operands. If it fails, it
62 /// returns a constant expression of the specified operands.
70 /// instruction with the specified operands and indices. The constant result is
98 Constant *ConstantFoldCall(Function *F, ArrayRef<Constant *> Operands,
|
| /external/llvm/lib/Transforms/IPO/ |
| ArgumentPromotion.cpp | 21 // more than three operands to the function, because passing thousands of
22 // operands for a large array or structure is unprofitable! This limit can be
263 // This load is safe if any prefix of its operands is safe to load.
376 IndicesVector Operands;
380 Operands.clear();
386 Operands.push_back(0);
403 Operands.push_back(C->getSExtValue());
423 // is safe if Operands, or a prefix of Operands, is marked as safe.
424 if (!PrefixIn(Operands, SafeToUnconditionallyLoad)
[all...] |
| /external/llvm/test/MC/X86/ |
| x86_operands.s | 30 # Indirect Memory Operands
|
