| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
113 if (!isAllocated(Regs[i]))
138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
139 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
144 unsigned Reg = Regs[FirstUnalloc];
150 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs,
152 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 146 void setUsed(BitVector &Regs) {
147 RegsAvailable.reset(Regs);
149 void setUnused(BitVector &Regs) {
150 RegsAvailable |= Regs;
|
| CallingConvLower.h | 232 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const {
234 if (!isAllocated(Regs[i]))
259 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) {
260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
265 unsigned Reg = Regs[FirstUnalloc];
271 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs,
273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
278 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
|
| RegisterPressure.h | 176 void addLiveRegs(ArrayRef<unsigned> Regs);
271 void increasePhysRegPressure(ArrayRef<unsigned> Regs);
272 void decreasePhysRegPressure(ArrayRef<unsigned> Regs);
274 void increaseVirtRegPressure(ArrayRef<unsigned> Regs);
275 void decreaseVirtRegPressure(ArrayRef<unsigned> Regs);
|
| MachineRegisterInfo.h | 385 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
59 const std::vector<CodeGenRegister*> &Regs,
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
171 const CodeGenRegister::Set &Regs = RC.getMembers();
172 if (Regs.empty())
177 OS << " {" << (*Regs.begin())->getWeight(RegBank)
247 const std::vector<CodeGenRegister*> &Regs,
255 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
256 Record *Reg = Regs[i]->TheDef;
274 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace")
[all...] |
| CodeGenRegisters.cpp | 145 RegUnitIterator(const CodeGenRegister::Set &Regs):
146 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
330 // SR is composed of multiple sub-regs. Find their names in this register.
[all...] |
| CodeGenTarget.cpp | 202 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters();
203 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
204 if (Regs[i]->TheDef->getValueAsString("AsmName") == Name)
205 return Regs[i];
|
| CodeGenRegisters.h | 621 // Compute the set of registers completely covered by the registers in Regs.
622 // The returned BitVector will have a bit set for each register in Regs,
624 // registers in Regs.
628 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
|
| AsmMatcherEmitter.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterPressure.cpp | 86 void RegPressureTracker::increasePhysRegPressure(ArrayRef<unsigned> Regs) {
87 for (unsigned I = 0, E = Regs.size(); I != E; ++I)
89 TRI->getMinimalPhysRegClass(Regs[I]), TRI);
94 void RegPressureTracker::decreasePhysRegPressure(ArrayRef<unsigned> Regs) {
95 for (unsigned I = 0, E = Regs.size(); I != E; ++I)
96 decreaseSetPressure(CurrSetPressure, TRI->getMinimalPhysRegClass(Regs[I]),
102 void RegPressureTracker::increaseVirtRegPressure(ArrayRef<unsigned> Regs) {
103 for (unsigned I = 0, E = Regs.size(); I != E; ++I)
105 MRI->getRegClass(Regs[I]), TRI);
109 void RegPressureTracker::decreaseVirtRegPressure(ArrayRef<unsigned> Regs) {
[all...] |
| ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs;
586 for (SmallVector<LiveReg, 4>::iterator i = Regs.begin(), e = Regs.end();
590 Regs.insert(i, LR);
594 Regs.push_back(LR);
600 while (!Regs.empty()) {
602 dv = Regs.pop_back_val().Value;
609 DomainValue *Latest = Regs.pop_back_val().Value;
|
| AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
|
| AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs,
76 Regs.push_back(Reg);
157 // In a return block, examine the function live-out regs.
169 // In a non-return block, examine the live-in regs of all successors.
554 std::vector<unsigned> Regs;
555 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
556 assert(Regs.size() > 0 && "Empty register group!");
557 if (Regs.size() == 0)
567 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
568 unsigned Reg = Regs[i]
[all...] |
| LocalStackSlotAllocation.cpp | 197 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs,
203 unsigned e = Regs.size();
205 RegOffset = Regs[i];
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 588 SmallVector<std::pair<unsigned,bool>, 4> Regs;
620 Regs.push_back(std::make_pair(Reg, isKill));
623 if (Regs.empty())
625 if (Regs.size() > 1 || StrOpc== 0) {
629 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
630 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
631 } else if (Regs.size() == 1) {
634 .addReg(Regs[0].first, getKillRegState(Regs[0].second)
[all...] |
| ARMLoadStoreOptimizer.cpp | 97 ArrayRef<std::pair<unsigned, bool> > Regs,
279 /// registers in Regs as the register operands that would be loaded / stored.
287 ArrayRef<std::pair<unsigned, bool> > Regs,
290 unsigned NumRegs = Regs.size();
320 NewBase = Regs[NumRegs-1].first;
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
354 | getKillRegState(Regs[i].second));
393 SmallVector<std::pair<unsigned, bool>, 8> Regs;
400 Regs.push_back(std::make_pair(Reg, isKill));
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)
[all...] |
| Thumb2SizeReduction.cpp | 193 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
194 if (*Regs == ARM::CPSR)
604 // Early exit if the regs aren't all low regs.
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 803 SmallPtrSet<const SCEV *, 16> &Regs,
815 SmallPtrSet<const SCEV *, 16> &Regs,
819 SmallPtrSet<const SCEV *, 16> &Regs,
829 SmallPtrSet<const SCEV *, 16> &Regs,
851 if (!Regs.count(AR->getOperand(1))) {
852 RateRegister(AR->getOperand(1), Regs, L, SE, DT);
875 /// that refers to one of those regs an instant loser.
877 SmallPtrSet<const SCEV *, 16> &Regs,
885 if (Regs.insert(Reg)) {
886 RateRegister(Reg, Regs, L, SE, DT)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 575 /// Regs - This list holds the registers assigned to the values.
579 SmallVector<unsigned, 4> Regs;
583 RegsForValue(const SmallVector<unsigned, 4> ®s,
585 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
596 Regs.push_back(Reg + i);
616 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
