| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 45 MachineInstr *MI;
47 MachineInstrBuilder() : MI(0) {}
48 explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {}
52 operator MachineInstr*() const { return MI; }
53 MachineInstr *operator->() const { return MI; }
54 operator MachineBasicBlock::iterator() const { return MI; }
63 MI->addOperand(MachineOperand::CreateReg(RegNo,
79 MI->addOperand(MachineOperand::CreateImm(Val))
[all...] |
| DFAPacketizer.h | 76 bool canReserveResources(llvm::MachineInstr *MI);
80 void reserveResources(llvm::MachineInstr *MI);
106 // Generate MI -> SU map.
124 // addToPacket - Add MI to the current packet.
125 virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
126 MachineBasicBlock::iterator MII = MI;
127 CurrentPacketMIs.push_back(MI);
128 ResourceTracker->reserveResources(MI);
133 void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
146 // isSoloInstruction - return true if instruction MI can not be packetize
[all...] |
| /external/llvm/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 45 bool isDead(const MachineInstr *MI) const;
51 INITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination",
54 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
58 if (MI->isInlineAsm())
63 if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
67 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
68 const MachineOperand &MO = MI->getOperand(i);
128 MachineInstr *MI = &*MII;
131 if (isDead(MI)) {
[all...] |
| OptimizePHIs.cpp | 51 bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
53 bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
78 /// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands
83 bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI,
86 assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction");
87 unsigned DstReg = MI->getOperand(0).getReg();
90 if (!PHIsInCycle.insert(MI))
98 for (unsigned i = 1; i != MI->getNumOperands(); i += 2) {
99 unsigned SrcReg = MI->getOperand(i).getReg();
128 bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle)
[all...] |
| ProcessImplicitDefs.cpp | 34 void processImplicitDef(MachineInstr *MI);
35 bool canTurnIntoImplicitDef(MachineInstr *MI);
64 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
65 if (!MI->isCopyLike() &&
66 !MI->isInsertSubreg() &&
67 !MI->isRegSequence() &&
68 !MI->isPHI())
70 for (MIOperands MO(MI); MO.isValid(); ++MO)
76 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
77 DEBUG(dbgs() << "Processing " << *MI);
[all...] |
| MachineLICM.cpp | 153 MachineInstr *MI;
156 CandidateInfo(MachineInstr *mi, unsigned def, int fi)
157 : MI(mi), Def(def), FI(fi) {}
167 void HoistPostRA(MachineInstr *MI, unsigned Def);
171 void ProcessMI(MachineInstr *MI,
195 bool HasLoopPHIUse(const MachineInstr *MI) const;
200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
203 bool IsCheapInstruction(MachineInstr &MI) const;
212 /// effect of hoisting MI from the current block to the preheader
[all...] |
| MachineCSE.cpp | 84 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
88 bool hasLivePhysRegDefUses(const MachineInstr *MI,
92 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
96 bool isCSECandidate(MachineInstr *MI);
98 MachineInstr *CSMI, MachineInstr *MI);
117 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
120 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
121 MachineOperand &MO = MI->getOperand(i);
144 DEBUG(dbgs() << "*** to: " << *MI);
198 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
[all...] |
| DFAPacketizer.cpp | 91 bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
92 const llvm::MCInstrDesc &MID = MI->getDesc();
98 void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
99 const llvm::MCInstrDesc &MID = MI->getDesc();
148 MachineInstr *MI) {
151 finalizeBundle(*MBB, MIFirst, MI);
166 // Generate MI -> SU map.
175 MachineInstr *MI = BeginItr;
180 if (this->isSoloInstruction(MI)) {
181 endPacket(MBB, MI);
[all...] |
| LiveRangeEdit.cpp | 136 MachineBasicBlock::iterator MI,
142 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
144 return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
161 MachineInstr *MI = MO.getParent();
163 if (DefMI && DefMI != MI)
165 if (!MI->canFoldAsLoad())
167 DefMI = MI;
169 if (UseMI && UseMI != MI)
174 UseMI = MI;
221 MachineInstr *MI = Dead.pop_back_val()
[all...] |
| MachineSink.cpp | 82 bool isWorthBreakingCriticalEdge(MachineInstr *MI,
85 MachineBasicBlock *SplitCriticalEdge(MachineInstr *MI,
89 bool SinkInstruction(MachineInstr *MI, bool &SawStore);
93 MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB,
95 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
99 bool PerformTrivialForwardCoalescing(MachineInstr *MI,
124 bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI,
126 if (!MI->isCopy())
129 unsigned SrcReg = MI->getOperand(1).getReg();
130 unsigned DstReg = MI->getOperand(0).getReg()
[all...] |
| InlineSpiller.cpp | 171 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
174 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
178 MachineBasicBlock::iterator MI);
180 SlotIndex, MachineBasicBlock::iterator MI);
207 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
209 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
210 if (!MI->isFullCopy())
212 if (MI->getOperand(0).getReg() == Reg)
213 return MI->getOperand(1).getReg();
214 if (MI->getOperand(1).getReg() == Reg
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86IntelInstPrinter.cpp | 33 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
35 printInstruction(MI, OS);
42 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
45 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
47 switch (MI->getOperand(Op).getImm()) {
87 void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
89 const MCOperand &Op = MI->getOperand(OpNo);
114 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
116 const MCOperand &Op = MI->getOperand(OpNo);
127 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.h | 85 void printInstruction(const MCInst *MI, raw_ostream &O);
89 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
92 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
93 void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O);
94 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
95 void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
96 void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
|
| MipsInstPrinter.cpp | 70 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
72 switch (MI->getOpcode()) {
81 printInstruction(MI, O);
84 switch (MI->getOpcode()) {
148 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
150 const MCOperand &Op = MI->getOperand(OpNo);
165 void MipsInstPrinter::printUnsignedImm(const MCInst *MI, int opNum,
167 const MCOperand &MO = MI->getOperand(opNum);
171 printOperand(MI, opNum, O);
175 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 118 // feeder insn between it's definition, this MI and jump, jmpInst
207 MachineInstr *MI = II;
212 int64_t v = MI->getOperand(2).getImm();
213 if (MI->getOpcode() == Hexagon::CMPGEri ||
214 (MI->getOpcode() == Hexagon::CMPGEUri && v > 0))
218 ((MI->getOpcode() == Hexagon::CMPEQri ||
219 MI->getOpcode() == Hexagon::CMPGTri ||
220 MI->getOpcode() == Hexagon::CMPGEri) &&
226 cmpReg1 = MI->getOperand(1).getReg();
229 cmpOp2 = MI->getOperand(2).getReg()
[all...] |
| HexagonMCInst.h | 31 void setMI(const MachineInstr *MI) { MachineI = MI; }
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 62 MachineInstr &MI = *I;
63 DebugLoc dl = MI.getDebugLoc();
64 int Size = MI.getOperand(0).getImm();
65 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
78 MachineInstr &MI = *II;
79 DebugLoc dl = MI.getDebugLoc();
80 while (!MI.getOperand(i).isFI()) {
82 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
85 int FrameIndex = MI.getOperand(i).getIndex();
88 MachineFunction &MF = *MI.getParent()->getParent()
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 58 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
63 uint64_t getBinaryCodeForInstr(const MCInst &MI,
69 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
75 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
80 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
83 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
85 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
87 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
112 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
115 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 42 bool MoveCopyOutOfITBlock(MachineInstr *MI,
54 static void TrackDefUses(MachineInstr *MI,
61 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
62 MachineOperand &MO = MI->getOperand(i);
91 static bool isCopy(MachineInstr *MI) {
92 switch (MI->getOpcode()) {
104 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
108 if (!isCopy(MI))
113 assert(MI->getOperand(0).getSubReg() == 0 &&
114 MI->getOperand(1).getSubReg() == 0 &
[all...] |
| ARMBaseInstrInfo.h | 75 bool isPredicated(const MachineInstr *MI) const;
77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
84 bool PredicateInstruction(MachineInstr *MI,
91 virtual bool DefinesPredicate(MachineInstr *MI,
94 virtual bool isPredicable(MachineInstr *MI) const;
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 35 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
43 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
47 MachineBasicBlock::iterator MI, DebugLoc DL,
63 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
|
| Mips16InstrInfo.cpp | 41 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
52 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
98 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
99 MachineBasicBlock &MBB = *MI->getParent();
101 switch(MI->getDesc().getOpcode()) {
105 ExpandRetRA16(MBB, MI, Mips::JrRa16);
109 MBB.erase(MI);
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 46 uint64_t getBinaryCodeForInstr(const MCInst &MI) const;
50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
52 return getMachineOpValue(MI, MI.getOperand(OpIdx));
87 void EmitIMM(const MCInst &MI, unsigned &CurByte, raw_ostream &OS) const;
89 void EmitImmediate(const MCInst &MI, unsigned opNo, bool pcrel,
93 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
109 unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI,
135 EmitIMM(const MCInst &MI, unsigned &CurByte,raw_ostream &OS) const
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeAsmPrinter.cpp | 70 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
73 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
74 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
75 void printFSLImm(const MachineInstr *MI, int opNum, raw_ostream &O);
76 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
79 void EmitInstruction(const MachineInstr *MI);
189 void MBlazeAsmPrinter::EmitInstruction(const MachineInstr *MI) {
193 MCInstLowering.Lower(MI, TmpInst);
199 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
208 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O)
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 145 void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const {
147 assert(MI->isInlineAsm() && "printInlineAsm only works on inline asms");
149 unsigned NumOperands = MI->getNumOperands();
153 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
157 assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?");
160 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
185 for (unsigned i = MI->getNumOperands(); i != 0; --i) {
186 if (MI->getOperand(i-1).isMetadata() &&
187 (LocMD = MI->getOperand(i-1).getMetadata()) &
[all...] |
