1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the ARM VFP instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 18 SDTCisSameAs<1, 2>]>; 19 20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>; 21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; 22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; 23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; 24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 28 29 30 //===----------------------------------------------------------------------===// 31 // Operand Definitions. 32 // 33 34 // 8-bit floating-point immediate encodings. 35 def FPImmOperand : AsmOperandClass { 36 let Name = "FPImm"; 37 let ParserMethod = "parseFPImm"; 38 } 39 40 def vfp_f32imm : Operand<f32>, 41 PatLeaf<(f32 fpimm), [{ 42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 43 }], SDNodeXForm<fpimm, [{ 44 APFloat InVal = N->getValueAPF(); 45 uint32_t enc = ARM_AM::getFP32Imm(InVal); 46 return CurDAG->getTargetConstant(enc, MVT::i32); 47 }]>> { 48 let PrintMethod = "printFPImmOperand"; 49 let ParserMatchClass = FPImmOperand; 50 } 51 52 def vfp_f64imm : Operand<f64>, 53 PatLeaf<(f64 fpimm), [{ 54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 55 }], SDNodeXForm<fpimm, [{ 56 APFloat InVal = N->getValueAPF(); 57 uint32_t enc = ARM_AM::getFP64Imm(InVal); 58 return CurDAG->getTargetConstant(enc, MVT::i32); 59 }]>> { 60 let PrintMethod = "printFPImmOperand"; 61 let ParserMatchClass = FPImmOperand; 62 } 63 64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 65 return cast<LoadSDNode>(N)->getAlignment() >= 4; 66 }]>; 67 68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 69 (store node:$val, node:$ptr), [{ 70 return cast<StoreSDNode>(N)->getAlignment() >= 4; 71 }]>; 72 73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand 74 // (the number of fixed bits) differently than it appears in the assembly 75 // source. It's encoded as "Size - fbits" where Size is the size of the 76 // fixed-point representation (32 or 16) and fbits is the value appearing 77 // in the assembly source, an integer in [0,16] or (0,32], depending on size. 78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 79 def fbits32 : Operand<i32> { 80 let PrintMethod = "printFBits32"; 81 let ParserMatchClass = fbits32_asm_operand; 82 } 83 84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 85 def fbits16 : Operand<i32> { 86 let PrintMethod = "printFBits16"; 87 let ParserMatchClass = fbits16_asm_operand; 88 } 89 90 //===----------------------------------------------------------------------===// 91 // Load / store Instructions. 92 // 93 94 let canFoldAsLoad = 1, isReMaterializable = 1 in { 95 96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 97 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>; 99 100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 101 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 102 [(set SPR:$Sd, (load addrmode5:$addr))]> { 103 // Some single precision VFP instructions may be executed on both NEON and VFP 104 // pipelines. 105 let D = VFPNeonDomain; 106 } 107 108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 109 110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 111 IIC_fpStore64, "vstr", "\t$Dd, $addr", 112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>; 113 114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 115 IIC_fpStore32, "vstr", "\t$Sd, $addr", 116 [(store SPR:$Sd, addrmode5:$addr)]> { 117 // Some single precision VFP instructions may be executed on both NEON and VFP 118 // pipelines. 119 let D = VFPNeonDomain; 120 } 121 122 //===----------------------------------------------------------------------===// 123 // Load / store multiple Instructions. 124 // 125 126 multiclass vfp_ldst_mult<string asm, bit L_bit, 127 InstrItinClass itin, InstrItinClass itin_upd> { 128 // Double Precision 129 def DIA : 130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 131 IndexModeNone, itin, 132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 133 let Inst{24-23} = 0b01; // Increment After 134 let Inst{21} = 0; // No writeback 135 let Inst{20} = L_bit; 136 } 137 def DIA_UPD : 138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 139 variable_ops), 140 IndexModeUpd, itin_upd, 141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 142 let Inst{24-23} = 0b01; // Increment After 143 let Inst{21} = 1; // Writeback 144 let Inst{20} = L_bit; 145 } 146 def DDB_UPD : 147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 148 variable_ops), 149 IndexModeUpd, itin_upd, 150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 151 let Inst{24-23} = 0b10; // Decrement Before 152 let Inst{21} = 1; // Writeback 153 let Inst{20} = L_bit; 154 } 155 156 // Single Precision 157 def SIA : 158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 159 IndexModeNone, itin, 160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 161 let Inst{24-23} = 0b01; // Increment After 162 let Inst{21} = 0; // No writeback 163 let Inst{20} = L_bit; 164 165 // Some single precision VFP instructions may be executed on both NEON and 166 // VFP pipelines. 167 let D = VFPNeonDomain; 168 } 169 def SIA_UPD : 170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 171 variable_ops), 172 IndexModeUpd, itin_upd, 173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 174 let Inst{24-23} = 0b01; // Increment After 175 let Inst{21} = 1; // Writeback 176 let Inst{20} = L_bit; 177 178 // Some single precision VFP instructions may be executed on both NEON and 179 // VFP pipelines. 180 let D = VFPNeonDomain; 181 } 182 def SDB_UPD : 183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 184 variable_ops), 185 IndexModeUpd, itin_upd, 186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 187 let Inst{24-23} = 0b10; // Decrement Before 188 let Inst{21} = 1; // Writeback 189 let Inst{20} = L_bit; 190 191 // Some single precision VFP instructions may be executed on both NEON and 192 // VFP pipelines. 193 let D = VFPNeonDomain; 194 } 195 } 196 197 let neverHasSideEffects = 1 in { 198 199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 201 202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>; 204 205 } // neverHasSideEffects 206 207 def : MnemonicAlias<"vldm", "vldmia">; 208 def : MnemonicAlias<"vstm", "vstmia">; 209 210 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>, 211 Requires<[HasVFP2]>; 212 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>, 213 Requires<[HasVFP2]>; 214 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>, 215 Requires<[HasVFP2]>; 216 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>, 217 Requires<[HasVFP2]>; 218 defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 219 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 220 defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 221 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 222 defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 223 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 224 defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 225 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 226 227 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores 228 229 //===----------------------------------------------------------------------===// 230 // FP Binary Operations. 231 // 232 233 let TwoOperandAliasConstraint = "$Dn = $Dd" in 234 def VADDD : ADbI<0b11100, 0b11, 0, 0, 235 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 236 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 237 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; 238 239 let TwoOperandAliasConstraint = "$Sn = $Sd" in 240 def VADDS : ASbIn<0b11100, 0b11, 0, 0, 241 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 242 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 243 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { 244 // Some single precision VFP instructions may be executed on both NEON and 245 // VFP pipelines on A8. 246 let D = VFPNeonA8Domain; 247 } 248 249 let TwoOperandAliasConstraint = "$Dn = $Dd" in 250 def VSUBD : ADbI<0b11100, 0b11, 1, 0, 251 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 252 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 253 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; 254 255 let TwoOperandAliasConstraint = "$Sn = $Sd" in 256 def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 257 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 258 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 259 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> { 260 // Some single precision VFP instructions may be executed on both NEON and 261 // VFP pipelines on A8. 262 let D = VFPNeonA8Domain; 263 } 264 265 let TwoOperandAliasConstraint = "$Dn = $Dd" in 266 def VDIVD : ADbI<0b11101, 0b00, 0, 0, 267 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 268 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 269 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; 270 271 let TwoOperandAliasConstraint = "$Sn = $Sd" in 272 def VDIVS : ASbI<0b11101, 0b00, 0, 0, 273 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 274 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 275 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; 276 277 let TwoOperandAliasConstraint = "$Dn = $Dd" in 278 def VMULD : ADbI<0b11100, 0b10, 0, 0, 279 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 280 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 281 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; 282 283 let TwoOperandAliasConstraint = "$Sn = $Sd" in 284 def VMULS : ASbIn<0b11100, 0b10, 0, 0, 285 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 286 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 287 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> { 288 // Some single precision VFP instructions may be executed on both NEON and 289 // VFP pipelines on A8. 290 let D = VFPNeonA8Domain; 291 } 292 293 def VNMULD : ADbI<0b11100, 0b10, 1, 0, 294 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 295 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 296 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; 297 298 def VNMULS : ASbI<0b11100, 0b10, 1, 0, 299 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 300 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 301 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> { 302 // Some single precision VFP instructions may be executed on both NEON and 303 // VFP pipelines on A8. 304 let D = VFPNeonA8Domain; 305 } 306 307 // Match reassociated forms only if not sign dependent rounding. 308 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 309 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 310 def : Pat<(fmul (fneg SPR:$a), SPR:$b), 311 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 312 313 // These are encoded as unary instructions. 314 let Defs = [FPSCR_NZCV] in { 315 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 316 (outs), (ins DPR:$Dd, DPR:$Dm), 317 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 318 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 319 320 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 321 (outs), (ins SPR:$Sd, SPR:$Sm), 322 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 323 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 324 // Some single precision VFP instructions may be executed on both NEON and 325 // VFP pipelines on A8. 326 let D = VFPNeonA8Domain; 327 } 328 329 // FIXME: Verify encoding after integrated assembler is working. 330 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 331 (outs), (ins DPR:$Dd, DPR:$Dm), 332 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 333 [/* For disassembly only; pattern left blank */]>; 334 335 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 336 (outs), (ins SPR:$Sd, SPR:$Sm), 337 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 338 [/* For disassembly only; pattern left blank */]> { 339 // Some single precision VFP instructions may be executed on both NEON and 340 // VFP pipelines on A8. 341 let D = VFPNeonA8Domain; 342 } 343 } // Defs = [FPSCR_NZCV] 344 345 //===----------------------------------------------------------------------===// 346 // FP Unary Operations. 347 // 348 349 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 350 (outs DPR:$Dd), (ins DPR:$Dm), 351 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 352 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 353 354 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 355 (outs SPR:$Sd), (ins SPR:$Sm), 356 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 357 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 358 // Some single precision VFP instructions may be executed on both NEON and 359 // VFP pipelines on A8. 360 let D = VFPNeonA8Domain; 361 } 362 363 let Defs = [FPSCR_NZCV] in { 364 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 365 (outs), (ins DPR:$Dd), 366 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 367 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 368 let Inst{3-0} = 0b0000; 369 let Inst{5} = 0; 370 } 371 372 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 373 (outs), (ins SPR:$Sd), 374 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 375 [(arm_cmpfp0 SPR:$Sd)]> { 376 let Inst{3-0} = 0b0000; 377 let Inst{5} = 0; 378 379 // Some single precision VFP instructions may be executed on both NEON and 380 // VFP pipelines on A8. 381 let D = VFPNeonA8Domain; 382 } 383 384 // FIXME: Verify encoding after integrated assembler is working. 385 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 386 (outs), (ins DPR:$Dd), 387 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 388 [/* For disassembly only; pattern left blank */]> { 389 let Inst{3-0} = 0b0000; 390 let Inst{5} = 0; 391 } 392 393 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 394 (outs), (ins SPR:$Sd), 395 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 396 [/* For disassembly only; pattern left blank */]> { 397 let Inst{3-0} = 0b0000; 398 let Inst{5} = 0; 399 400 // Some single precision VFP instructions may be executed on both NEON and 401 // VFP pipelines on A8. 402 let D = VFPNeonA8Domain; 403 } 404 } // Defs = [FPSCR_NZCV] 405 406 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 407 (outs DPR:$Dd), (ins SPR:$Sm), 408 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 409 [(set DPR:$Dd, (fextend SPR:$Sm))]> { 410 // Instruction operands. 411 bits<5> Dd; 412 bits<5> Sm; 413 414 // Encode instruction operands. 415 let Inst{3-0} = Sm{4-1}; 416 let Inst{5} = Sm{0}; 417 let Inst{15-12} = Dd{3-0}; 418 let Inst{22} = Dd{4}; 419 } 420 421 // Special case encoding: bits 11-8 is 0b1011. 422 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 423 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 424 [(set SPR:$Sd, (fround DPR:$Dm))]> { 425 // Instruction operands. 426 bits<5> Sd; 427 bits<5> Dm; 428 429 // Encode instruction operands. 430 let Inst{3-0} = Dm{3-0}; 431 let Inst{5} = Dm{4}; 432 let Inst{15-12} = Sd{4-1}; 433 let Inst{22} = Sd{0}; 434 435 let Inst{27-23} = 0b11101; 436 let Inst{21-16} = 0b110111; 437 let Inst{11-8} = 0b1011; 438 let Inst{7-6} = 0b11; 439 let Inst{4} = 0; 440 } 441 442 // Between half-precision and single-precision. For disassembly only. 443 444 // FIXME: Verify encoding after integrated assembler is working. 445 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 446 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 447 [/* For disassembly only; pattern left blank */]>; 448 449 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 450 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 451 [/* For disassembly only; pattern left blank */]>; 452 453 def : Pat<(f32_to_f16 SPR:$a), 454 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 455 456 def : Pat<(f16_to_f32 GPR:$a), 457 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 458 459 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 460 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 461 [/* For disassembly only; pattern left blank */]>; 462 463 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 464 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 465 [/* For disassembly only; pattern left blank */]>; 466 467 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 468 (outs DPR:$Dd), (ins DPR:$Dm), 469 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 470 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 471 472 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 473 (outs SPR:$Sd), (ins SPR:$Sm), 474 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 475 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 476 // Some single precision VFP instructions may be executed on both NEON and 477 // VFP pipelines on A8. 478 let D = VFPNeonA8Domain; 479 } 480 481 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 482 (outs DPR:$Dd), (ins DPR:$Dm), 483 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 484 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; 485 486 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 487 (outs SPR:$Sd), (ins SPR:$Sm), 488 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 489 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; 490 491 let neverHasSideEffects = 1 in { 492 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 493 (outs DPR:$Dd), (ins DPR:$Dm), 494 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; 495 496 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 497 (outs SPR:$Sd), (ins SPR:$Sm), 498 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; 499 } // neverHasSideEffects 500 501 //===----------------------------------------------------------------------===// 502 // FP <-> GPR Copies. Int <-> FP Conversions. 503 // 504 505 def VMOVRS : AVConv2I<0b11100001, 0b1010, 506 (outs GPR:$Rt), (ins SPR:$Sn), 507 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 508 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { 509 // Instruction operands. 510 bits<4> Rt; 511 bits<5> Sn; 512 513 // Encode instruction operands. 514 let Inst{19-16} = Sn{4-1}; 515 let Inst{7} = Sn{0}; 516 let Inst{15-12} = Rt; 517 518 let Inst{6-5} = 0b00; 519 let Inst{3-0} = 0b0000; 520 521 // Some single precision VFP instructions may be executed on both NEON and VFP 522 // pipelines. 523 let D = VFPNeonDomain; 524 } 525 526 def VMOVSR : AVConv4I<0b11100000, 0b1010, 527 (outs SPR:$Sn), (ins GPR:$Rt), 528 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 529 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> { 530 // Instruction operands. 531 bits<5> Sn; 532 bits<4> Rt; 533 534 // Encode instruction operands. 535 let Inst{19-16} = Sn{4-1}; 536 let Inst{7} = Sn{0}; 537 let Inst{15-12} = Rt; 538 539 let Inst{6-5} = 0b00; 540 let Inst{3-0} = 0b0000; 541 542 // Some single precision VFP instructions may be executed on both NEON and VFP 543 // pipelines. 544 let D = VFPNeonDomain; 545 } 546 547 let neverHasSideEffects = 1 in { 548 def VMOVRRD : AVConv3I<0b11000101, 0b1011, 549 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 550 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 551 [/* FIXME: Can't write pattern for multiple result instr*/]> { 552 // Instruction operands. 553 bits<5> Dm; 554 bits<4> Rt; 555 bits<4> Rt2; 556 557 // Encode instruction operands. 558 let Inst{3-0} = Dm{3-0}; 559 let Inst{5} = Dm{4}; 560 let Inst{15-12} = Rt; 561 let Inst{19-16} = Rt2; 562 563 let Inst{7-6} = 0b00; 564 565 // Some single precision VFP instructions may be executed on both NEON and VFP 566 // pipelines. 567 let D = VFPNeonDomain; 568 } 569 570 def VMOVRRS : AVConv3I<0b11000101, 0b1010, 571 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 572 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 573 [/* For disassembly only; pattern left blank */]> { 574 bits<5> src1; 575 bits<4> Rt; 576 bits<4> Rt2; 577 578 // Encode instruction operands. 579 let Inst{3-0} = src1{4-1}; 580 let Inst{5} = src1{0}; 581 let Inst{15-12} = Rt; 582 let Inst{19-16} = Rt2; 583 584 let Inst{7-6} = 0b00; 585 586 // Some single precision VFP instructions may be executed on both NEON and VFP 587 // pipelines. 588 let D = VFPNeonDomain; 589 let DecoderMethod = "DecodeVMOVRRS"; 590 } 591 } // neverHasSideEffects 592 593 // FMDHR: GPR -> SPR 594 // FMDLR: GPR -> SPR 595 596 def VMOVDRR : AVConv5I<0b11000100, 0b1011, 597 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 598 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 599 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> { 600 // Instruction operands. 601 bits<5> Dm; 602 bits<4> Rt; 603 bits<4> Rt2; 604 605 // Encode instruction operands. 606 let Inst{3-0} = Dm{3-0}; 607 let Inst{5} = Dm{4}; 608 let Inst{15-12} = Rt; 609 let Inst{19-16} = Rt2; 610 611 let Inst{7-6} = 0b00; 612 613 // Some single precision VFP instructions may be executed on both NEON and VFP 614 // pipelines. 615 let D = VFPNeonDomain; 616 } 617 618 let neverHasSideEffects = 1 in 619 def VMOVSRR : AVConv5I<0b11000100, 0b1010, 620 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 621 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 622 [/* For disassembly only; pattern left blank */]> { 623 // Instruction operands. 624 bits<5> dst1; 625 bits<4> src1; 626 bits<4> src2; 627 628 // Encode instruction operands. 629 let Inst{3-0} = dst1{4-1}; 630 let Inst{5} = dst1{0}; 631 let Inst{15-12} = src1; 632 let Inst{19-16} = src2; 633 634 let Inst{7-6} = 0b00; 635 636 // Some single precision VFP instructions may be executed on both NEON and VFP 637 // pipelines. 638 let D = VFPNeonDomain; 639 640 let DecoderMethod = "DecodeVMOVSRR"; 641 } 642 643 // FMRDH: SPR -> GPR 644 // FMRDL: SPR -> GPR 645 // FMRRS: SPR -> GPR 646 // FMRX: SPR system reg -> GPR 647 // FMSRR: GPR -> SPR 648 // FMXR: GPR -> VFP system reg 649 650 651 // Int -> FP: 652 653 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 654 bits<4> opcod4, dag oops, dag iops, 655 InstrItinClass itin, string opc, string asm, 656 list<dag> pattern> 657 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 658 pattern> { 659 // Instruction operands. 660 bits<5> Dd; 661 bits<5> Sm; 662 663 // Encode instruction operands. 664 let Inst{3-0} = Sm{4-1}; 665 let Inst{5} = Sm{0}; 666 let Inst{15-12} = Dd{3-0}; 667 let Inst{22} = Dd{4}; 668 } 669 670 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 671 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 672 string opc, string asm, list<dag> pattern> 673 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 674 pattern> { 675 // Instruction operands. 676 bits<5> Sd; 677 bits<5> Sm; 678 679 // Encode instruction operands. 680 let Inst{3-0} = Sm{4-1}; 681 let Inst{5} = Sm{0}; 682 let Inst{15-12} = Sd{4-1}; 683 let Inst{22} = Sd{0}; 684 } 685 686 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 687 (outs DPR:$Dd), (ins SPR:$Sm), 688 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 689 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> { 690 let Inst{7} = 1; // s32 691 } 692 693 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 694 (outs SPR:$Sd),(ins SPR:$Sm), 695 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 696 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> { 697 let Inst{7} = 1; // s32 698 699 // Some single precision VFP instructions may be executed on both NEON and 700 // VFP pipelines on A8. 701 let D = VFPNeonA8Domain; 702 } 703 704 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 705 (outs DPR:$Dd), (ins SPR:$Sm), 706 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 707 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> { 708 let Inst{7} = 0; // u32 709 } 710 711 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 712 (outs SPR:$Sd), (ins SPR:$Sm), 713 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 714 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> { 715 let Inst{7} = 0; // u32 716 717 // Some single precision VFP instructions may be executed on both NEON and 718 // VFP pipelines on A8. 719 let D = VFPNeonA8Domain; 720 } 721 722 // FP -> Int: 723 724 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 725 bits<4> opcod4, dag oops, dag iops, 726 InstrItinClass itin, string opc, string asm, 727 list<dag> pattern> 728 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 729 pattern> { 730 // Instruction operands. 731 bits<5> Sd; 732 bits<5> Dm; 733 734 // Encode instruction operands. 735 let Inst{3-0} = Dm{3-0}; 736 let Inst{5} = Dm{4}; 737 let Inst{15-12} = Sd{4-1}; 738 let Inst{22} = Sd{0}; 739 } 740 741 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 742 bits<4> opcod4, dag oops, dag iops, 743 InstrItinClass itin, string opc, string asm, 744 list<dag> pattern> 745 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 746 pattern> { 747 // Instruction operands. 748 bits<5> Sd; 749 bits<5> Sm; 750 751 // Encode instruction operands. 752 let Inst{3-0} = Sm{4-1}; 753 let Inst{5} = Sm{0}; 754 let Inst{15-12} = Sd{4-1}; 755 let Inst{22} = Sd{0}; 756 } 757 758 // Always set Z bit in the instruction, i.e. "round towards zero" variants. 759 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 760 (outs SPR:$Sd), (ins DPR:$Dm), 761 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 762 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> { 763 let Inst{7} = 1; // Z bit 764 } 765 766 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 767 (outs SPR:$Sd), (ins SPR:$Sm), 768 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 769 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> { 770 let Inst{7} = 1; // Z bit 771 772 // Some single precision VFP instructions may be executed on both NEON and 773 // VFP pipelines on A8. 774 let D = VFPNeonA8Domain; 775 } 776 777 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 778 (outs SPR:$Sd), (ins DPR:$Dm), 779 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 780 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> { 781 let Inst{7} = 1; // Z bit 782 } 783 784 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 785 (outs SPR:$Sd), (ins SPR:$Sm), 786 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 787 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> { 788 let Inst{7} = 1; // Z bit 789 790 // Some single precision VFP instructions may be executed on both NEON and 791 // VFP pipelines on A8. 792 let D = VFPNeonA8Domain; 793 } 794 795 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 796 let Uses = [FPSCR] in { 797 // FIXME: Verify encoding after integrated assembler is working. 798 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 799 (outs SPR:$Sd), (ins DPR:$Dm), 800 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 801 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{ 802 let Inst{7} = 0; // Z bit 803 } 804 805 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 806 (outs SPR:$Sd), (ins SPR:$Sm), 807 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 808 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> { 809 let Inst{7} = 0; // Z bit 810 } 811 812 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 813 (outs SPR:$Sd), (ins DPR:$Dm), 814 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 815 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{ 816 let Inst{7} = 0; // Z bit 817 } 818 819 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 820 (outs SPR:$Sd), (ins SPR:$Sm), 821 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 822 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> { 823 let Inst{7} = 0; // Z bit 824 } 825 } 826 827 // Convert between floating-point and fixed-point 828 // Data type for fixed-point naming convention: 829 // S16 (U=0, sx=0) -> SH 830 // U16 (U=1, sx=0) -> UH 831 // S32 (U=0, sx=1) -> SL 832 // U32 (U=1, sx=1) -> UL 833 834 let Constraints = "$a = $dst" in { 835 836 // FP to Fixed-Point: 837 838 // Single Precision register 839 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 840 bit op5, dag oops, dag iops, InstrItinClass itin, 841 string opc, string asm, list<dag> pattern> 842 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 843 bits<5> dst; 844 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 845 let Inst{22} = dst{0}; 846 let Inst{15-12} = dst{4-1}; 847 } 848 849 // Double Precision register 850 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 851 bit op5, dag oops, dag iops, InstrItinClass itin, 852 string opc, string asm, list<dag> pattern> 853 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 854 bits<5> dst; 855 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 856 let Inst{22} = dst{4}; 857 let Inst{15-12} = dst{3-0}; 858 } 859 860 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 861 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 862 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> { 863 // Some single precision VFP instructions may be executed on both NEON and 864 // VFP pipelines on A8. 865 let D = VFPNeonA8Domain; 866 } 867 868 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 869 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 870 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> { 871 // Some single precision VFP instructions may be executed on both NEON and 872 // VFP pipelines on A8. 873 let D = VFPNeonA8Domain; 874 } 875 876 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 877 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 878 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> { 879 // Some single precision VFP instructions may be executed on both NEON and 880 // VFP pipelines on A8. 881 let D = VFPNeonA8Domain; 882 } 883 884 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 885 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 886 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> { 887 // Some single precision VFP instructions may be executed on both NEON and 888 // VFP pipelines on A8. 889 let D = VFPNeonA8Domain; 890 } 891 892 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 893 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 894 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>; 895 896 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 897 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 898 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>; 899 900 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 901 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 902 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>; 903 904 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 905 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 906 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>; 907 908 // Fixed-Point to FP: 909 910 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 911 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 912 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> { 913 // Some single precision VFP instructions may be executed on both NEON and 914 // VFP pipelines on A8. 915 let D = VFPNeonA8Domain; 916 } 917 918 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 919 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 920 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> { 921 // Some single precision VFP instructions may be executed on both NEON and 922 // VFP pipelines on A8. 923 let D = VFPNeonA8Domain; 924 } 925 926 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 927 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 928 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> { 929 // Some single precision VFP instructions may be executed on both NEON and 930 // VFP pipelines on A8. 931 let D = VFPNeonA8Domain; 932 } 933 934 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 935 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 936 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> { 937 // Some single precision VFP instructions may be executed on both NEON and 938 // VFP pipelines on A8. 939 let D = VFPNeonA8Domain; 940 } 941 942 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 943 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 944 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>; 945 946 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 947 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 948 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>; 949 950 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 951 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 952 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>; 953 954 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 955 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 956 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>; 957 958 } // End of 'let Constraints = "$a = $dst" in' 959 960 //===----------------------------------------------------------------------===// 961 // FP Multiply-Accumulate Operations. 962 // 963 964 def VMLAD : ADbI<0b11100, 0b00, 0, 0, 965 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 966 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 967 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 968 (f64 DPR:$Ddin)))]>, 969 RegConstraint<"$Ddin = $Dd">, 970 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 971 972 def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 973 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 974 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 975 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 976 SPR:$Sdin))]>, 977 RegConstraint<"$Sdin = $Sd">, 978 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 979 // Some single precision VFP instructions may be executed on both NEON and 980 // VFP pipelines on A8. 981 let D = VFPNeonA8Domain; 982 } 983 984 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 985 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 986 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 987 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 988 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 989 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>; 990 991 def VMLSD : ADbI<0b11100, 0b00, 1, 0, 992 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 993 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 994 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 995 (f64 DPR:$Ddin)))]>, 996 RegConstraint<"$Ddin = $Dd">, 997 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 998 999 def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 1000 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1001 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 1002 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1003 SPR:$Sdin))]>, 1004 RegConstraint<"$Sdin = $Sd">, 1005 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1006 // Some single precision VFP instructions may be executed on both NEON and 1007 // VFP pipelines on A8. 1008 let D = VFPNeonA8Domain; 1009 } 1010 1011 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1012 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1013 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1014 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1015 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1016 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1017 1018 def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 1019 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1020 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 1021 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1022 (f64 DPR:$Ddin)))]>, 1023 RegConstraint<"$Ddin = $Dd">, 1024 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1025 1026 def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 1027 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1028 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 1029 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1030 SPR:$Sdin))]>, 1031 RegConstraint<"$Sdin = $Sd">, 1032 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1033 // Some single precision VFP instructions may be executed on both NEON and 1034 // VFP pipelines on A8. 1035 let D = VFPNeonA8Domain; 1036 } 1037 1038 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1039 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1040 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1041 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1042 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1043 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1044 1045 def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 1046 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1047 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 1048 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1049 (f64 DPR:$Ddin)))]>, 1050 RegConstraint<"$Ddin = $Dd">, 1051 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1052 1053 def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 1054 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1055 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 1056 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1057 RegConstraint<"$Sdin = $Sd">, 1058 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1059 // Some single precision VFP instructions may be executed on both NEON and 1060 // VFP pipelines on A8. 1061 let D = VFPNeonA8Domain; 1062 } 1063 1064 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1065 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1066 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1067 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1068 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1069 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1070 1071 //===----------------------------------------------------------------------===// 1072 // Fused FP Multiply-Accumulate Operations. 1073 // 1074 def VFMAD : ADbI<0b11101, 0b10, 0, 0, 1075 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1076 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 1077 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1078 (f64 DPR:$Ddin)))]>, 1079 RegConstraint<"$Ddin = $Dd">, 1080 Requires<[HasVFP4,UseFusedMAC]>; 1081 1082 def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 1083 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1084 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 1085 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1086 SPR:$Sdin))]>, 1087 RegConstraint<"$Sdin = $Sd">, 1088 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1089 // Some single precision VFP instructions may be executed on both NEON and 1090 // VFP pipelines. 1091 } 1092 1093 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1094 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1095 Requires<[HasVFP4,UseFusedMAC]>; 1096 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1097 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1098 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1099 1100 // Match @llvm.fma.* intrinsics 1101 // (fma x, y, z) -> (vfms z, x, y) 1102 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 1103 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1104 Requires<[HasVFP4]>; 1105 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 1106 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1107 Requires<[HasVFP4]>; 1108 1109 def VFMSD : ADbI<0b11101, 0b10, 1, 0, 1110 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1111 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 1112 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1113 (f64 DPR:$Ddin)))]>, 1114 RegConstraint<"$Ddin = $Dd">, 1115 Requires<[HasVFP4,UseFusedMAC]>; 1116 1117 def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 1118 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1119 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 1120 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1121 SPR:$Sdin))]>, 1122 RegConstraint<"$Sdin = $Sd">, 1123 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1124 // Some single precision VFP instructions may be executed on both NEON and 1125 // VFP pipelines. 1126 } 1127 1128 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1129 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1130 Requires<[HasVFP4,UseFusedMAC]>; 1131 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1132 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1133 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1134 1135 // Match @llvm.fma.* intrinsics 1136 // (fma (fneg x), y, z) -> (vfms z, x, y) 1137 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 1138 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1139 Requires<[HasVFP4]>; 1140 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 1141 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1142 Requires<[HasVFP4]>; 1143 // (fma x, (fneg y), z) -> (vfms z, x, y) 1144 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)), 1145 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1146 Requires<[HasVFP4]>; 1147 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), 1148 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1149 Requires<[HasVFP4]>; 1150 1151 def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 1152 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1153 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 1154 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1155 (f64 DPR:$Ddin)))]>, 1156 RegConstraint<"$Ddin = $Dd">, 1157 Requires<[HasVFP4,UseFusedMAC]>; 1158 1159 def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 1160 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1161 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 1162 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1163 SPR:$Sdin))]>, 1164 RegConstraint<"$Sdin = $Sd">, 1165 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1166 // Some single precision VFP instructions may be executed on both NEON and 1167 // VFP pipelines. 1168 } 1169 1170 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1171 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1172 Requires<[HasVFP4,UseFusedMAC]>; 1173 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1174 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1175 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1176 1177 // Match @llvm.fma.* intrinsics 1178 // (fneg (fma x, y, z)) -> (vfnma z, x, y) 1179 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 1180 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1181 Requires<[HasVFP4]>; 1182 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 1183 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1184 Requires<[HasVFP4]>; 1185 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 1186 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 1187 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1188 Requires<[HasVFP4]>; 1189 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 1190 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1191 Requires<[HasVFP4]>; 1192 1193 def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 1194 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1195 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 1196 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1197 (f64 DPR:$Ddin)))]>, 1198 RegConstraint<"$Ddin = $Dd">, 1199 Requires<[HasVFP4,UseFusedMAC]>; 1200 1201 def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 1202 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1203 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 1204 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1205 RegConstraint<"$Sdin = $Sd">, 1206 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1207 // Some single precision VFP instructions may be executed on both NEON and 1208 // VFP pipelines. 1209 } 1210 1211 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1212 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1213 Requires<[HasVFP4,UseFusedMAC]>; 1214 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1215 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1216 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1217 1218 // Match @llvm.fma.* intrinsics 1219 1220 // (fma x, y, (fneg z)) -> (vfnms z, x, y)) 1221 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 1222 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1223 Requires<[HasVFP4]>; 1224 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 1225 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1226 Requires<[HasVFP4]>; 1227 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 1228 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 1229 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1230 Requires<[HasVFP4]>; 1231 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 1232 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1233 Requires<[HasVFP4]>; 1234 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y) 1235 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))), 1236 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1237 Requires<[HasVFP4]>; 1238 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))), 1239 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1240 Requires<[HasVFP4]>; 1241 1242 //===----------------------------------------------------------------------===// 1243 // FP Conditional moves. 1244 // 1245 1246 let neverHasSideEffects = 1 in { 1247 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p), 1248 4, IIC_fpUNA64, 1249 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, 1250 RegConstraint<"$Dn = $Dd">; 1251 1252 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p), 1253 4, IIC_fpUNA32, 1254 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, 1255 RegConstraint<"$Sn = $Sd">; 1256 } // neverHasSideEffects 1257 1258 //===----------------------------------------------------------------------===// 1259 // Move from VFP System Register to ARM core register. 1260 // 1261 1262 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1263 list<dag> pattern>: 1264 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1265 1266 // Instruction operand. 1267 bits<4> Rt; 1268 1269 let Inst{27-20} = 0b11101111; 1270 let Inst{19-16} = opc19_16; 1271 let Inst{15-12} = Rt; 1272 let Inst{11-8} = 0b1010; 1273 let Inst{7} = 0; 1274 let Inst{6-5} = 0b00; 1275 let Inst{4} = 1; 1276 let Inst{3-0} = 0b0000; 1277 } 1278 1279 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 1280 // to APSR. 1281 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in 1282 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 1283 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 1284 1285 // Application level FPSCR -> GPR 1286 let hasSideEffects = 1, Uses = [FPSCR] in 1287 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), 1288 "vmrs", "\t$Rt, fpscr", 1289 [(set GPR:$Rt, (int_arm_get_fpscr))]>; 1290 1291 // System level FPEXC, FPSID -> GPR 1292 let Uses = [FPSCR] in { 1293 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), 1294 "vmrs", "\t$Rt, fpexc", []>; 1295 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), 1296 "vmrs", "\t$Rt, fpsid", []>; 1297 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins), 1298 "vmrs", "\t$Rt, mvfr0", []>; 1299 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins), 1300 "vmrs", "\t$Rt, mvfr1", []>; 1301 } 1302 1303 //===----------------------------------------------------------------------===// 1304 // Move from ARM core register to VFP System Register. 1305 // 1306 1307 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1308 list<dag> pattern>: 1309 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1310 1311 // Instruction operand. 1312 bits<4> src; 1313 1314 // Encode instruction operand. 1315 let Inst{15-12} = src; 1316 1317 let Inst{27-20} = 0b11101110; 1318 let Inst{19-16} = opc19_16; 1319 let Inst{11-8} = 0b1010; 1320 let Inst{7} = 0; 1321 let Inst{4} = 1; 1322 } 1323 1324 let Defs = [FPSCR] in { 1325 // Application level GPR -> FPSCR 1326 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), 1327 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; 1328 // System level GPR -> FPEXC 1329 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), 1330 "vmsr", "\tfpexc, $src", []>; 1331 // System level GPR -> FPSID 1332 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), 1333 "vmsr", "\tfpsid, $src", []>; 1334 } 1335 1336 //===----------------------------------------------------------------------===// 1337 // Misc. 1338 // 1339 1340 // Materialize FP immediates. VFP3 only. 1341 let isReMaterializable = 1 in { 1342 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 1343 VFPMiscFrm, IIC_fpUNA64, 1344 "vmov", ".f64\t$Dd, $imm", 1345 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> { 1346 bits<5> Dd; 1347 bits<8> imm; 1348 1349 let Inst{27-23} = 0b11101; 1350 let Inst{22} = Dd{4}; 1351 let Inst{21-20} = 0b11; 1352 let Inst{19-16} = imm{7-4}; 1353 let Inst{15-12} = Dd{3-0}; 1354 let Inst{11-9} = 0b101; 1355 let Inst{8} = 1; // Double precision. 1356 let Inst{7-4} = 0b0000; 1357 let Inst{3-0} = imm{3-0}; 1358 } 1359 1360 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 1361 VFPMiscFrm, IIC_fpUNA32, 1362 "vmov", ".f32\t$Sd, $imm", 1363 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 1364 bits<5> Sd; 1365 bits<8> imm; 1366 1367 let Inst{27-23} = 0b11101; 1368 let Inst{22} = Sd{0}; 1369 let Inst{21-20} = 0b11; 1370 let Inst{19-16} = imm{7-4}; 1371 let Inst{15-12} = Sd{4-1}; 1372 let Inst{11-9} = 0b101; 1373 let Inst{8} = 0; // Single precision. 1374 let Inst{7-4} = 0b0000; 1375 let Inst{3-0} = imm{3-0}; 1376 } 1377 } 1378 1379 //===----------------------------------------------------------------------===// 1380 // Assembler aliases. 1381 // 1382 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to 1383 // support them all, but supporting at least some of the basics is 1384 // good to be friendly. 1385 def : VFP2MnemonicAlias<"flds", "vldr">; 1386 def : VFP2MnemonicAlias<"fldd", "vldr">; 1387 def : VFP2MnemonicAlias<"fmrs", "vmov">; 1388 def : VFP2MnemonicAlias<"fmsr", "vmov">; 1389 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 1390 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 1391 def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 1392 def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 1393 def : VFP2MnemonicAlias<"fmrdd", "vmov">; 1394 def : VFP2MnemonicAlias<"fmrds", "vmov">; 1395 def : VFP2MnemonicAlias<"fmrrd", "vmov">; 1396 def : VFP2MnemonicAlias<"fmdrr", "vmov">; 1397 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 1398 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 1399 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 1400 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 1401 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 1402 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 1403 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 1404 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 1405 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 1406 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 1407 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 1408 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 1409 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 1410 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 1411 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 1412 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 1413 def : VFP2MnemonicAlias<"fsts", "vstr">; 1414 def : VFP2MnemonicAlias<"fstd", "vstr">; 1415 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 1416 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 1417 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 1418 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 1419 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 1420 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 1421 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 1422 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 1423 def : VFP2MnemonicAlias<"fmrx", "vmrs">; 1424 def : VFP2MnemonicAlias<"fmxr", "vmsr">; 1425 1426 // Be friendly and accept the old form of zero-compare 1427 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 1428 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 1429 1430 1431 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>; 1432 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 1433 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1434 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm", 1435 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1436 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 1437 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1438 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm", 1439 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1440 1441 // No need for the size suffix on VSQRT. It's implied by the register classes. 1442 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 1443 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 1444 1445 // VLDR/VSTR accept an optional type suffix. 1446 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 1447 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1448 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 1449 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1450 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 1451 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1452 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 1453 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1454 1455 // VMOV can accept optional 32-bit or less data type suffix suffix. 1456 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 1457 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1458 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 1459 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1460 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 1461 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1462 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 1463 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1464 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 1465 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1466 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 1467 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1468 1469 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 1470 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 1471 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 1472 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 1473 1474 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 1475 // VMOVD does. 1476 def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 1477 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 1478
