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      1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the ARM specific subclass of TargetMachine.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef ARMTARGETMACHINE_H
     15 #define ARMTARGETMACHINE_H
     16 
     17 #include "ARMInstrInfo.h"
     18 #include "ARMELFWriterInfo.h"
     19 #include "ARMFrameLowering.h"
     20 #include "ARMJITInfo.h"
     21 #include "ARMSubtarget.h"
     22 #include "ARMISelLowering.h"
     23 #include "ARMSelectionDAGInfo.h"
     24 #include "Thumb1InstrInfo.h"
     25 #include "Thumb1FrameLowering.h"
     26 #include "Thumb2InstrInfo.h"
     27 #include "llvm/Target/TargetMachine.h"
     28 #include "llvm/Target/TargetData.h"
     29 #include "llvm/MC/MCStreamer.h"
     30 #include "llvm/ADT/OwningPtr.h"
     31 
     32 namespace llvm {
     33 
     34 class ARMBaseTargetMachine : public LLVMTargetMachine {
     35 protected:
     36   ARMSubtarget        Subtarget;
     37 private:
     38   ARMJITInfo          JITInfo;
     39   InstrItineraryData  InstrItins;
     40 
     41 public:
     42   ARMBaseTargetMachine(const Target &T, StringRef TT,
     43                        StringRef CPU, StringRef FS,
     44                        const TargetOptions &Options,
     45                        Reloc::Model RM, CodeModel::Model CM,
     46                        CodeGenOpt::Level OL);
     47 
     48   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
     49   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
     50   virtual const InstrItineraryData *getInstrItineraryData() const {
     51     return &InstrItins;
     52   }
     53 
     54   // Pass Pipeline Configuration
     55   virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
     56 
     57   virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
     58 };
     59 
     60 /// ARMTargetMachine - ARM target machine.
     61 ///
     62 class ARMTargetMachine : public ARMBaseTargetMachine {
     63   virtual void anchor();
     64   ARMInstrInfo        InstrInfo;
     65   const TargetData    DataLayout;       // Calculates type size & alignment
     66   ARMELFWriterInfo    ELFWriterInfo;
     67   ARMTargetLowering   TLInfo;
     68   ARMSelectionDAGInfo TSInfo;
     69   ARMFrameLowering    FrameLowering;
     70  public:
     71   ARMTargetMachine(const Target &T, StringRef TT,
     72                    StringRef CPU, StringRef FS,
     73                    const TargetOptions &Options,
     74                    Reloc::Model RM, CodeModel::Model CM,
     75                    CodeGenOpt::Level OL);
     76 
     77   virtual const ARMRegisterInfo  *getRegisterInfo() const {
     78     return &InstrInfo.getRegisterInfo();
     79   }
     80 
     81   virtual const ARMTargetLowering *getTargetLowering() const {
     82     return &TLInfo;
     83   }
     84 
     85   virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
     86     return &TSInfo;
     87   }
     88   virtual const ARMFrameLowering *getFrameLowering() const {
     89     return &FrameLowering;
     90   }
     91 
     92   virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
     93   virtual const TargetData       *getTargetData() const { return &DataLayout; }
     94   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
     95     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
     96   }
     97 };
     98 
     99 /// ThumbTargetMachine - Thumb target machine.
    100 /// Due to the way architectures are handled, this represents both
    101 ///   Thumb-1 and Thumb-2.
    102 ///
    103 class ThumbTargetMachine : public ARMBaseTargetMachine {
    104   virtual void anchor();
    105   // Either Thumb1InstrInfo or Thumb2InstrInfo.
    106   OwningPtr<ARMBaseInstrInfo> InstrInfo;
    107   const TargetData    DataLayout;   // Calculates type size & alignment
    108   ARMELFWriterInfo    ELFWriterInfo;
    109   ARMTargetLowering   TLInfo;
    110   ARMSelectionDAGInfo TSInfo;
    111   // Either Thumb1FrameLowering or ARMFrameLowering.
    112   OwningPtr<ARMFrameLowering> FrameLowering;
    113 public:
    114   ThumbTargetMachine(const Target &T, StringRef TT,
    115                      StringRef CPU, StringRef FS,
    116                      const TargetOptions &Options,
    117                      Reloc::Model RM, CodeModel::Model CM,
    118                      CodeGenOpt::Level OL);
    119 
    120   /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
    121   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
    122     return &InstrInfo->getRegisterInfo();
    123   }
    124 
    125   virtual const ARMTargetLowering *getTargetLowering() const {
    126     return &TLInfo;
    127   }
    128 
    129   virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
    130     return &TSInfo;
    131   }
    132 
    133   /// returns either Thumb1InstrInfo or Thumb2InstrInfo
    134   virtual const ARMBaseInstrInfo *getInstrInfo() const {
    135     return InstrInfo.get();
    136   }
    137   /// returns either Thumb1FrameLowering or ARMFrameLowering
    138   virtual const ARMFrameLowering *getFrameLowering() const {
    139     return FrameLowering.get();
    140   }
    141   virtual const TargetData       *getTargetData() const { return &DataLayout; }
    142   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
    143     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
    144   }
    145 };
    146 
    147 } // end namespace llvm
    148 
    149 #endif
    150