1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is the top level entry point for the Hexagon target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Target-independent interfaces which we are implementing 16 //===----------------------------------------------------------------------===// 17 18 include "llvm/Target/Target.td" 19 20 //===----------------------------------------------------------------------===// 21 // Hexagon Subtarget features. 22 //===----------------------------------------------------------------------===// 23 24 // Hexagon Archtectures 25 def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2", 26 "Hexagon v2">; 27 def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3", 28 "Hexagon v3">; 29 def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4", 30 "Hexagon v4">; 31 def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5", 32 "Hexagon v5">; 33 34 //===----------------------------------------------------------------------===// 35 // Register File, Calling Conv, Instruction Descriptions 36 //===----------------------------------------------------------------------===// 37 include "HexagonSchedule.td" 38 include "HexagonRegisterInfo.td" 39 include "HexagonCallingConv.td" 40 include "HexagonInstrInfo.td" 41 include "HexagonIntrinsics.td" 42 include "HexagonIntrinsicsDerived.td" 43 44 def HexagonInstrInfo : InstrInfo; 45 46 //===----------------------------------------------------------------------===// 47 // Hexagon processors supported. 48 //===----------------------------------------------------------------------===// 49 50 class Proc<string Name, SchedMachineModel Model, 51 list<SubtargetFeature> Features> 52 : ProcessorModel<Name, Model, Features>; 53 54 def : Proc<"hexagonv2", HexagonModel, [ArchV2]>; 55 def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>; 56 def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>; 57 def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>; 58 59 60 // Hexagon Uses the MC printer for assembler output, so make sure the TableGen 61 // AsmWriter bits get associated with the correct class. 62 def HexagonAsmWriter : AsmWriter { 63 string AsmWriterClassName = "InstPrinter"; 64 bit isMCAsmWriter = 1; 65 } 66 67 //===----------------------------------------------------------------------===// 68 // Declare the target which we are implementing 69 //===----------------------------------------------------------------------===// 70 71 def Hexagon : Target { 72 // Pull in Instruction Info: 73 let InstructionSet = HexagonInstrInfo; 74 75 let AssemblyWriters = [HexagonAsmWriter]; 76 } 77
