1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Hexagon Intruction Flags + 12 // 13 // *** Must match HexagonBaseInfo.h *** 14 //===----------------------------------------------------------------------===// 15 16 class Type<bits<5> t> { 17 bits<5> Value = t; 18 } 19 def TypePSEUDO : Type<0>; 20 def TypeALU32 : Type<1>; 21 def TypeCR : Type<2>; 22 def TypeJR : Type<3>; 23 def TypeJ : Type<4>; 24 def TypeLD : Type<5>; 25 def TypeST : Type<6>; 26 def TypeSYSTEM : Type<7>; 27 def TypeXTYPE : Type<8>; 28 def TypeMARKER : Type<31>; 29 30 //===----------------------------------------------------------------------===// 31 // Intruction Class Declaration + 32 //===----------------------------------------------------------------------===// 33 34 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, 35 string cstr, InstrItinClass itin, Type type> : Instruction { 36 field bits<32> Inst; 37 38 let Namespace = "Hexagon"; 39 40 dag OutOperandList = outs; 41 dag InOperandList = ins; 42 let AsmString = asmstr; 43 let Pattern = pattern; 44 let Constraints = cstr; 45 let Itinerary = itin; 46 let Size = 4; 47 48 // *** Must match HexagonBaseInfo.h *** 49 // Instruction type according to the ISA. 50 Type HexagonType = type; 51 let TSFlags{4-0} = HexagonType.Value; 52 // Solo instructions, i.e., those that cannot be in a packet with others. 53 bits<1> isHexagonSolo = 0; 54 let TSFlags{5} = isHexagonSolo; 55 // Predicated instructions. 56 bits<1> isPredicated = 0; 57 let TSFlags{6} = isPredicated; 58 59 // *** The code above must match HexagonBaseInfo.h *** 60 } 61 62 //===----------------------------------------------------------------------===// 63 // Intruction Classes Definitions + 64 //===----------------------------------------------------------------------===// 65 66 // LD Instruction Class in V2/V3/V4. 67 // Definition of the instruction class NOT CHANGED. 68 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern> 69 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> { 70 bits<5> rd; 71 bits<5> rs; 72 bits<13> imm13; 73 } 74 75 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern> 76 : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> { 77 bits<5> rd; 78 bits<5> rs; 79 bits<13> imm13; 80 let mayLoad = 1; 81 } 82 83 // LD Instruction Class in V2/V3/V4. 84 // Definition of the instruction class NOT CHANGED. 85 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, 86 string cstr> 87 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> { 88 bits<5> rd; 89 bits<5> rs; 90 bits<5> rt; 91 bits<13> imm13; 92 } 93 94 // ST Instruction Class in V2/V3 can take SLOT0 only. 95 // ST Instruction Class in V4 can take SLOT0 & SLOT1. 96 // Definition of the instruction class CHANGED from V2/V3 to V4. 97 class STInst<dag outs, dag ins, string asmstr, list<dag> pattern> 98 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> { 99 bits<5> rd; 100 bits<5> rs; 101 bits<13> imm13; 102 } 103 104 class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern> 105 : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> { 106 bits<5> rd; 107 bits<5> rs; 108 bits<13> imm13; 109 let mayStore = 1; 110 } 111 112 // SYSTEM Instruction Class in V4 can take SLOT0 only 113 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. 114 class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern> 115 : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> { 116 bits<5> rd; 117 bits<5> rs; 118 bits<13> imm13; 119 } 120 121 // ST Instruction Class in V2/V3 can take SLOT0 only. 122 // ST Instruction Class in V4 can take SLOT0 & SLOT1. 123 // Definition of the instruction class CHANGED from V2/V3 to V4. 124 class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern, 125 string cstr> 126 : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> { 127 bits<5> rd; 128 bits<5> rs; 129 bits<5> rt; 130 bits<13> imm13; 131 } 132 133 // ALU32 Instruction Class in V2/V3/V4. 134 // Definition of the instruction class NOT CHANGED. 135 class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern> 136 : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> { 137 bits<5> rd; 138 bits<5> rs; 139 bits<5> rt; 140 bits<16> imm16; 141 bits<16> imm16_2; 142 } 143 144 // ALU64 Instruction Class in V2/V3. 145 // XTYPE Instruction Class in V4. 146 // Definition of the instruction class NOT CHANGED. 147 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. 148 class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern> 149 : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> { 150 bits<5> rd; 151 bits<5> rs; 152 bits<5> rt; 153 bits<16> imm16; 154 bits<16> imm16_2; 155 } 156 157 class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern, 158 string cstr> 159 : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> { 160 bits<5> rd; 161 bits<5> rs; 162 bits<5> rt; 163 bits<16> imm16; 164 bits<16> imm16_2; 165 } 166 167 // M Instruction Class in V2/V3. 168 // XTYPE Instruction Class in V4. 169 // Definition of the instruction class NOT CHANGED. 170 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 171 class MInst<dag outs, dag ins, string asmstr, list<dag> pattern> 172 : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> { 173 bits<5> rd; 174 bits<5> rs; 175 bits<5> rt; 176 } 177 178 // M Instruction Class in V2/V3. 179 // XTYPE Instruction Class in V4. 180 // Definition of the instruction class NOT CHANGED. 181 // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 182 class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, 183 string cstr> 184 : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> { 185 bits<5> rd; 186 bits<5> rs; 187 bits<5> rt; 188 } 189 190 // S Instruction Class in V2/V3. 191 // XTYPE Instruction Class in V4. 192 // Definition of the instruction class NOT CHANGED. 193 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 194 class SInst<dag outs, dag ins, string asmstr, list<dag> pattern> 195 : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> { 196 bits<5> rd; 197 bits<5> rs; 198 bits<5> rt; 199 } 200 201 // S Instruction Class in V2/V3. 202 // XTYPE Instruction Class in V4. 203 // Definition of the instruction class NOT CHANGED. 204 // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 205 class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern, 206 string cstr> 207 : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> { 208 // : InstHexagon<outs, ins, asmstr, pattern, cstr, S> { 209 // : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> { 210 bits<5> rd; 211 bits<5> rs; 212 bits<5> rt; 213 } 214 215 // J Instruction Class in V2/V3/V4. 216 // Definition of the instruction class NOT CHANGED. 217 class JType<dag outs, dag ins, string asmstr, list<dag> pattern> 218 : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> { 219 bits<16> imm16; 220 } 221 222 // JR Instruction Class in V2/V3/V4. 223 // Definition of the instruction class NOT CHANGED. 224 class JRType<dag outs, dag ins, string asmstr, list<dag> pattern> 225 : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> { 226 bits<5> rs; 227 bits<5> pu; // Predicate register 228 } 229 230 // CR Instruction Class in V2/V3/V4. 231 // Definition of the instruction class NOT CHANGED. 232 class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern> 233 : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> { 234 bits<5> rs; 235 bits<10> imm10; 236 } 237 238 class Marker<dag outs, dag ins, string asmstr, list<dag> pattern> 239 : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> { 240 let isCodeGenOnly = 1; 241 let isPseudo = 1; 242 } 243 244 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 245 : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> { 246 let isCodeGenOnly = 1; 247 let isPseudo = 1; 248 } 249 250 //===----------------------------------------------------------------------===// 251 // Intruction Classes Definitions - 252 //===----------------------------------------------------------------------===// 253 254 255 // 256 // ALU32 patterns 257 //. 258 class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern> 259 : ALU32Type<outs, ins, asmstr, pattern> { 260 } 261 262 class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern> 263 : ALU32Type<outs, ins, asmstr, pattern> { 264 let rt{0-4} = 0; 265 } 266 267 class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern> 268 : ALU32Type<outs, ins, asmstr, pattern> { 269 let rt{0-4} = 0; 270 } 271 272 class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern> 273 : ALU32Type<outs, ins, asmstr, pattern> { 274 let rt{0-4} = 0; 275 } 276 277 // 278 // ALU64 patterns. 279 // 280 class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern> 281 : ALU64Type<outs, ins, asmstr, pattern> { 282 } 283 284 class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern> 285 : ALU64Type<outs, ins, asmstr, pattern> { 286 let rt{0-4} = 0; 287 } 288 289 // J Type Instructions. 290 class JInst<dag outs, dag ins, string asmstr, list<dag> pattern> 291 : JType<outs, ins, asmstr, pattern> { 292 } 293 294 // JR type Instructions. 295 class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern> 296 : JRType<outs, ins, asmstr, pattern> { 297 } 298 299 300 // Post increment ST Instruction. 301 class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, 302 string cstr> 303 : STInstPost<outs, ins, asmstr, pattern, cstr> { 304 let rt{0-4} = 0; 305 } 306 307 class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern, 308 string cstr> 309 : STInstPost<outs, ins, asmstr, pattern, cstr> { 310 let rt{0-4} = 0; 311 let mayStore = 1; 312 } 313 314 // Post increment LD Instruction. 315 class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, 316 string cstr> 317 : LDInstPost<outs, ins, asmstr, pattern, cstr> { 318 let rt{0-4} = 0; 319 } 320 321 class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern, 322 string cstr> 323 : LDInstPost<outs, ins, asmstr, pattern, cstr> { 324 let rt{0-4} = 0; 325 let mayLoad = 1; 326 } 327 328 //===----------------------------------------------------------------------===// 329 // V4 Instruction Format Definitions + 330 //===----------------------------------------------------------------------===// 331 332 include "HexagonInstrFormatsV4.td" 333 334 //===----------------------------------------------------------------------===// 335 // V4 Instruction Format Definitions + 336 //===----------------------------------------------------------------------===// 337
