1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hexagon V4 instruction classes in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //----------------------------------------------------------------------------// 15 // Hexagon Intruction Flags + 16 // 17 // *** Must match BaseInfo.h *** 18 //----------------------------------------------------------------------------// 19 20 def TypeMEMOP : Type<9>; 21 def TypeNV : Type<10>; 22 def TypePREFIX : Type<30>; 23 24 //----------------------------------------------------------------------------// 25 // Intruction Classes Definitions + 26 //----------------------------------------------------------------------------// 27 28 // 29 // NV type instructions. 30 // 31 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern> 32 : InstHexagon<outs, ins, asmstr, pattern, "", NV_V4, TypeNV> { 33 bits<5> rd; 34 bits<5> rs; 35 bits<13> imm13; 36 } 37 38 // Definition of Post increment new value store. 39 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern, 40 string cstr> 41 : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV> { 42 bits<5> rd; 43 bits<5> rs; 44 bits<5> rt; 45 bits<13> imm13; 46 } 47 48 // Post increment ST Instruction. 49 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern, 50 string cstr> 51 : NVInstPost_V4<outs, ins, asmstr, pattern, cstr> { 52 let rt{0-4} = 0; 53 } 54 55 class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern> 56 : InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4, TypeMEMOP> { 57 bits<5> rd; 58 bits<5> rs; 59 bits<6> imm6; 60 } 61 62 class Immext<dag outs, dag ins, string asmstr, list<dag> pattern> 63 : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX> { 64 let isCodeGenOnly = 1; 65 66 bits<26> imm26; 67 } 68
