1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hexagon V4 instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 let neverHasSideEffects = 1 in 15 def IMMEXT : Immext<(outs), (ins), 16 "/* immext #... */", 17 []>, 18 Requires<[HasV4T]>; 19 20 // Hexagon V4 Architecture spec defines 8 instruction classes: 21 // LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the 22 // compiler) 23 24 // LD Instructions: 25 // ======================================== 26 // Loads (8/16/32/64 bit) 27 // Deallocframe 28 29 // ST Instructions: 30 // ======================================== 31 // Stores (8/16/32/64 bit) 32 // Allocframe 33 34 // ALU32 Instructions: 35 // ======================================== 36 // Arithmetic / Logical (32 bit) 37 // Vector Halfword 38 39 // XTYPE Instructions (32/64 bit): 40 // ======================================== 41 // Arithmetic, Logical, Bit Manipulation 42 // Multiply (Integer, Fractional, Complex) 43 // Permute / Vector Permute Operations 44 // Predicate Operations 45 // Shift / Shift with Add/Sub/Logical 46 // Vector Byte ALU 47 // Vector Halfword (ALU, Shift, Multiply) 48 // Vector Word (ALU, Shift) 49 50 // J Instructions: 51 // ======================================== 52 // Jump/Call PC-relative 53 54 // JR Instructions: 55 // ======================================== 56 // Jump/Call Register 57 58 // MEMOP Instructions: 59 // ======================================== 60 // Operation on memory (8/16/32 bit) 61 62 // NV Instructions: 63 // ======================================== 64 // New-value Jumps 65 // New-value Stores 66 67 // CR Instructions: 68 // ======================================== 69 // Control-Register Transfers 70 // Hardware Loop Setup 71 // Predicate Logicals & Reductions 72 73 // SYSTEM Instructions (not implemented in the compiler): 74 // ======================================== 75 // Prefetch 76 // Cache Maintenance 77 // Bus Operations 78 79 80 //===----------------------------------------------------------------------===// 81 // ALU32 + 82 //===----------------------------------------------------------------------===// 83 84 // Shift halfword. 85 86 let isPredicated = 1 in 87 def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), 88 (ins PredRegs:$src1, IntRegs:$src2), 89 "if ($src1) $dst = aslh($src2)", 90 []>, 91 Requires<[HasV4T]>; 92 93 let isPredicated = 1 in 94 def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 95 (ins PredRegs:$src1, IntRegs:$src2), 96 "if (!$src1) $dst = aslh($src2)", 97 []>, 98 Requires<[HasV4T]>; 99 100 let isPredicated = 1 in 101 def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), 102 (ins PredRegs:$src1, IntRegs:$src2), 103 "if ($src1.new) $dst = aslh($src2)", 104 []>, 105 Requires<[HasV4T]>; 106 107 let isPredicated = 1 in 108 def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 109 (ins PredRegs:$src1, IntRegs:$src2), 110 "if (!$src1.new) $dst = aslh($src2)", 111 []>, 112 Requires<[HasV4T]>; 113 114 let isPredicated = 1 in 115 def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), 116 (ins PredRegs:$src1, IntRegs:$src2), 117 "if ($src1) $dst = asrh($src2)", 118 []>, 119 Requires<[HasV4T]>; 120 121 let isPredicated = 1 in 122 def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 123 (ins PredRegs:$src1, IntRegs:$src2), 124 "if (!$src1) $dst = asrh($src2)", 125 []>, 126 Requires<[HasV4T]>; 127 128 let isPredicated = 1 in 129 def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), 130 (ins PredRegs:$src1, IntRegs:$src2), 131 "if ($src1.new) $dst = asrh($src2)", 132 []>, 133 Requires<[HasV4T]>; 134 135 let isPredicated = 1 in 136 def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 137 (ins PredRegs:$src1, IntRegs:$src2), 138 "if (!$src1.new) $dst = asrh($src2)", 139 []>, 140 Requires<[HasV4T]>; 141 142 // Sign extend. 143 144 let isPredicated = 1 in 145 def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), 146 (ins PredRegs:$src1, IntRegs:$src2), 147 "if ($src1) $dst = sxtb($src2)", 148 []>, 149 Requires<[HasV4T]>; 150 151 let isPredicated = 1 in 152 def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 153 (ins PredRegs:$src1, IntRegs:$src2), 154 "if (!$src1) $dst = sxtb($src2)", 155 []>, 156 Requires<[HasV4T]>; 157 158 let isPredicated = 1 in 159 def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), 160 (ins PredRegs:$src1, IntRegs:$src2), 161 "if ($src1.new) $dst = sxtb($src2)", 162 []>, 163 Requires<[HasV4T]>; 164 165 let isPredicated = 1 in 166 def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 167 (ins PredRegs:$src1, IntRegs:$src2), 168 "if (!$src1.new) $dst = sxtb($src2)", 169 []>, 170 Requires<[HasV4T]>; 171 172 173 let isPredicated = 1 in 174 def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), 175 (ins PredRegs:$src1, IntRegs:$src2), 176 "if ($src1) $dst = sxth($src2)", 177 []>, 178 Requires<[HasV4T]>; 179 180 let isPredicated = 1 in 181 def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 182 (ins PredRegs:$src1, IntRegs:$src2), 183 "if (!$src1) $dst = sxth($src2)", 184 []>, 185 Requires<[HasV4T]>; 186 187 let isPredicated = 1 in 188 def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), 189 (ins PredRegs:$src1, IntRegs:$src2), 190 "if ($src1.new) $dst = sxth($src2)", 191 []>, 192 Requires<[HasV4T]>; 193 194 let isPredicated = 1 in 195 def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 196 (ins PredRegs:$src1, IntRegs:$src2), 197 "if (!$src1.new) $dst = sxth($src2)", 198 []>, 199 Requires<[HasV4T]>; 200 201 // Zero exten. 202 203 let neverHasSideEffects = 1, isPredicated = 1 in 204 def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), 205 (ins PredRegs:$src1, IntRegs:$src2), 206 "if ($src1) $dst = zxtb($src2)", 207 []>, 208 Requires<[HasV4T]>; 209 210 let neverHasSideEffects = 1, isPredicated = 1 in 211 def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 212 (ins PredRegs:$src1, IntRegs:$src2), 213 "if (!$src1) $dst = zxtb($src2)", 214 []>, 215 Requires<[HasV4T]>; 216 217 let neverHasSideEffects = 1, isPredicated = 1 in 218 def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), 219 (ins PredRegs:$src1, IntRegs:$src2), 220 "if ($src1.new) $dst = zxtb($src2)", 221 []>, 222 Requires<[HasV4T]>; 223 224 let neverHasSideEffects = 1, isPredicated = 1 in 225 def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 226 (ins PredRegs:$src1, IntRegs:$src2), 227 "if (!$src1.new) $dst = zxtb($src2)", 228 []>, 229 Requires<[HasV4T]>; 230 231 let neverHasSideEffects = 1, isPredicated = 1 in 232 def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), 233 (ins PredRegs:$src1, IntRegs:$src2), 234 "if ($src1) $dst = zxth($src2)", 235 []>, 236 Requires<[HasV4T]>; 237 238 let neverHasSideEffects = 1, isPredicated = 1 in 239 def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 240 (ins PredRegs:$src1, IntRegs:$src2), 241 "if (!$src1) $dst = zxth($src2)", 242 []>, 243 Requires<[HasV4T]>; 244 245 let neverHasSideEffects = 1, isPredicated = 1 in 246 def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), 247 (ins PredRegs:$src1, IntRegs:$src2), 248 "if ($src1.new) $dst = zxth($src2)", 249 []>, 250 Requires<[HasV4T]>; 251 252 let neverHasSideEffects = 1, isPredicated = 1 in 253 def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), 254 (ins PredRegs:$src1, IntRegs:$src2), 255 "if (!$src1.new) $dst = zxth($src2)", 256 []>, 257 Requires<[HasV4T]>; 258 259 // Generate frame index addresses. 260 let neverHasSideEffects = 1, isReMaterializable = 1 in 261 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst), 262 (ins IntRegs:$src1, s32Imm:$offset), 263 "$dst = add($src1, ##$offset)", 264 []>, 265 Requires<[HasV4T]>; 266 267 268 //===----------------------------------------------------------------------===// 269 // ALU32 - 270 //===----------------------------------------------------------------------===// 271 272 273 //===----------------------------------------------------------------------===// 274 // ALU32/PERM + 275 //===----------------------------------------------------------------------===// 276 277 // Combine 278 // Rdd=combine(Rs, #s8) 279 let neverHasSideEffects = 1 in 280 def COMBINE_ri_V4 : ALU32_ri<(outs DoubleRegs:$dst), 281 (ins IntRegs:$src1, s8Imm:$src2), 282 "$dst = combine($src1, #$src2)", 283 []>, 284 Requires<[HasV4T]>; 285 // Rdd=combine(#s8, Rs) 286 let neverHasSideEffects = 1 in 287 def COMBINE_ir_V4 : ALU32_ir<(outs DoubleRegs:$dst), 288 (ins s8Imm:$src1, IntRegs:$src2), 289 "$dst = combine(#$src1, $src2)", 290 []>, 291 Requires<[HasV4T]>; 292 //===----------------------------------------------------------------------===// 293 // ALU32/PERM + 294 //===----------------------------------------------------------------------===// 295 296 //===----------------------------------------------------------------------===// 297 // LD + 298 //===----------------------------------------------------------------------===// 299 // 300 // These absolute set addressing mode instructions accept immediate as 301 // an operand. We have duplicated these patterns to take global address. 302 303 let neverHasSideEffects = 1 in 304 def LDrid_abs_setimm_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2), 305 (ins u6Imm:$addr), 306 "$dst1 = memd($dst2=#$addr)", 307 []>, 308 Requires<[HasV4T]>; 309 310 // Rd=memb(Re=#U6) 311 let neverHasSideEffects = 1 in 312 def LDrib_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 313 (ins u6Imm:$addr), 314 "$dst1 = memb($dst2=#$addr)", 315 []>, 316 Requires<[HasV4T]>; 317 318 // Rd=memh(Re=#U6) 319 let neverHasSideEffects = 1 in 320 def LDrih_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 321 (ins u6Imm:$addr), 322 "$dst1 = memh($dst2=#$addr)", 323 []>, 324 Requires<[HasV4T]>; 325 326 // Rd=memub(Re=#U6) 327 let neverHasSideEffects = 1 in 328 def LDriub_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 329 (ins u6Imm:$addr), 330 "$dst1 = memub($dst2=#$addr)", 331 []>, 332 Requires<[HasV4T]>; 333 334 // Rd=memuh(Re=#U6) 335 let neverHasSideEffects = 1 in 336 def LDriuh_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 337 (ins u6Imm:$addr), 338 "$dst1 = memuh($dst2=#$addr)", 339 []>, 340 Requires<[HasV4T]>; 341 342 // Rd=memw(Re=#U6) 343 let neverHasSideEffects = 1 in 344 def LDriw_abs_setimm_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 345 (ins u6Imm:$addr), 346 "$dst1 = memw($dst2=#$addr)", 347 []>, 348 Requires<[HasV4T]>; 349 350 // Following patterns are defined for absolute set addressing mode 351 // instruction which take global address as operand. 352 let neverHasSideEffects = 1 in 353 def LDrid_abs_set_V4 : LDInst2<(outs DoubleRegs:$dst1, IntRegs:$dst2), 354 (ins globaladdress:$addr), 355 "$dst1 = memd($dst2=##$addr)", 356 []>, 357 Requires<[HasV4T]>; 358 359 // Rd=memb(Re=#U6) 360 let neverHasSideEffects = 1 in 361 def LDrib_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 362 (ins globaladdress:$addr), 363 "$dst1 = memb($dst2=##$addr)", 364 []>, 365 Requires<[HasV4T]>; 366 367 // Rd=memh(Re=#U6) 368 let neverHasSideEffects = 1 in 369 def LDrih_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 370 (ins globaladdress:$addr), 371 "$dst1 = memh($dst2=##$addr)", 372 []>, 373 Requires<[HasV4T]>; 374 375 // Rd=memub(Re=#U6) 376 let neverHasSideEffects = 1 in 377 def LDriub_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 378 (ins globaladdress:$addr), 379 "$dst1 = memub($dst2=##$addr)", 380 []>, 381 Requires<[HasV4T]>; 382 383 // Rd=memuh(Re=#U6) 384 let neverHasSideEffects = 1 in 385 def LDriuh_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 386 (ins globaladdress:$addr), 387 "$dst1 = memuh($dst2=##$addr)", 388 []>, 389 Requires<[HasV4T]>; 390 391 // Rd=memw(Re=#U6) 392 let neverHasSideEffects = 1 in 393 def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2), 394 (ins globaladdress:$addr), 395 "$dst1 = memw($dst2=##$addr)", 396 []>, 397 Requires<[HasV4T]>; 398 399 // Load doubleword. 400 // 401 // Make sure that in post increment load, the first operand is always the post 402 // increment operand. 403 // 404 // Rdd=memd(Rs+Rt<<#u2) 405 // Special case pattern for indexed load without offset which is easier to 406 // match. AddedComplexity of this pattern should be lower than base+offset load 407 // and lower yet than the more generic version with offset/shift below 408 // Similar approach is taken for all other base+index loads. 409 let AddedComplexity = 10, isPredicable = 1 in 410 def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst), 411 (ins IntRegs:$src1, IntRegs:$src2), 412 "$dst=memd($src1+$src2<<#0)", 413 [(set (i64 DoubleRegs:$dst), 414 (i64 (load (add (i32 IntRegs:$src1), 415 (i32 IntRegs:$src2)))))]>, 416 Requires<[HasV4T]>; 417 418 let AddedComplexity = 40, isPredicable = 1 in 419 def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst), 420 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 421 "$dst=memd($src1+$src2<<#$offset)", 422 [(set (i64 DoubleRegs:$dst), 423 (i64 (load (add (i32 IntRegs:$src1), 424 (shl (i32 IntRegs:$src2), 425 u2ImmPred:$offset)))))]>, 426 Requires<[HasV4T]>; 427 428 //// Load doubleword conditionally. 429 // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2) 430 // if (Pv) Rd=memd(Rs+Rt<<#u2) 431 let AddedComplexity = 15, isPredicated = 1 in 432 def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst), 433 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 434 "if ($src1) $dst=memd($src2+$src3<<#0)", 435 []>, 436 Requires<[HasV4T]>; 437 438 // if (Pv.new) Rd=memd(Rs+Rt<<#u2) 439 let AddedComplexity = 15, isPredicated = 1 in 440 def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst), 441 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 442 "if ($src1.new) $dst=memd($src2+$src3<<#0)", 443 []>, 444 Requires<[HasV4T]>; 445 446 // if (!Pv) Rd=memd(Rs+Rt<<#u2) 447 let AddedComplexity = 15, isPredicated = 1 in 448 def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 449 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 450 "if (!$src1) $dst=memd($src2+$src3<<#0)", 451 []>, 452 Requires<[HasV4T]>; 453 454 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2) 455 let AddedComplexity = 15, isPredicated = 1 in 456 def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 457 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 458 "if (!$src1.new) $dst=memd($src2+$src3<<#0)", 459 []>, 460 Requires<[HasV4T]>; 461 462 // if (Pv) Rd=memd(Rs+Rt<<#u2) 463 let AddedComplexity = 45, isPredicated = 1 in 464 def LDrid_indexed_shl_cPt_V4 : LDInst2<(outs DoubleRegs:$dst), 465 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 466 u2Imm:$offset), 467 "if ($src1) $dst=memd($src2+$src3<<#$offset)", 468 []>, 469 Requires<[HasV4T]>; 470 471 // if (Pv.new) Rd=memd(Rs+Rt<<#u2) 472 let AddedComplexity = 45, isPredicated = 1 in 473 def LDrid_indexed_shl_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst), 474 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 475 u2Imm:$offset), 476 "if ($src1.new) $dst=memd($src2+$src3<<#$offset)", 477 []>, 478 Requires<[HasV4T]>; 479 480 // if (!Pv) Rd=memd(Rs+Rt<<#u2) 481 let AddedComplexity = 45, isPredicated = 1 in 482 def LDrid_indexed_shl_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 483 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 484 u2Imm:$offset), 485 "if (!$src1) $dst=memd($src2+$src3<<#$offset)", 486 []>, 487 Requires<[HasV4T]>; 488 489 // if (!Pv.new) Rd=memd(Rs+Rt<<#u2) 490 let AddedComplexity = 45, isPredicated = 1 in 491 def LDrid_indexed_shl_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 492 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 493 u2Imm:$offset), 494 "if (!$src1.new) $dst=memd($src2+$src3<<#$offset)", 495 []>, 496 Requires<[HasV4T]>; 497 498 // Rdd=memd(Rt<<#u2+#U6) 499 500 //// Load byte. 501 // Rd=memb(Rs+Rt<<#u2) 502 let AddedComplexity = 10, isPredicable = 1 in 503 def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst), 504 (ins IntRegs:$src1, IntRegs:$src2), 505 "$dst=memb($src1+$src2<<#0)", 506 [(set (i32 IntRegs:$dst), 507 (i32 (sextloadi8 (add (i32 IntRegs:$src1), 508 (i32 IntRegs:$src2)))))]>, 509 Requires<[HasV4T]>; 510 511 let AddedComplexity = 10, isPredicable = 1 in 512 def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst), 513 (ins IntRegs:$src1, IntRegs:$src2), 514 "$dst=memub($src1+$src2<<#0)", 515 [(set (i32 IntRegs:$dst), 516 (i32 (zextloadi8 (add (i32 IntRegs:$src1), 517 (i32 IntRegs:$src2)))))]>, 518 Requires<[HasV4T]>; 519 520 let AddedComplexity = 10, isPredicable = 1 in 521 def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst), 522 (ins IntRegs:$src1, IntRegs:$src2), 523 "$dst=memub($src1+$src2<<#0)", 524 [(set (i32 IntRegs:$dst), 525 (i32 (extloadi8 (add (i32 IntRegs:$src1), 526 (i32 IntRegs:$src2)))))]>, 527 Requires<[HasV4T]>; 528 529 let AddedComplexity = 40, isPredicable = 1 in 530 def LDrib_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), 531 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 532 "$dst=memb($src1+$src2<<#$offset)", 533 [(set (i32 IntRegs:$dst), 534 (i32 (sextloadi8 (add (i32 IntRegs:$src1), 535 (shl (i32 IntRegs:$src2), 536 u2ImmPred:$offset)))))]>, 537 Requires<[HasV4T]>; 538 539 let AddedComplexity = 40, isPredicable = 1 in 540 def LDriub_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), 541 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 542 "$dst=memub($src1+$src2<<#$offset)", 543 [(set (i32 IntRegs:$dst), 544 (i32 (zextloadi8 (add (i32 IntRegs:$src1), 545 (shl (i32 IntRegs:$src2), 546 u2ImmPred:$offset)))))]>, 547 Requires<[HasV4T]>; 548 549 let AddedComplexity = 40, isPredicable = 1 in 550 def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), 551 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 552 "$dst=memub($src1+$src2<<#$offset)", 553 [(set (i32 IntRegs:$dst), 554 (i32 (extloadi8 (add (i32 IntRegs:$src1), 555 (shl (i32 IntRegs:$src2), 556 u2ImmPred:$offset)))))]>, 557 Requires<[HasV4T]>; 558 559 //// Load byte conditionally. 560 // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2) 561 // if (Pv) Rd=memb(Rs+Rt<<#u2) 562 let AddedComplexity = 15, isPredicated = 1 in 563 def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst), 564 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 565 "if ($src1) $dst=memb($src2+$src3<<#0)", 566 []>, 567 Requires<[HasV4T]>; 568 569 // if (Pv.new) Rd=memb(Rs+Rt<<#u2) 570 let AddedComplexity = 15, isPredicated = 1 in 571 def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 572 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 573 "if ($src1.new) $dst=memb($src2+$src3<<#0)", 574 []>, 575 Requires<[HasV4T]>; 576 577 // if (!Pv) Rd=memb(Rs+Rt<<#u2) 578 let AddedComplexity = 15, isPredicated = 1 in 579 def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 580 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 581 "if (!$src1) $dst=memb($src2+$src3<<#0)", 582 []>, 583 Requires<[HasV4T]>; 584 585 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2) 586 let AddedComplexity = 15, isPredicated = 1 in 587 def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 588 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 589 "if (!$src1.new) $dst=memb($src2+$src3<<#0)", 590 []>, 591 Requires<[HasV4T]>; 592 593 // if (Pv) Rd=memb(Rs+Rt<<#u2) 594 let AddedComplexity = 45, isPredicated = 1 in 595 def LDrib_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), 596 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 597 u2Imm:$offset), 598 "if ($src1) $dst=memb($src2+$src3<<#$offset)", 599 []>, 600 Requires<[HasV4T]>; 601 602 // if (Pv.new) Rd=memb(Rs+Rt<<#u2) 603 let AddedComplexity = 45, isPredicated = 1 in 604 def LDrib_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 605 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 606 u2Imm:$offset), 607 "if ($src1.new) $dst=memb($src2+$src3<<#$offset)", 608 []>, 609 Requires<[HasV4T]>; 610 611 // if (!Pv) Rd=memb(Rs+Rt<<#u2) 612 let AddedComplexity = 45, isPredicated = 1 in 613 def LDrib_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 614 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 615 u2Imm:$offset), 616 "if (!$src1) $dst=memb($src2+$src3<<#$offset)", 617 []>, 618 Requires<[HasV4T]>; 619 620 // if (!Pv.new) Rd=memb(Rs+Rt<<#u2) 621 let AddedComplexity = 45, isPredicated = 1 in 622 def LDrib_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 623 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 624 u2Imm:$offset), 625 "if (!$src1.new) $dst=memb($src2+$src3<<#$offset)", 626 []>, 627 Requires<[HasV4T]>; 628 629 //// Load unsigned byte conditionally. 630 // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2) 631 // if (Pv) Rd=memub(Rs+Rt<<#u2) 632 let AddedComplexity = 15, isPredicated = 1 in 633 def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst), 634 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 635 "if ($src1) $dst=memub($src2+$src3<<#0)", 636 []>, 637 Requires<[HasV4T]>; 638 639 // if (Pv.new) Rd=memub(Rs+Rt<<#u2) 640 let AddedComplexity = 15, isPredicated = 1 in 641 def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 642 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 643 "if ($src1.new) $dst=memub($src2+$src3<<#0)", 644 []>, 645 Requires<[HasV4T]>; 646 647 // if (!Pv) Rd=memub(Rs+Rt<<#u2) 648 let AddedComplexity = 15, isPredicated = 1 in 649 def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 650 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 651 "if (!$src1) $dst=memub($src2+$src3<<#0)", 652 []>, 653 Requires<[HasV4T]>; 654 655 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2) 656 let AddedComplexity = 15, isPredicated = 1 in 657 def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 658 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 659 "if (!$src1.new) $dst=memub($src2+$src3<<#0)", 660 []>, 661 Requires<[HasV4T]>; 662 663 // if (Pv) Rd=memub(Rs+Rt<<#u2) 664 let AddedComplexity = 45, isPredicated = 1 in 665 def LDriub_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), 666 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 667 u2Imm:$offset), 668 "if ($src1) $dst=memub($src2+$src3<<#$offset)", 669 []>, 670 Requires<[HasV4T]>; 671 672 // if (Pv.new) Rd=memub(Rs+Rt<<#u2) 673 let AddedComplexity = 45, isPredicated = 1 in 674 def LDriub_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 675 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 676 u2Imm:$offset), 677 "if ($src1.new) $dst=memub($src2+$src3<<#$offset)", 678 []>, 679 Requires<[HasV4T]>; 680 681 // if (!Pv) Rd=memub(Rs+Rt<<#u2) 682 let AddedComplexity = 45, isPredicated = 1 in 683 def LDriub_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 684 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 685 u2Imm:$offset), 686 "if (!$src1) $dst=memub($src2+$src3<<#$offset)", 687 []>, 688 Requires<[HasV4T]>; 689 690 // if (!Pv.new) Rd=memub(Rs+Rt<<#u2) 691 let AddedComplexity = 45, isPredicated = 1 in 692 def LDriub_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 693 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 694 u2Imm:$offset), 695 "if (!$src1.new) $dst=memub($src2+$src3<<#$offset)", 696 []>, 697 Requires<[HasV4T]>; 698 699 // Rd=memb(Rt<<#u2+#U6) 700 701 //// Load halfword 702 // Rd=memh(Rs+Rt<<#u2) 703 let AddedComplexity = 10, isPredicable = 1 in 704 def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst), 705 (ins IntRegs:$src1, IntRegs:$src2), 706 "$dst=memh($src1+$src2<<#0)", 707 [(set (i32 IntRegs:$dst), 708 (i32 (sextloadi16 (add (i32 IntRegs:$src1), 709 (i32 IntRegs:$src2)))))]>, 710 Requires<[HasV4T]>; 711 712 let AddedComplexity = 10, isPredicable = 1 in 713 def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst), 714 (ins IntRegs:$src1, IntRegs:$src2), 715 "$dst=memuh($src1+$src2<<#0)", 716 [(set (i32 IntRegs:$dst), 717 (i32 (zextloadi16 (add (i32 IntRegs:$src1), 718 (i32 IntRegs:$src2)))))]>, 719 Requires<[HasV4T]>; 720 721 let AddedComplexity = 10, isPredicable = 1 in 722 def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst), 723 (ins IntRegs:$src1, IntRegs:$src2), 724 "$dst=memuh($src1+$src2<<#0)", 725 [(set (i32 IntRegs:$dst), 726 (i32 (extloadi16 (add (i32 IntRegs:$src1), 727 (i32 IntRegs:$src2)))))]>, 728 Requires<[HasV4T]>; 729 730 // Rd=memh(Rs+Rt<<#u2) 731 let AddedComplexity = 40, isPredicable = 1 in 732 def LDrih_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), 733 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 734 "$dst=memh($src1+$src2<<#$offset)", 735 [(set (i32 IntRegs:$dst), 736 (i32 (sextloadi16 (add (i32 IntRegs:$src1), 737 (shl (i32 IntRegs:$src2), 738 u2ImmPred:$offset)))))]>, 739 Requires<[HasV4T]>; 740 741 let AddedComplexity = 40, isPredicable = 1 in 742 def LDriuh_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), 743 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 744 "$dst=memuh($src1+$src2<<#$offset)", 745 [(set (i32 IntRegs:$dst), 746 (i32 (zextloadi16 (add (i32 IntRegs:$src1), 747 (shl (i32 IntRegs:$src2), 748 u2ImmPred:$offset)))))]>, 749 Requires<[HasV4T]>; 750 751 let AddedComplexity = 40, isPredicable = 1 in 752 def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), 753 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 754 "$dst=memuh($src1+$src2<<#$offset)", 755 [(set (i32 IntRegs:$dst), 756 (i32 (extloadi16 (add (i32 IntRegs:$src1), 757 (shl (i32 IntRegs:$src2), 758 u2ImmPred:$offset)))))]>, 759 Requires<[HasV4T]>; 760 761 //// Load halfword conditionally. 762 // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2) 763 // if (Pv) Rd=memh(Rs+Rt<<#u2) 764 let AddedComplexity = 15, isPredicated = 1 in 765 def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst), 766 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 767 "if ($src1) $dst=memh($src2+$src3<<#0)", 768 []>, 769 Requires<[HasV4T]>; 770 771 // if (Pv.new) Rd=memh(Rs+Rt<<#u2) 772 let AddedComplexity = 15, isPredicated = 1 in 773 def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 774 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 775 "if ($src1.new) $dst=memh($src2+$src3<<#0)", 776 []>, 777 Requires<[HasV4T]>; 778 779 // if (!Pv) Rd=memh(Rs+Rt<<#u2) 780 let AddedComplexity = 15, isPredicated = 1 in 781 def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 782 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 783 "if (!$src1) $dst=memh($src2+$src3<<#0)", 784 []>, 785 Requires<[HasV4T]>; 786 787 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) 788 let AddedComplexity = 15, isPredicated = 1 in 789 def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 790 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 791 "if (!$src1.new) $dst=memh($src2+$src3<<#0)", 792 []>, 793 Requires<[HasV4T]>; 794 795 // if (Pv) Rd=memh(Rs+Rt<<#u2) 796 let AddedComplexity = 45, isPredicated = 1 in 797 def LDrih_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), 798 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 799 u2Imm:$offset), 800 "if ($src1) $dst=memh($src2+$src3<<#$offset)", 801 []>, 802 Requires<[HasV4T]>; 803 804 // if (Pv.new) Rd=memh(Rs+Rt<<#u2) 805 let AddedComplexity = 45, isPredicated = 1 in 806 def LDrih_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 807 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 808 u2Imm:$offset), 809 "if ($src1.new) $dst=memh($src2+$src3<<#$offset)", 810 []>, 811 Requires<[HasV4T]>; 812 813 // if (!Pv) Rd=memh(Rs+Rt<<#u2) 814 let AddedComplexity = 45, isPredicated = 1 in 815 def LDrih_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 816 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 817 u2Imm:$offset), 818 "if (!$src1) $dst=memh($src2+$src3<<#$offset)", 819 []>, 820 Requires<[HasV4T]>; 821 822 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) 823 let AddedComplexity = 45, isPredicated = 1 in 824 def LDrih_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 825 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 826 u2Imm:$offset), 827 "if (!$src1.new) $dst=memh($src2+$src3<<#$offset)", 828 []>, 829 Requires<[HasV4T]>; 830 831 //// Load unsigned halfword conditionally. 832 // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2) 833 // if (Pv) Rd=memuh(Rs+Rt<<#u2) 834 let AddedComplexity = 15, isPredicated = 1 in 835 def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst), 836 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 837 "if ($src1) $dst=memuh($src2+$src3<<#0)", 838 []>, 839 Requires<[HasV4T]>; 840 841 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2) 842 let AddedComplexity = 15, isPredicated = 1 in 843 def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 844 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 845 "if ($src1.new) $dst=memuh($src2+$src3<<#0)", 846 []>, 847 Requires<[HasV4T]>; 848 849 // if (!Pv) Rd=memuh(Rs+Rt<<#u2) 850 let AddedComplexity = 15, isPredicated = 1 in 851 def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 852 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 853 "if (!$src1) $dst=memuh($src2+$src3<<#0)", 854 []>, 855 Requires<[HasV4T]>; 856 857 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) 858 let AddedComplexity = 15, isPredicated = 1 in 859 def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 860 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 861 "if (!$src1.new) $dst=memuh($src2+$src3<<#0)", 862 []>, 863 Requires<[HasV4T]>; 864 865 // if (Pv) Rd=memuh(Rs+Rt<<#u2) 866 let AddedComplexity = 45, isPredicated = 1 in 867 def LDriuh_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), 868 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 869 u2Imm:$offset), 870 "if ($src1) $dst=memuh($src2+$src3<<#$offset)", 871 []>, 872 Requires<[HasV4T]>; 873 874 // if (Pv.new) Rd=memuh(Rs+Rt<<#u2) 875 let AddedComplexity = 45, isPredicated = 1 in 876 def LDriuh_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 877 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 878 u2Imm:$offset), 879 "if ($src1.new) $dst=memuh($src2+$src3<<#$offset)", 880 []>, 881 Requires<[HasV4T]>; 882 883 // if (!Pv) Rd=memuh(Rs+Rt<<#u2) 884 let AddedComplexity = 45, isPredicated = 1 in 885 def LDriuh_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 886 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 887 u2Imm:$offset), 888 "if (!$src1) $dst=memuh($src2+$src3<<#$offset)", 889 []>, 890 Requires<[HasV4T]>; 891 892 // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) 893 let AddedComplexity = 45, isPredicated = 1 in 894 def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 895 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 896 u2Imm:$offset), 897 "if (!$src1.new) $dst=memuh($src2+$src3<<#$offset)", 898 []>, 899 Requires<[HasV4T]>; 900 901 // Rd=memh(Rt<<#u2+#U6) 902 903 //// Load word. 904 // Load predicate: Fix for bug 5279. 905 let neverHasSideEffects = 1 in 906 def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst), 907 (ins MEMri:$addr), 908 "Error; should not emit", 909 []>, 910 Requires<[HasV4T]>; 911 912 // Rd=memw(Re=#U6) 913 914 // Rd=memw(Rs+Rt<<#u2) 915 let AddedComplexity = 10, isPredicable = 1 in 916 def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst), 917 (ins IntRegs:$src1, IntRegs:$src2), 918 "$dst=memw($src1+$src2<<#0)", 919 [(set (i32 IntRegs:$dst), 920 (i32 (load (add (i32 IntRegs:$src1), 921 (i32 IntRegs:$src2)))))]>, 922 Requires<[HasV4T]>; 923 924 // Rd=memw(Rs+Rt<<#u2) 925 let AddedComplexity = 40, isPredicable = 1 in 926 def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), 927 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), 928 "$dst=memw($src1+$src2<<#$offset)", 929 [(set (i32 IntRegs:$dst), 930 (i32 (load (add (i32 IntRegs:$src1), 931 (shl (i32 IntRegs:$src2), 932 u2ImmPred:$offset)))))]>, 933 Requires<[HasV4T]>; 934 935 //// Load word conditionally. 936 // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2) 937 // if (Pv) Rd=memw(Rs+Rt<<#u2) 938 let AddedComplexity = 15, isPredicated = 1 in 939 def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst), 940 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 941 "if ($src1) $dst=memw($src2+$src3<<#0)", 942 []>, 943 Requires<[HasV4T]>; 944 945 // if (Pv.new) Rd=memh(Rs+Rt<<#u2) 946 let AddedComplexity = 15, isPredicated = 1 in 947 def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 948 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 949 "if ($src1.new) $dst=memw($src2+$src3<<#0)", 950 []>, 951 Requires<[HasV4T]>; 952 953 // if (!Pv) Rd=memh(Rs+Rt<<#u2) 954 let AddedComplexity = 15, isPredicated = 1 in 955 def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 956 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 957 "if (!$src1) $dst=memw($src2+$src3<<#0)", 958 []>, 959 Requires<[HasV4T]>; 960 961 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) 962 let AddedComplexity = 15, isPredicated = 1 in 963 def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 964 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), 965 "if (!$src1.new) $dst=memw($src2+$src3<<#0)", 966 []>, 967 Requires<[HasV4T]>; 968 969 // if (Pv) Rd=memh(Rs+Rt<<#u2) 970 let AddedComplexity = 45, isPredicated = 1 in 971 def LDriw_indexed_shl_cPt_V4 : LDInst2<(outs IntRegs:$dst), 972 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 973 u2Imm:$offset), 974 "if ($src1) $dst=memw($src2+$src3<<#$offset)", 975 []>, 976 Requires<[HasV4T]>; 977 978 // if (Pv.new) Rd=memh(Rs+Rt<<#u2) 979 let AddedComplexity = 45, isPredicated = 1 in 980 def LDriw_indexed_shl_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 981 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 982 u2Imm:$offset), 983 "if ($src1.new) $dst=memw($src2+$src3<<#$offset)", 984 []>, 985 Requires<[HasV4T]>; 986 987 // if (!Pv) Rd=memh(Rs+Rt<<#u2) 988 let AddedComplexity = 45, isPredicated = 1 in 989 def LDriw_indexed_shl_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 990 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 991 u2Imm:$offset), 992 "if (!$src1) $dst=memw($src2+$src3<<#$offset)", 993 []>, 994 Requires<[HasV4T]>; 995 996 // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) 997 let AddedComplexity = 45, isPredicated = 1 in 998 def LDriw_indexed_shl_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 999 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, 1000 u2Imm:$offset), 1001 "if (!$src1.new) $dst=memw($src2+$src3<<#$offset)", 1002 []>, 1003 Requires<[HasV4T]>; 1004 1005 // Rd=memw(Rt<<#u2+#U6) 1006 1007 1008 // Post-inc Load, Predicated, Dot new 1009 1010 1011 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1012 def POST_LDrid_cdnPt_V4 : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2), 1013 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3), 1014 "if ($src1.new) $dst1 = memd($src2++#$src3)", 1015 [], 1016 "$src2 = $dst2">, 1017 Requires<[HasV4T]>; 1018 1019 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1020 def POST_LDrid_cdnNotPt_V4 : LDInst2PI<(outs DoubleRegs:$dst1, IntRegs:$dst2), 1021 (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3), 1022 "if (!$src1.new) $dst1 = memd($src2++#$src3)", 1023 [], 1024 "$src2 = $dst2">, 1025 Requires<[HasV4T]>; 1026 1027 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1028 def POST_LDrib_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1029 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), 1030 "if ($src1.new) $dst1 = memb($src2++#$src3)", 1031 [], 1032 "$src2 = $dst2">, 1033 Requires<[HasV4T]>; 1034 1035 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1036 def POST_LDrib_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1037 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), 1038 "if (!$src1.new) $dst1 = memb($src2++#$src3)", 1039 [], 1040 "$src2 = $dst2">, 1041 Requires<[HasV4T]>; 1042 1043 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1044 def POST_LDrih_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1045 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), 1046 "if ($src1.new) $dst1 = memh($src2++#$src3)", 1047 [], 1048 "$src2 = $dst2">, 1049 Requires<[HasV4T]>; 1050 1051 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1052 def POST_LDrih_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1053 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), 1054 "if (!$src1.new) $dst1 = memh($src2++#$src3)", 1055 [], 1056 "$src2 = $dst2">, 1057 Requires<[HasV4T]>; 1058 1059 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1060 def POST_LDriub_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1061 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), 1062 "if ($src1.new) $dst1 = memub($src2++#$src3)", 1063 [], 1064 "$src2 = $dst2">, 1065 Requires<[HasV4T]>; 1066 1067 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1068 def POST_LDriub_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1069 (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), 1070 "if (!$src1.new) $dst1 = memub($src2++#$src3)", 1071 [], 1072 "$src2 = $dst2">, 1073 Requires<[HasV4T]>; 1074 1075 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1076 def POST_LDriuh_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1077 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), 1078 "if ($src1.new) $dst1 = memuh($src2++#$src3)", 1079 [], 1080 "$src2 = $dst2">, 1081 Requires<[HasV4T]>; 1082 1083 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1084 def POST_LDriuh_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1085 (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), 1086 "if (!$src1.new) $dst1 = memuh($src2++#$src3)", 1087 [], 1088 "$src2 = $dst2">, 1089 Requires<[HasV4T]>; 1090 1091 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1092 def POST_LDriw_cdnPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1093 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3), 1094 "if ($src1.new) $dst1 = memw($src2++#$src3)", 1095 [], 1096 "$src2 = $dst2">, 1097 Requires<[HasV4T]>; 1098 1099 let hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in 1100 def POST_LDriw_cdnNotPt_V4 : LDInst2PI<(outs IntRegs:$dst1, IntRegs:$dst2), 1101 (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3), 1102 "if (!$src1.new) $dst1 = memw($src2++#$src3)", 1103 [], 1104 "$src2 = $dst2">, 1105 Requires<[HasV4T]>; 1106 1107 /// Load from global offset 1108 1109 let isPredicable = 1, neverHasSideEffects = 1 in 1110 def LDrid_GP_V4 : LDInst2<(outs DoubleRegs:$dst), 1111 (ins globaladdress:$global, u16Imm:$offset), 1112 "$dst=memd(#$global+$offset)", 1113 []>, 1114 Requires<[HasV4T]>; 1115 1116 let neverHasSideEffects = 1, isPredicated = 1 in 1117 def LDrid_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1118 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1119 "if ($src1) $dst=memd(##$global+$offset)", 1120 []>, 1121 Requires<[HasV4T]>; 1122 1123 let neverHasSideEffects = 1, isPredicated = 1 in 1124 def LDrid_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1125 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1126 "if (!$src1) $dst=memd(##$global+$offset)", 1127 []>, 1128 Requires<[HasV4T]>; 1129 1130 let neverHasSideEffects = 1, isPredicated = 1 in 1131 def LDrid_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1132 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1133 "if ($src1.new) $dst=memd(##$global+$offset)", 1134 []>, 1135 Requires<[HasV4T]>; 1136 1137 let neverHasSideEffects = 1, isPredicated = 1 in 1138 def LDrid_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1139 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1140 "if (!$src1.new) $dst=memd(##$global+$offset)", 1141 []>, 1142 Requires<[HasV4T]>; 1143 1144 let isPredicable = 1, neverHasSideEffects = 1 in 1145 def LDrib_GP_V4 : LDInst2<(outs IntRegs:$dst), 1146 (ins globaladdress:$global, u16Imm:$offset), 1147 "$dst=memb(#$global+$offset)", 1148 []>, 1149 Requires<[HasV4T]>; 1150 1151 let neverHasSideEffects = 1, isPredicated = 1 in 1152 def LDrib_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1153 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1154 "if ($src1) $dst=memb(##$global+$offset)", 1155 []>, 1156 Requires<[HasV4T]>; 1157 1158 let neverHasSideEffects = 1, isPredicated = 1 in 1159 def LDrib_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1160 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1161 "if (!$src1) $dst=memb(##$global+$offset)", 1162 []>, 1163 Requires<[HasV4T]>; 1164 1165 let neverHasSideEffects = 1, isPredicated = 1 in 1166 def LDrib_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1167 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1168 "if ($src1.new) $dst=memb(##$global+$offset)", 1169 []>, 1170 Requires<[HasV4T]>; 1171 1172 let neverHasSideEffects = 1, isPredicated = 1 in 1173 def LDrib_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1174 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1175 "if (!$src1.new) $dst=memb(##$global+$offset)", 1176 []>, 1177 Requires<[HasV4T]>; 1178 1179 1180 let isPredicable = 1, neverHasSideEffects = 1 in 1181 def LDriub_GP_V4 : LDInst2<(outs IntRegs:$dst), 1182 (ins globaladdress:$global, u16Imm:$offset), 1183 "$dst=memub(#$global+$offset)", 1184 []>, 1185 Requires<[HasV4T]>; 1186 1187 1188 let neverHasSideEffects = 1, isPredicated = 1 in 1189 def LDriub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1190 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1191 "if ($src1) $dst=memub(##$global+$offset)", 1192 []>, 1193 Requires<[HasV4T]>; 1194 1195 let neverHasSideEffects = 1, isPredicated = 1 in 1196 def LDriub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1197 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1198 "if (!$src1) $dst=memub(##$global+$offset)", 1199 []>, 1200 Requires<[HasV4T]>; 1201 1202 let neverHasSideEffects = 1, isPredicated = 1 in 1203 def LDriub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1204 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1205 "if ($src1.new) $dst=memub(##$global+$offset)", 1206 []>, 1207 Requires<[HasV4T]>; 1208 1209 let neverHasSideEffects = 1, isPredicated = 1 in 1210 def LDriub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1211 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1212 "if (!$src1.new) $dst=memub(##$global+$offset)", 1213 []>, 1214 Requires<[HasV4T]>; 1215 1216 1217 let isPredicable = 1, neverHasSideEffects = 1 in 1218 def LDrih_GP_V4 : LDInst2<(outs IntRegs:$dst), 1219 (ins globaladdress:$global, u16Imm:$offset), 1220 "$dst=memh(#$global+$offset)", 1221 []>, 1222 Requires<[HasV4T]>; 1223 1224 1225 let neverHasSideEffects = 1, isPredicated = 1 in 1226 def LDrih_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1227 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1228 "if ($src1) $dst=memh(##$global+$offset)", 1229 []>, 1230 Requires<[HasV4T]>; 1231 1232 let neverHasSideEffects = 1, isPredicated = 1 in 1233 def LDrih_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1234 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1235 "if (!$src1) $dst=memh(##$global+$offset)", 1236 []>, 1237 Requires<[HasV4T]>; 1238 1239 let neverHasSideEffects = 1, isPredicated = 1 in 1240 def LDrih_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1241 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1242 "if ($src1.new) $dst=memh(##$global+$offset)", 1243 []>, 1244 Requires<[HasV4T]>; 1245 1246 let neverHasSideEffects = 1, isPredicated = 1 in 1247 def LDrih_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1248 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1249 "if (!$src1.new) $dst=memh(##$global+$offset)", 1250 []>, 1251 Requires<[HasV4T]>; 1252 1253 1254 let isPredicable = 1, neverHasSideEffects = 1 in 1255 def LDriuh_GP_V4 : LDInst2<(outs IntRegs:$dst), 1256 (ins globaladdress:$global, u16Imm:$offset), 1257 "$dst=memuh(#$global+$offset)", 1258 []>, 1259 Requires<[HasV4T]>; 1260 1261 let neverHasSideEffects = 1, isPredicated = 1 in 1262 def LDriuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1263 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1264 "if ($src1) $dst=memuh(##$global+$offset)", 1265 []>, 1266 Requires<[HasV4T]>; 1267 1268 let neverHasSideEffects = 1, isPredicated = 1 in 1269 def LDriuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1270 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1271 "if (!$src1) $dst=memuh(##$global+$offset)", 1272 []>, 1273 Requires<[HasV4T]>; 1274 1275 let neverHasSideEffects = 1, isPredicated = 1 in 1276 def LDriuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1277 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1278 "if ($src1.new) $dst=memuh(##$global+$offset)", 1279 []>, 1280 Requires<[HasV4T]>; 1281 1282 let neverHasSideEffects = 1, isPredicated = 1 in 1283 def LDriuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1284 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1285 "if (!$src1.new) $dst=memuh(##$global+$offset)", 1286 []>, 1287 Requires<[HasV4T]>; 1288 1289 let isPredicable = 1, neverHasSideEffects = 1 in 1290 def LDriw_GP_V4 : LDInst2<(outs IntRegs:$dst), 1291 (ins globaladdress:$global, u16Imm:$offset), 1292 "$dst=memw(#$global+$offset)", 1293 []>, 1294 Requires<[HasV4T]>; 1295 1296 1297 let neverHasSideEffects = 1, isPredicated = 1 in 1298 def LDriw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1299 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1300 "if ($src1) $dst=memw(##$global+$offset)", 1301 []>, 1302 Requires<[HasV4T]>; 1303 1304 let neverHasSideEffects = 1, isPredicated = 1 in 1305 def LDriw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1306 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1307 "if (!$src1) $dst=memw(##$global+$offset)", 1308 []>, 1309 Requires<[HasV4T]>; 1310 1311 1312 let neverHasSideEffects = 1, isPredicated = 1 in 1313 def LDriw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1314 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1315 "if ($src1.new) $dst=memw(##$global+$offset)", 1316 []>, 1317 Requires<[HasV4T]>; 1318 1319 let neverHasSideEffects = 1, isPredicated = 1 in 1320 def LDriw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1321 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset), 1322 "if (!$src1.new) $dst=memw(##$global+$offset)", 1323 []>, 1324 Requires<[HasV4T]>; 1325 1326 1327 let isPredicable = 1, neverHasSideEffects = 1 in 1328 def LDd_GP_V4 : LDInst2<(outs DoubleRegs:$dst), 1329 (ins globaladdress:$global), 1330 "$dst=memd(#$global)", 1331 []>, 1332 Requires<[HasV4T]>; 1333 1334 // if (Pv) Rtt=memd(##global) 1335 let neverHasSideEffects = 1, isPredicated = 1 in 1336 def LDd_GP_cPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1337 (ins PredRegs:$src1, globaladdress:$global), 1338 "if ($src1) $dst=memd(##$global)", 1339 []>, 1340 Requires<[HasV4T]>; 1341 1342 1343 // if (!Pv) Rtt=memd(##global) 1344 let neverHasSideEffects = 1, isPredicated = 1 in 1345 def LDd_GP_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1346 (ins PredRegs:$src1, globaladdress:$global), 1347 "if (!$src1) $dst=memd(##$global)", 1348 []>, 1349 Requires<[HasV4T]>; 1350 1351 // if (Pv) Rtt=memd(##global) 1352 let neverHasSideEffects = 1, isPredicated = 1 in 1353 def LDd_GP_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1354 (ins PredRegs:$src1, globaladdress:$global), 1355 "if ($src1.new) $dst=memd(##$global)", 1356 []>, 1357 Requires<[HasV4T]>; 1358 1359 1360 // if (!Pv) Rtt=memd(##global) 1361 let neverHasSideEffects = 1, isPredicated = 1 in 1362 def LDd_GP_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 1363 (ins PredRegs:$src1, globaladdress:$global), 1364 "if (!$src1.new) $dst=memd(##$global)", 1365 []>, 1366 Requires<[HasV4T]>; 1367 1368 let isPredicable = 1, neverHasSideEffects = 1 in 1369 def LDb_GP_V4 : LDInst2<(outs IntRegs:$dst), 1370 (ins globaladdress:$global), 1371 "$dst=memb(#$global)", 1372 []>, 1373 Requires<[HasV4T]>; 1374 1375 // if (Pv) Rt=memb(##global) 1376 let neverHasSideEffects = 1, isPredicated = 1 in 1377 def LDb_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1378 (ins PredRegs:$src1, globaladdress:$global), 1379 "if ($src1) $dst=memb(##$global)", 1380 []>, 1381 Requires<[HasV4T]>; 1382 1383 // if (!Pv) Rt=memb(##global) 1384 let neverHasSideEffects = 1, isPredicated = 1 in 1385 def LDb_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1386 (ins PredRegs:$src1, globaladdress:$global), 1387 "if (!$src1) $dst=memb(##$global)", 1388 []>, 1389 Requires<[HasV4T]>; 1390 1391 // if (Pv) Rt=memb(##global) 1392 let neverHasSideEffects = 1, isPredicated = 1 in 1393 def LDb_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1394 (ins PredRegs:$src1, globaladdress:$global), 1395 "if ($src1.new) $dst=memb(##$global)", 1396 []>, 1397 Requires<[HasV4T]>; 1398 1399 // if (!Pv) Rt=memb(##global) 1400 let neverHasSideEffects = 1, isPredicated = 1 in 1401 def LDb_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1402 (ins PredRegs:$src1, globaladdress:$global), 1403 "if (!$src1.new) $dst=memb(##$global)", 1404 []>, 1405 Requires<[HasV4T]>; 1406 1407 let isPredicable = 1, neverHasSideEffects = 1 in 1408 def LDub_GP_V4 : LDInst2<(outs IntRegs:$dst), 1409 (ins globaladdress:$global), 1410 "$dst=memub(#$global)", 1411 []>, 1412 Requires<[HasV4T]>; 1413 1414 // if (Pv) Rt=memub(##global) 1415 let neverHasSideEffects = 1, isPredicated = 1 in 1416 def LDub_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1417 (ins PredRegs:$src1, globaladdress:$global), 1418 "if ($src1) $dst=memub(##$global)", 1419 []>, 1420 Requires<[HasV4T]>; 1421 1422 1423 // if (!Pv) Rt=memub(##global) 1424 let neverHasSideEffects = 1, isPredicated = 1 in 1425 def LDub_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1426 (ins PredRegs:$src1, globaladdress:$global), 1427 "if (!$src1) $dst=memub(##$global)", 1428 []>, 1429 Requires<[HasV4T]>; 1430 1431 // if (Pv) Rt=memub(##global) 1432 let neverHasSideEffects = 1, isPredicated = 1 in 1433 def LDub_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1434 (ins PredRegs:$src1, globaladdress:$global), 1435 "if ($src1.new) $dst=memub(##$global)", 1436 []>, 1437 Requires<[HasV4T]>; 1438 1439 1440 // if (!Pv) Rt=memub(##global) 1441 let neverHasSideEffects = 1, isPredicated = 1 in 1442 def LDub_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1443 (ins PredRegs:$src1, globaladdress:$global), 1444 "if (!$src1.new) $dst=memub(##$global)", 1445 []>, 1446 Requires<[HasV4T]>; 1447 1448 let isPredicable = 1, neverHasSideEffects = 1 in 1449 def LDh_GP_V4 : LDInst2<(outs IntRegs:$dst), 1450 (ins globaladdress:$global), 1451 "$dst=memh(#$global)", 1452 []>, 1453 Requires<[HasV4T]>; 1454 1455 // if (Pv) Rt=memh(##global) 1456 let neverHasSideEffects = 1, isPredicated = 1 in 1457 def LDh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1458 (ins PredRegs:$src1, globaladdress:$global), 1459 "if ($src1) $dst=memh(##$global)", 1460 []>, 1461 Requires<[HasV4T]>; 1462 1463 // if (!Pv) Rt=memh(##global) 1464 let neverHasSideEffects = 1, isPredicated = 1 in 1465 def LDh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1466 (ins PredRegs:$src1, globaladdress:$global), 1467 "if (!$src1) $dst=memh(##$global)", 1468 []>, 1469 Requires<[HasV4T]>; 1470 1471 // if (Pv) Rt=memh(##global) 1472 let neverHasSideEffects = 1, isPredicated = 1 in 1473 def LDh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1474 (ins PredRegs:$src1, globaladdress:$global), 1475 "if ($src1.new) $dst=memh(##$global)", 1476 []>, 1477 Requires<[HasV4T]>; 1478 1479 // if (!Pv) Rt=memh(##global) 1480 let neverHasSideEffects = 1, isPredicated = 1 in 1481 def LDh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1482 (ins PredRegs:$src1, globaladdress:$global), 1483 "if (!$src1.new) $dst=memh(##$global)", 1484 []>, 1485 Requires<[HasV4T]>; 1486 1487 let isPredicable = 1, neverHasSideEffects = 1 in 1488 def LDuh_GP_V4 : LDInst2<(outs IntRegs:$dst), 1489 (ins globaladdress:$global), 1490 "$dst=memuh(#$global)", 1491 []>, 1492 Requires<[HasV4T]>; 1493 1494 // if (Pv) Rt=memuh(##global) 1495 let neverHasSideEffects = 1, isPredicated = 1 in 1496 def LDuh_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1497 (ins PredRegs:$src1, globaladdress:$global), 1498 "if ($src1) $dst=memuh(##$global)", 1499 []>, 1500 Requires<[HasV4T]>; 1501 1502 // if (!Pv) Rt=memuh(##global) 1503 let neverHasSideEffects = 1, isPredicated = 1 in 1504 def LDuh_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1505 (ins PredRegs:$src1, globaladdress:$global), 1506 "if (!$src1) $dst=memuh(##$global)", 1507 []>, 1508 Requires<[HasV4T]>; 1509 1510 // if (Pv) Rt=memuh(##global) 1511 let neverHasSideEffects = 1, isPredicated = 1 in 1512 def LDuh_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1513 (ins PredRegs:$src1, globaladdress:$global), 1514 "if ($src1.new) $dst=memuh(##$global)", 1515 []>, 1516 Requires<[HasV4T]>; 1517 1518 // if (!Pv) Rt=memuh(##global) 1519 let neverHasSideEffects = 1, isPredicated = 1 in 1520 def LDuh_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1521 (ins PredRegs:$src1, globaladdress:$global), 1522 "if (!$src1.new) $dst=memuh(##$global)", 1523 []>, 1524 Requires<[HasV4T]>; 1525 1526 let isPredicable = 1, neverHasSideEffects = 1 in 1527 def LDw_GP_V4 : LDInst2<(outs IntRegs:$dst), 1528 (ins globaladdress:$global), 1529 "$dst=memw(#$global)", 1530 []>, 1531 Requires<[HasV4T]>; 1532 1533 // if (Pv) Rt=memw(##global) 1534 let neverHasSideEffects = 1, isPredicated = 1 in 1535 def LDw_GP_cPt_V4 : LDInst2<(outs IntRegs:$dst), 1536 (ins PredRegs:$src1, globaladdress:$global), 1537 "if ($src1) $dst=memw(##$global)", 1538 []>, 1539 Requires<[HasV4T]>; 1540 1541 1542 // if (!Pv) Rt=memw(##global) 1543 let neverHasSideEffects = 1, isPredicated = 1 in 1544 def LDw_GP_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1545 (ins PredRegs:$src1, globaladdress:$global), 1546 "if (!$src1) $dst=memw(##$global)", 1547 []>, 1548 Requires<[HasV4T]>; 1549 1550 // if (Pv) Rt=memw(##global) 1551 let neverHasSideEffects = 1, isPredicated = 1 in 1552 def LDw_GP_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 1553 (ins PredRegs:$src1, globaladdress:$global), 1554 "if ($src1.new) $dst=memw(##$global)", 1555 []>, 1556 Requires<[HasV4T]>; 1557 1558 1559 // if (!Pv) Rt=memw(##global) 1560 let neverHasSideEffects = 1, isPredicated = 1 in 1561 def LDw_GP_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 1562 (ins PredRegs:$src1, globaladdress:$global), 1563 "if (!$src1.new) $dst=memw(##$global)", 1564 []>, 1565 Requires<[HasV4T]>; 1566 1567 1568 1569 def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)), 1570 (i64 (LDd_GP_V4 tglobaladdr:$global))>, 1571 Requires<[HasV4T]>; 1572 1573 def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)), 1574 (i32 (LDw_GP_V4 tglobaladdr:$global))>, 1575 Requires<[HasV4T]>; 1576 1577 def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)), 1578 (i32 (LDuh_GP_V4 tglobaladdr:$global))>, 1579 Requires<[HasV4T]>; 1580 1581 def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)), 1582 (i32 (LDub_GP_V4 tglobaladdr:$global))>, 1583 Requires<[HasV4T]>; 1584 1585 // Map from load(globaladdress) -> memw(#foo + 0) 1586 let AddedComplexity = 100 in 1587 def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))), 1588 (i64 (LDd_GP_V4 tglobaladdr:$global))>, 1589 Requires<[HasV4T]>; 1590 1591 // Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd 1592 let AddedComplexity = 100 in 1593 def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))), 1594 (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>, 1595 Requires<[HasV4T]>; 1596 1597 // When the Interprocedural Global Variable optimizer realizes that a certain 1598 // global variable takes only two constant values, it shrinks the global to 1599 // a boolean. Catch those loads here in the following 3 patterns. 1600 let AddedComplexity = 100 in 1601 def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))), 1602 (i32 (LDb_GP_V4 tglobaladdr:$global))>, 1603 Requires<[HasV4T]>; 1604 1605 let AddedComplexity = 100 in 1606 def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))), 1607 (i32 (LDb_GP_V4 tglobaladdr:$global))>, 1608 Requires<[HasV4T]>; 1609 1610 // Map from load(globaladdress) -> memb(#foo) 1611 let AddedComplexity = 100 in 1612 def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))), 1613 (i32 (LDb_GP_V4 tglobaladdr:$global))>, 1614 Requires<[HasV4T]>; 1615 1616 // Map from load(globaladdress) -> memb(#foo) 1617 let AddedComplexity = 100 in 1618 def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))), 1619 (i32 (LDb_GP_V4 tglobaladdr:$global))>, 1620 Requires<[HasV4T]>; 1621 1622 let AddedComplexity = 100 in 1623 def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))), 1624 (i32 (LDub_GP_V4 tglobaladdr:$global))>, 1625 Requires<[HasV4T]>; 1626 1627 // Map from load(globaladdress) -> memub(#foo) 1628 let AddedComplexity = 100 in 1629 def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))), 1630 (i32 (LDub_GP_V4 tglobaladdr:$global))>, 1631 Requires<[HasV4T]>; 1632 1633 // Map from load(globaladdress) -> memh(#foo) 1634 let AddedComplexity = 100 in 1635 def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))), 1636 (i32 (LDh_GP_V4 tglobaladdr:$global))>, 1637 Requires<[HasV4T]>; 1638 1639 // Map from load(globaladdress) -> memh(#foo) 1640 let AddedComplexity = 100 in 1641 def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))), 1642 (i32 (LDh_GP_V4 tglobaladdr:$global))>, 1643 Requires<[HasV4T]>; 1644 1645 // Map from load(globaladdress) -> memuh(#foo) 1646 let AddedComplexity = 100 in 1647 def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))), 1648 (i32 (LDuh_GP_V4 tglobaladdr:$global))>, 1649 Requires<[HasV4T]>; 1650 1651 // Map from load(globaladdress) -> memw(#foo) 1652 let AddedComplexity = 100 in 1653 def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))), 1654 (i32 (LDw_GP_V4 tglobaladdr:$global))>, 1655 Requires<[HasV4T]>; 1656 1657 def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global), 1658 u16ImmPred:$offset)), 1659 (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1660 Requires<[HasV4T]>; 1661 1662 def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global), 1663 u16ImmPred:$offset)), 1664 (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1665 Requires<[HasV4T]>; 1666 1667 def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global), 1668 u16ImmPred:$offset)), 1669 (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1670 Requires<[HasV4T]>; 1671 1672 def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global), 1673 u16ImmPred:$offset)), 1674 (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1675 Requires<[HasV4T]>; 1676 1677 // Map from load(globaladdress + x) -> memd(#foo + x) 1678 let AddedComplexity = 100 in 1679 def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global), 1680 u16ImmPred:$offset))), 1681 (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1682 Requires<[HasV4T]>; 1683 1684 // Map from load(globaladdress + x) -> memb(#foo + x) 1685 let AddedComplexity = 100 in 1686 def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global), 1687 u16ImmPred:$offset))), 1688 (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1689 Requires<[HasV4T]>; 1690 1691 // Map from load(globaladdress + x) -> memb(#foo + x) 1692 let AddedComplexity = 100 in 1693 def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global), 1694 u16ImmPred:$offset))), 1695 (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1696 Requires<[HasV4T]>; 1697 1698 // Map from load(globaladdress + x) -> memub(#foo + x) 1699 let AddedComplexity = 100 in 1700 def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global), 1701 u16ImmPred:$offset))), 1702 (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1703 Requires<[HasV4T]>; 1704 1705 // Map from load(globaladdress + x) -> memuh(#foo + x) 1706 let AddedComplexity = 100 in 1707 def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global), 1708 u16ImmPred:$offset))), 1709 (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1710 Requires<[HasV4T]>; 1711 1712 // Map from load(globaladdress + x) -> memh(#foo + x) 1713 let AddedComplexity = 100 in 1714 def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global), 1715 u16ImmPred:$offset))), 1716 (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1717 Requires<[HasV4T]>; 1718 1719 1720 // Map from load(globaladdress + x) -> memuh(#foo + x) 1721 let AddedComplexity = 100 in 1722 def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global), 1723 u16ImmPred:$offset))), 1724 (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1725 Requires<[HasV4T]>; 1726 1727 // Map from load(globaladdress + x) -> memw(#foo + x) 1728 let AddedComplexity = 100 in 1729 def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global), 1730 u16ImmPred:$offset))), 1731 (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>, 1732 Requires<[HasV4T]>; 1733 1734 1735 //===----------------------------------------------------------------------===// 1736 // LD - 1737 //===----------------------------------------------------------------------===// 1738 1739 //===----------------------------------------------------------------------===// 1740 // ST + 1741 //===----------------------------------------------------------------------===// 1742 /// 1743 /// Assumptions::: ****** DO NOT IGNORE ******** 1744 /// 1. Make sure that in post increment store, the zero'th operand is always the 1745 /// post increment operand. 1746 /// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the 1747 /// last operand. 1748 /// 1749 1750 // memd(Re=#U6)=Rtt 1751 def STrid_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1), 1752 (ins DoubleRegs:$src1, u6Imm:$src2), 1753 "memd($dst1=#$src2) = $src1", 1754 []>, 1755 Requires<[HasV4T]>; 1756 1757 // memb(Re=#U6)=Rs 1758 def STrib_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1), 1759 (ins IntRegs:$src1, u6Imm:$src2), 1760 "memb($dst1=#$src2) = $src1", 1761 []>, 1762 Requires<[HasV4T]>; 1763 1764 // memh(Re=#U6)=Rs 1765 def STrih_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1), 1766 (ins IntRegs:$src1, u6Imm:$src2), 1767 "memh($dst1=#$src2) = $src1", 1768 []>, 1769 Requires<[HasV4T]>; 1770 1771 // memw(Re=#U6)=Rs 1772 def STriw_abs_setimm_V4 : STInst2<(outs IntRegs:$dst1), 1773 (ins IntRegs:$src1, u6Imm:$src2), 1774 "memw($dst1=#$src2) = $src1", 1775 []>, 1776 Requires<[HasV4T]>; 1777 1778 // memd(Re=#U6)=Rtt 1779 def STrid_abs_set_V4 : STInst2<(outs IntRegs:$dst1), 1780 (ins DoubleRegs:$src1, globaladdress:$src2), 1781 "memd($dst1=##$src2) = $src1", 1782 []>, 1783 Requires<[HasV4T]>; 1784 1785 // memb(Re=#U6)=Rs 1786 def STrib_abs_set_V4 : STInst2<(outs IntRegs:$dst1), 1787 (ins IntRegs:$src1, globaladdress:$src2), 1788 "memb($dst1=##$src2) = $src1", 1789 []>, 1790 Requires<[HasV4T]>; 1791 1792 // memh(Re=#U6)=Rs 1793 def STrih_abs_set_V4 : STInst2<(outs IntRegs:$dst1), 1794 (ins IntRegs:$src1, globaladdress:$src2), 1795 "memh($dst1=##$src2) = $src1", 1796 []>, 1797 Requires<[HasV4T]>; 1798 1799 // memw(Re=#U6)=Rs 1800 def STriw_abs_set_V4 : STInst2<(outs IntRegs:$dst1), 1801 (ins IntRegs:$src1, globaladdress:$src2), 1802 "memw($dst1=##$src2) = $src1", 1803 []>, 1804 Requires<[HasV4T]>; 1805 1806 // memd(Rs+Ru<<#u2)=Rtt 1807 let AddedComplexity = 10, isPredicable = 1 in 1808 def STrid_indexed_shl_V4 : STInst<(outs), 1809 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4), 1810 "memd($src1+$src2<<#$src3) = $src4", 1811 [(store (i64 DoubleRegs:$src4), 1812 (add (i32 IntRegs:$src1), 1813 (shl (i32 IntRegs:$src2), u2ImmPred:$src3)))]>, 1814 Requires<[HasV4T]>; 1815 1816 // memd(Ru<<#u2+#U6)=Rtt 1817 let AddedComplexity = 10 in 1818 def STrid_shl_V4 : STInst<(outs), 1819 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4), 1820 "memd($src1<<#$src2+#$src3) = $src4", 1821 [(store (i64 DoubleRegs:$src4), 1822 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2), 1823 u6ImmPred:$src3))]>, 1824 Requires<[HasV4T]>; 1825 1826 // memd(Rx++#s4:3)=Rtt 1827 // memd(Rx++#s4:3:circ(Mu))=Rtt 1828 // memd(Rx++I:circ(Mu))=Rtt 1829 // memd(Rx++Mu)=Rtt 1830 // memd(Rx++Mu:brev)=Rtt 1831 // memd(gp+#u16:3)=Rtt 1832 1833 // Store doubleword conditionally. 1834 // if ([!]Pv[.new]) memd(#u6)=Rtt 1835 // TODO: needs to be implemented. 1836 1837 // if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt 1838 // if (Pv) memd(Rs+#u6:3)=Rtt 1839 // if (Pv.new) memd(Rs+#u6:3)=Rtt 1840 let AddedComplexity = 10, neverHasSideEffects = 1, 1841 isPredicated = 1 in 1842 def STrid_cdnPt_V4 : STInst2<(outs), 1843 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2), 1844 "if ($src1.new) memd($addr) = $src2", 1845 []>, 1846 Requires<[HasV4T]>; 1847 1848 // if (!Pv) memd(Rs+#u6:3)=Rtt 1849 // if (!Pv.new) memd(Rs+#u6:3)=Rtt 1850 let AddedComplexity = 10, neverHasSideEffects = 1, 1851 isPredicated = 1 in 1852 def STrid_cdnNotPt_V4 : STInst2<(outs), 1853 (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2), 1854 "if (!$src1.new) memd($addr) = $src2", 1855 []>, 1856 Requires<[HasV4T]>; 1857 1858 // if (Pv) memd(Rs+#u6:3)=Rtt 1859 // if (Pv.new) memd(Rs+#u6:3)=Rtt 1860 let AddedComplexity = 10, neverHasSideEffects = 1, 1861 isPredicated = 1 in 1862 def STrid_indexed_cdnPt_V4 : STInst2<(outs), 1863 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3, 1864 DoubleRegs:$src4), 1865 "if ($src1.new) memd($src2+#$src3) = $src4", 1866 []>, 1867 Requires<[HasV4T]>; 1868 1869 // if (!Pv) memd(Rs+#u6:3)=Rtt 1870 // if (!Pv.new) memd(Rs+#u6:3)=Rtt 1871 let AddedComplexity = 10, neverHasSideEffects = 1, 1872 isPredicated = 1 in 1873 def STrid_indexed_cdnNotPt_V4 : STInst2<(outs), 1874 (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3, 1875 DoubleRegs:$src4), 1876 "if (!$src1.new) memd($src2+#$src3) = $src4", 1877 []>, 1878 Requires<[HasV4T]>; 1879 1880 // if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt 1881 // if (Pv) memd(Rs+Ru<<#u2)=Rtt 1882 let AddedComplexity = 10, neverHasSideEffects = 1, 1883 isPredicated = 1 in 1884 def STrid_indexed_shl_cPt_V4 : STInst2<(outs), 1885 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 1886 DoubleRegs:$src5), 1887 "if ($src1) memd($src2+$src3<<#$src4) = $src5", 1888 []>, 1889 Requires<[HasV4T]>; 1890 1891 // if (Pv.new) memd(Rs+Ru<<#u2)=Rtt 1892 let AddedComplexity = 10, neverHasSideEffects = 1, 1893 isPredicated = 1 in 1894 def STrid_indexed_shl_cdnPt_V4 : STInst2<(outs), 1895 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 1896 DoubleRegs:$src5), 1897 "if ($src1.new) memd($src2+$src3<<#$src4) = $src5", 1898 []>, 1899 Requires<[HasV4T]>; 1900 // if (!Pv) memd(Rs+Ru<<#u2)=Rtt 1901 let AddedComplexity = 10, neverHasSideEffects = 1, 1902 isPredicated = 1 in 1903 def STrid_indexed_shl_cNotPt_V4 : STInst2<(outs), 1904 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 1905 DoubleRegs:$src5), 1906 "if (!$src1) memd($src2+$src3<<#$src4) = $src5", 1907 []>, 1908 Requires<[HasV4T]>; 1909 // if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt 1910 let AddedComplexity = 10, neverHasSideEffects = 1, 1911 isPredicated = 1 in 1912 def STrid_indexed_shl_cdnNotPt_V4 : STInst2<(outs), 1913 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 1914 DoubleRegs:$src5), 1915 "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5", 1916 []>, 1917 Requires<[HasV4T]>; 1918 1919 // if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt 1920 // if (Pv) memd(Rx++#s4:3)=Rtt 1921 // if (Pv.new) memd(Rx++#s4:3)=Rtt 1922 let AddedComplexity = 10, neverHasSideEffects = 1, 1923 isPredicated = 1 in 1924 def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst), 1925 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, 1926 s4_3Imm:$offset), 1927 "if ($src1.new) memd($src3++#$offset) = $src2", 1928 [], 1929 "$src3 = $dst">, 1930 Requires<[HasV4T]>; 1931 1932 // if (!Pv) memd(Rx++#s4:3)=Rtt 1933 // if (!Pv.new) memd(Rx++#s4:3)=Rtt 1934 let AddedComplexity = 10, neverHasSideEffects = 1, 1935 isPredicated = 1 in 1936 def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst), 1937 (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, 1938 s4_3Imm:$offset), 1939 "if (!$src1.new) memd($src3++#$offset) = $src2", 1940 [], 1941 "$src3 = $dst">, 1942 Requires<[HasV4T]>; 1943 1944 1945 // Store byte. 1946 // memb(Rs+#u6:0)=#S8 1947 let AddedComplexity = 10, isPredicable = 1 in 1948 def STrib_imm_V4 : STInst<(outs), 1949 (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3), 1950 "memb($src1+#$src2) = #$src3", 1951 [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1), 1952 u6_0ImmPred:$src2))]>, 1953 Requires<[HasV4T]>; 1954 1955 // memb(Rs+Ru<<#u2)=Rt 1956 let AddedComplexity = 10, isPredicable = 1 in 1957 def STrib_indexed_shl_V4 : STInst<(outs), 1958 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4), 1959 "memb($src1+$src2<<#$src3) = $src4", 1960 [(truncstorei8 (i32 IntRegs:$src4), 1961 (add (i32 IntRegs:$src1), 1962 (shl (i32 IntRegs:$src2), 1963 u2ImmPred:$src3)))]>, 1964 Requires<[HasV4T]>; 1965 1966 // memb(Ru<<#u2+#U6)=Rt 1967 let AddedComplexity = 10 in 1968 def STrib_shl_V4 : STInst<(outs), 1969 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4), 1970 "memb($src1<<#$src2+#$src3) = $src4", 1971 [(truncstorei8 (i32 IntRegs:$src4), 1972 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2), 1973 u6ImmPred:$src3))]>, 1974 Requires<[HasV4T]>; 1975 1976 // memb(Rx++#s4:0:circ(Mu))=Rt 1977 // memb(Rx++I:circ(Mu))=Rt 1978 // memb(Rx++Mu)=Rt 1979 // memb(Rx++Mu:brev)=Rt 1980 // memb(gp+#u16:0)=Rt 1981 1982 1983 // Store byte conditionally. 1984 // if ([!]Pv[.new]) memb(#u6)=Rt 1985 // if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6 1986 // if (Pv) memb(Rs+#u6:0)=#S6 1987 let neverHasSideEffects = 1, 1988 isPredicated = 1 in 1989 def STrib_imm_cPt_V4 : STInst2<(outs), 1990 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4), 1991 "if ($src1) memb($src2+#$src3) = #$src4", 1992 []>, 1993 Requires<[HasV4T]>; 1994 1995 // if (Pv.new) memb(Rs+#u6:0)=#S6 1996 let neverHasSideEffects = 1, 1997 isPredicated = 1 in 1998 def STrib_imm_cdnPt_V4 : STInst2<(outs), 1999 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4), 2000 "if ($src1.new) memb($src2+#$src3) = #$src4", 2001 []>, 2002 Requires<[HasV4T]>; 2003 2004 // if (!Pv) memb(Rs+#u6:0)=#S6 2005 let neverHasSideEffects = 1, 2006 isPredicated = 1 in 2007 def STrib_imm_cNotPt_V4 : STInst2<(outs), 2008 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4), 2009 "if (!$src1) memb($src2+#$src3) = #$src4", 2010 []>, 2011 Requires<[HasV4T]>; 2012 2013 // if (!Pv.new) memb(Rs+#u6:0)=#S6 2014 let neverHasSideEffects = 1, 2015 isPredicated = 1 in 2016 def STrib_imm_cdnNotPt_V4 : STInst2<(outs), 2017 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4), 2018 "if (!$src1.new) memb($src2+#$src3) = #$src4", 2019 []>, 2020 Requires<[HasV4T]>; 2021 2022 // if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt 2023 // if (Pv) memb(Rs+#u6:0)=Rt 2024 // if (Pv.new) memb(Rs+#u6:0)=Rt 2025 let neverHasSideEffects = 1, 2026 isPredicated = 1 in 2027 def STrib_cdnPt_V4 : STInst2<(outs), 2028 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 2029 "if ($src1.new) memb($addr) = $src2", 2030 []>, 2031 Requires<[HasV4T]>; 2032 2033 // if (!Pv) memb(Rs+#u6:0)=Rt 2034 // if (!Pv.new) memb(Rs+#u6:0)=Rt 2035 let neverHasSideEffects = 1, 2036 isPredicated = 1 in 2037 def STrib_cdnNotPt_V4 : STInst2<(outs), 2038 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 2039 "if (!$src1.new) memb($addr) = $src2", 2040 []>, 2041 Requires<[HasV4T]>; 2042 2043 // if (Pv) memb(Rs+#u6:0)=Rt 2044 // if (!Pv) memb(Rs+#u6:0)=Rt 2045 // if (Pv.new) memb(Rs+#u6:0)=Rt 2046 let neverHasSideEffects = 1, 2047 isPredicated = 1 in 2048 def STrib_indexed_cdnPt_V4 : STInst2<(outs), 2049 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4), 2050 "if ($src1.new) memb($src2+#$src3) = $src4", 2051 []>, 2052 Requires<[HasV4T]>; 2053 2054 // if (!Pv.new) memb(Rs+#u6:0)=Rt 2055 let neverHasSideEffects = 1, 2056 isPredicated = 1 in 2057 def STrib_indexed_cdnNotPt_V4 : STInst2<(outs), 2058 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4), 2059 "if (!$src1.new) memb($src2+#$src3) = $src4", 2060 []>, 2061 Requires<[HasV4T]>; 2062 2063 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt 2064 // if (Pv) memb(Rs+Ru<<#u2)=Rt 2065 let AddedComplexity = 10, 2066 isPredicated = 1 in 2067 def STrib_indexed_shl_cPt_V4 : STInst2<(outs), 2068 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2069 IntRegs:$src5), 2070 "if ($src1) memb($src2+$src3<<#$src4) = $src5", 2071 []>, 2072 Requires<[HasV4T]>; 2073 2074 // if (Pv.new) memb(Rs+Ru<<#u2)=Rt 2075 let AddedComplexity = 10, 2076 isPredicated = 1 in 2077 def STrib_indexed_shl_cdnPt_V4 : STInst2<(outs), 2078 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2079 IntRegs:$src5), 2080 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5", 2081 []>, 2082 Requires<[HasV4T]>; 2083 2084 // if (!Pv) memb(Rs+Ru<<#u2)=Rt 2085 let AddedComplexity = 10, 2086 isPredicated = 1 in 2087 def STrib_indexed_shl_cNotPt_V4 : STInst2<(outs), 2088 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2089 IntRegs:$src5), 2090 "if (!$src1) memb($src2+$src3<<#$src4) = $src5", 2091 []>, 2092 Requires<[HasV4T]>; 2093 2094 // if (!Pv.new) memb(Rs+Ru<<#u2)=Rt 2095 let AddedComplexity = 10, 2096 isPredicated = 1 in 2097 def STrib_indexed_shl_cdnNotPt_V4 : STInst2<(outs), 2098 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2099 IntRegs:$src5), 2100 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5", 2101 []>, 2102 Requires<[HasV4T]>; 2103 2104 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt 2105 // if (Pv) memb(Rx++#s4:0)=Rt 2106 // if (Pv.new) memb(Rx++#s4:0)=Rt 2107 let hasCtrlDep = 1, 2108 isPredicated = 1 in 2109 def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst), 2110 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), 2111 "if ($src1.new) memb($src3++#$offset) = $src2", 2112 [],"$src3 = $dst">, 2113 Requires<[HasV4T]>; 2114 2115 // if (!Pv) memb(Rx++#s4:0)=Rt 2116 // if (!Pv.new) memb(Rx++#s4:0)=Rt 2117 let hasCtrlDep = 1, 2118 isPredicated = 1 in 2119 def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst), 2120 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), 2121 "if (!$src1.new) memb($src3++#$offset) = $src2", 2122 [],"$src3 = $dst">, 2123 Requires<[HasV4T]>; 2124 2125 2126 // Store halfword. 2127 // TODO: needs to be implemented 2128 // memh(Re=#U6)=Rt.H 2129 // memh(Rs+#s11:1)=Rt.H 2130 // memh(Rs+#u6:1)=#S8 2131 let AddedComplexity = 10, isPredicable = 1 in 2132 def STrih_imm_V4 : STInst<(outs), 2133 (ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3), 2134 "memh($src1+#$src2) = #$src3", 2135 [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1), 2136 u6_1ImmPred:$src2))]>, 2137 Requires<[HasV4T]>; 2138 2139 // memh(Rs+Ru<<#u2)=Rt.H 2140 // TODO: needs to be implemented. 2141 2142 // memh(Rs+Ru<<#u2)=Rt 2143 let AddedComplexity = 10, isPredicable = 1 in 2144 def STrih_indexed_shl_V4 : STInst<(outs), 2145 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4), 2146 "memh($src1+$src2<<#$src3) = $src4", 2147 [(truncstorei16 (i32 IntRegs:$src4), 2148 (add (i32 IntRegs:$src1), 2149 (shl (i32 IntRegs:$src2), 2150 u2ImmPred:$src3)))]>, 2151 Requires<[HasV4T]>; 2152 2153 // memh(Ru<<#u2+#U6)=Rt.H 2154 // memh(Ru<<#u2+#U6)=Rt 2155 let AddedComplexity = 10 in 2156 def STrih_shl_V4 : STInst<(outs), 2157 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4), 2158 "memh($src1<<#$src2+#$src3) = $src4", 2159 [(truncstorei16 (i32 IntRegs:$src4), 2160 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2), 2161 u6ImmPred:$src3))]>, 2162 Requires<[HasV4T]>; 2163 2164 // memh(Rx++#s4:1:circ(Mu))=Rt.H 2165 // memh(Rx++#s4:1:circ(Mu))=Rt 2166 // memh(Rx++I:circ(Mu))=Rt.H 2167 // memh(Rx++I:circ(Mu))=Rt 2168 // memh(Rx++Mu)=Rt.H 2169 // memh(Rx++Mu)=Rt 2170 // memh(Rx++Mu:brev)=Rt.H 2171 // memh(Rx++Mu:brev)=Rt 2172 // memh(gp+#u16:1)=Rt 2173 // if ([!]Pv[.new]) memh(#u6)=Rt.H 2174 // if ([!]Pv[.new]) memh(#u6)=Rt 2175 2176 // if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6 2177 // if (Pv) memh(Rs+#u6:1)=#S6 2178 let neverHasSideEffects = 1, 2179 isPredicated = 1 in 2180 def STrih_imm_cPt_V4 : STInst2<(outs), 2181 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4), 2182 "if ($src1) memh($src2+#$src3) = #$src4", 2183 []>, 2184 Requires<[HasV4T]>; 2185 2186 // if (Pv.new) memh(Rs+#u6:1)=#S6 2187 let neverHasSideEffects = 1, 2188 isPredicated = 1 in 2189 def STrih_imm_cdnPt_V4 : STInst2<(outs), 2190 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4), 2191 "if ($src1.new) memh($src2+#$src3) = #$src4", 2192 []>, 2193 Requires<[HasV4T]>; 2194 2195 // if (!Pv) memh(Rs+#u6:1)=#S6 2196 let neverHasSideEffects = 1, 2197 isPredicated = 1 in 2198 def STrih_imm_cNotPt_V4 : STInst2<(outs), 2199 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4), 2200 "if (!$src1) memh($src2+#$src3) = #$src4", 2201 []>, 2202 Requires<[HasV4T]>; 2203 2204 // if (!Pv.new) memh(Rs+#u6:1)=#S6 2205 let neverHasSideEffects = 1, 2206 isPredicated = 1 in 2207 def STrih_imm_cdnNotPt_V4 : STInst2<(outs), 2208 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4), 2209 "if (!$src1.new) memh($src2+#$src3) = #$src4", 2210 []>, 2211 Requires<[HasV4T]>; 2212 2213 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt.H 2214 // TODO: needs to be implemented. 2215 2216 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt 2217 // if (Pv) memh(Rs+#u6:1)=Rt 2218 // if (Pv.new) memh(Rs+#u6:1)=Rt 2219 let neverHasSideEffects = 1, 2220 isPredicated = 1 in 2221 def STrih_cdnPt_V4 : STInst2<(outs), 2222 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 2223 "if ($src1.new) memh($addr) = $src2", 2224 []>, 2225 Requires<[HasV4T]>; 2226 2227 // if (!Pv) memh(Rs+#u6:1)=Rt 2228 // if (!Pv.new) memh(Rs+#u6:1)=Rt 2229 let neverHasSideEffects = 1, 2230 isPredicated = 1 in 2231 def STrih_cdnNotPt_V4 : STInst2<(outs), 2232 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 2233 "if (!$src1.new) memh($addr) = $src2", 2234 []>, 2235 Requires<[HasV4T]>; 2236 2237 // if (Pv.new) memh(Rs+#u6:1)=Rt 2238 let neverHasSideEffects = 1, 2239 isPredicated = 1 in 2240 def STrih_indexed_cdnPt_V4 : STInst2<(outs), 2241 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4), 2242 "if ($src1.new) memh($src2+#$src3) = $src4", 2243 []>, 2244 Requires<[HasV4T]>; 2245 2246 // if (!Pv.new) memh(Rs+#u6:1)=Rt 2247 let neverHasSideEffects = 1, 2248 isPredicated = 1 in 2249 def STrih_indexed_cdnNotPt_V4 : STInst2<(outs), 2250 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4), 2251 "if (!$src1.new) memh($src2+#$src3) = $src4", 2252 []>, 2253 Requires<[HasV4T]>; 2254 2255 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H 2256 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt 2257 // if (Pv) memh(Rs+Ru<<#u2)=Rt 2258 let AddedComplexity = 10, 2259 isPredicated = 1 in 2260 def STrih_indexed_shl_cPt_V4 : STInst2<(outs), 2261 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2262 IntRegs:$src5), 2263 "if ($src1) memh($src2+$src3<<#$src4) = $src5", 2264 []>, 2265 Requires<[HasV4T]>; 2266 2267 // if (Pv.new) memh(Rs+Ru<<#u2)=Rt 2268 let AddedComplexity = 10, 2269 isPredicated = 1 in 2270 def STrih_indexed_shl_cdnPt_V4 : STInst2<(outs), 2271 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2272 IntRegs:$src5), 2273 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5", 2274 []>, 2275 Requires<[HasV4T]>; 2276 2277 // if (!Pv) memh(Rs+Ru<<#u2)=Rt 2278 let AddedComplexity = 10, 2279 isPredicated = 1 in 2280 def STrih_indexed_shl_cNotPt_V4 : STInst2<(outs), 2281 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2282 IntRegs:$src5), 2283 "if (!$src1) memh($src2+$src3<<#$src4) = $src5", 2284 []>, 2285 Requires<[HasV4T]>; 2286 2287 // if (!Pv.new) memh(Rs+Ru<<#u2)=Rt 2288 let AddedComplexity = 10, 2289 isPredicated = 1 in 2290 def STrih_indexed_shl_cdnNotPt_V4 : STInst2<(outs), 2291 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2292 IntRegs:$src5), 2293 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5", 2294 []>, 2295 Requires<[HasV4T]>; 2296 2297 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H 2298 // TODO: Needs to be implemented. 2299 2300 // if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt 2301 // if (Pv) memh(Rx++#s4:1)=Rt 2302 // if (Pv.new) memh(Rx++#s4:1)=Rt 2303 let hasCtrlDep = 1, 2304 isPredicated = 1 in 2305 def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst), 2306 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), 2307 "if ($src1.new) memh($src3++#$offset) = $src2", 2308 [],"$src3 = $dst">, 2309 Requires<[HasV4T]>; 2310 2311 // if (!Pv) memh(Rx++#s4:1)=Rt 2312 // if (!Pv.new) memh(Rx++#s4:1)=Rt 2313 let hasCtrlDep = 1, 2314 isPredicated = 1 in 2315 def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst), 2316 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), 2317 "if (!$src1.new) memh($src3++#$offset) = $src2", 2318 [],"$src3 = $dst">, 2319 Requires<[HasV4T]>; 2320 2321 2322 // Store word. 2323 // memw(Re=#U6)=Rt 2324 // TODO: Needs to be implemented. 2325 2326 // Store predicate: 2327 let neverHasSideEffects = 1 in 2328 def STriw_pred_V4 : STInst2<(outs), 2329 (ins MEMri:$addr, PredRegs:$src1), 2330 "Error; should not emit", 2331 []>, 2332 Requires<[HasV4T]>; 2333 2334 2335 // memw(Rs+#u6:2)=#S8 2336 let AddedComplexity = 10, isPredicable = 1 in 2337 def STriw_imm_V4 : STInst<(outs), 2338 (ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3), 2339 "memw($src1+#$src2) = #$src3", 2340 [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1), 2341 u6_2ImmPred:$src2))]>, 2342 Requires<[HasV4T]>; 2343 2344 // memw(Rs+Ru<<#u2)=Rt 2345 let AddedComplexity = 10, isPredicable = 1 in 2346 def STriw_indexed_shl_V4 : STInst<(outs), 2347 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4), 2348 "memw($src1+$src2<<#$src3) = $src4", 2349 [(store (i32 IntRegs:$src4), (add (i32 IntRegs:$src1), 2350 (shl (i32 IntRegs:$src2), 2351 u2ImmPred:$src3)))]>, 2352 Requires<[HasV4T]>; 2353 2354 // memw(Ru<<#u2+#U6)=Rt 2355 let AddedComplexity = 10 in 2356 def STriw_shl_V4 : STInst<(outs), 2357 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4), 2358 "memw($src1<<#$src2+#$src3) = $src4", 2359 [(store (i32 IntRegs:$src4), 2360 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2), 2361 u6ImmPred:$src3))]>, 2362 Requires<[HasV4T]>; 2363 2364 // memw(Rx++#s4:2)=Rt 2365 // memw(Rx++#s4:2:circ(Mu))=Rt 2366 // memw(Rx++I:circ(Mu))=Rt 2367 // memw(Rx++Mu)=Rt 2368 // memw(Rx++Mu:brev)=Rt 2369 // memw(gp+#u16:2)=Rt 2370 2371 2372 // Store word conditionally. 2373 2374 // if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6 2375 // if (Pv) memw(Rs+#u6:2)=#S6 2376 let neverHasSideEffects = 1, 2377 isPredicated = 1 in 2378 def STriw_imm_cPt_V4 : STInst2<(outs), 2379 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4), 2380 "if ($src1) memw($src2+#$src3) = #$src4", 2381 []>, 2382 Requires<[HasV4T]>; 2383 2384 // if (Pv.new) memw(Rs+#u6:2)=#S6 2385 let neverHasSideEffects = 1, 2386 isPredicated = 1 in 2387 def STriw_imm_cdnPt_V4 : STInst2<(outs), 2388 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4), 2389 "if ($src1.new) memw($src2+#$src3) = #$src4", 2390 []>, 2391 Requires<[HasV4T]>; 2392 2393 // if (!Pv) memw(Rs+#u6:2)=#S6 2394 let neverHasSideEffects = 1, 2395 isPredicated = 1 in 2396 def STriw_imm_cNotPt_V4 : STInst2<(outs), 2397 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4), 2398 "if (!$src1) memw($src2+#$src3) = #$src4", 2399 []>, 2400 Requires<[HasV4T]>; 2401 2402 // if (!Pv.new) memw(Rs+#u6:2)=#S6 2403 let neverHasSideEffects = 1, 2404 isPredicated = 1 in 2405 def STriw_imm_cdnNotPt_V4 : STInst2<(outs), 2406 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4), 2407 "if (!$src1.new) memw($src2+#$src3) = #$src4", 2408 []>, 2409 Requires<[HasV4T]>; 2410 2411 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt 2412 // if (Pv) memw(Rs+#u6:2)=Rt 2413 // if (Pv.new) memw(Rs+#u6:2)=Rt 2414 let neverHasSideEffects = 1, 2415 isPredicated = 1 in 2416 def STriw_cdnPt_V4 : STInst2<(outs), 2417 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 2418 "if ($src1.new) memw($addr) = $src2", 2419 []>, 2420 Requires<[HasV4T]>; 2421 2422 // if (!Pv) memw(Rs+#u6:2)=Rt 2423 // if (!Pv.new) memw(Rs+#u6:2)=Rt 2424 let neverHasSideEffects = 1, 2425 isPredicated = 1 in 2426 def STriw_cdnNotPt_V4 : STInst2<(outs), 2427 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 2428 "if (!$src1.new) memw($addr) = $src2", 2429 []>, 2430 Requires<[HasV4T]>; 2431 2432 // if (Pv) memw(Rs+#u6:2)=Rt 2433 // if (!Pv) memw(Rs+#u6:2)=Rt 2434 // if (Pv.new) memw(Rs+#u6:2)=Rt 2435 let neverHasSideEffects = 1, 2436 isPredicated = 1 in 2437 def STriw_indexed_cdnPt_V4 : STInst2<(outs), 2438 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4), 2439 "if ($src1.new) memw($src2+#$src3) = $src4", 2440 []>, 2441 Requires<[HasV4T]>; 2442 2443 // if (!Pv.new) memw(Rs+#u6:2)=Rt 2444 let neverHasSideEffects = 1, 2445 isPredicated = 1 in 2446 def STriw_indexed_cdnNotPt_V4 : STInst2<(outs), 2447 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4), 2448 "if (!$src1.new) memw($src2+#$src3) = $src4", 2449 []>, 2450 Requires<[HasV4T]>; 2451 2452 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt 2453 // if (Pv) memw(Rs+Ru<<#u2)=Rt 2454 let AddedComplexity = 10, 2455 isPredicated = 1 in 2456 def STriw_indexed_shl_cPt_V4 : STInst2<(outs), 2457 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2458 IntRegs:$src5), 2459 "if ($src1) memw($src2+$src3<<#$src4) = $src5", 2460 []>, 2461 Requires<[HasV4T]>; 2462 2463 // if (Pv.new) memw(Rs+Ru<<#u2)=Rt 2464 let AddedComplexity = 10, 2465 isPredicated = 1 in 2466 def STriw_indexed_shl_cdnPt_V4 : STInst2<(outs), 2467 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2468 IntRegs:$src5), 2469 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5", 2470 []>, 2471 Requires<[HasV4T]>; 2472 2473 // if (!Pv) memw(Rs+Ru<<#u2)=Rt 2474 let AddedComplexity = 10, 2475 isPredicated = 1 in 2476 def STriw_indexed_shl_cNotPt_V4 : STInst2<(outs), 2477 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2478 IntRegs:$src5), 2479 "if (!$src1) memw($src2+$src3<<#$src4) = $src5", 2480 []>, 2481 Requires<[HasV4T]>; 2482 2483 // if (!Pv.new) memw(Rs+Ru<<#u2)=Rt 2484 let AddedComplexity = 10, 2485 isPredicated = 1 in 2486 def STriw_indexed_shl_cdnNotPt_V4 : STInst2<(outs), 2487 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 2488 IntRegs:$src5), 2489 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5", 2490 []>, 2491 Requires<[HasV4T]>; 2492 2493 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt 2494 // if (Pv) memw(Rx++#s4:2)=Rt 2495 // if (Pv.new) memw(Rx++#s4:2)=Rt 2496 let hasCtrlDep = 1, 2497 isPredicated = 1 in 2498 def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst), 2499 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), 2500 "if ($src1.new) memw($src3++#$offset) = $src2", 2501 [],"$src3 = $dst">, 2502 Requires<[HasV4T]>; 2503 2504 // if (!Pv) memw(Rx++#s4:2)=Rt 2505 // if (!Pv.new) memw(Rx++#s4:2)=Rt 2506 let hasCtrlDep = 1, 2507 isPredicated = 1 in 2508 def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst), 2509 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), 2510 "if (!$src1.new) memw($src3++#$offset) = $src2", 2511 [],"$src3 = $dst">, 2512 Requires<[HasV4T]>; 2513 2514 2515 /// store to global address 2516 2517 let isPredicable = 1, neverHasSideEffects = 1 in 2518 def STrid_GP_V4 : STInst2<(outs), 2519 (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src), 2520 "memd(#$global+$offset) = $src", 2521 []>, 2522 Requires<[HasV4T]>; 2523 2524 let neverHasSideEffects = 1, isPredicated = 1 in 2525 def STrid_GP_cPt_V4 : STInst2<(outs), 2526 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2527 DoubleRegs:$src2), 2528 "if ($src1) memd(##$global+$offset) = $src2", 2529 []>, 2530 Requires<[HasV4T]>; 2531 2532 let neverHasSideEffects = 1, isPredicated = 1 in 2533 def STrid_GP_cNotPt_V4 : STInst2<(outs), 2534 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2535 DoubleRegs:$src2), 2536 "if (!$src1) memd(##$global+$offset) = $src2", 2537 []>, 2538 Requires<[HasV4T]>; 2539 2540 let neverHasSideEffects = 1, isPredicated = 1 in 2541 def STrid_GP_cdnPt_V4 : STInst2<(outs), 2542 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2543 DoubleRegs:$src2), 2544 "if ($src1.new) memd(##$global+$offset) = $src2", 2545 []>, 2546 Requires<[HasV4T]>; 2547 2548 let neverHasSideEffects = 1, isPredicated = 1 in 2549 def STrid_GP_cdnNotPt_V4 : STInst2<(outs), 2550 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2551 DoubleRegs:$src2), 2552 "if (!$src1.new) memd(##$global+$offset) = $src2", 2553 []>, 2554 Requires<[HasV4T]>; 2555 2556 let isPredicable = 1, neverHasSideEffects = 1 in 2557 def STrib_GP_V4 : STInst2<(outs), 2558 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), 2559 "memb(#$global+$offset) = $src", 2560 []>, 2561 Requires<[HasV4T]>; 2562 2563 let neverHasSideEffects = 1, isPredicated = 1 in 2564 def STrib_GP_cPt_V4 : STInst2<(outs), 2565 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2566 IntRegs:$src2), 2567 "if ($src1) memb(##$global+$offset) = $src2", 2568 []>, 2569 Requires<[HasV4T]>; 2570 2571 let neverHasSideEffects = 1, isPredicated = 1 in 2572 def STrib_GP_cNotPt_V4 : STInst2<(outs), 2573 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2574 IntRegs:$src2), 2575 "if (!$src1) memb(##$global+$offset) = $src2", 2576 []>, 2577 Requires<[HasV4T]>; 2578 2579 let neverHasSideEffects = 1, isPredicated = 1 in 2580 def STrib_GP_cdnPt_V4 : STInst2<(outs), 2581 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2582 IntRegs:$src2), 2583 "if ($src1.new) memb(##$global+$offset) = $src2", 2584 []>, 2585 Requires<[HasV4T]>; 2586 2587 let neverHasSideEffects = 1, isPredicated = 1 in 2588 def STrib_GP_cdnNotPt_V4 : STInst2<(outs), 2589 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2590 IntRegs:$src2), 2591 "if (!$src1.new) memb(##$global+$offset) = $src2", 2592 []>, 2593 Requires<[HasV4T]>; 2594 2595 let isPredicable = 1, neverHasSideEffects = 1 in 2596 def STrih_GP_V4 : STInst2<(outs), 2597 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), 2598 "memh(#$global+$offset) = $src", 2599 []>, 2600 Requires<[HasV4T]>; 2601 2602 let neverHasSideEffects = 1, isPredicated = 1 in 2603 def STrih_GP_cPt_V4 : STInst2<(outs), 2604 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2605 IntRegs:$src2), 2606 "if ($src1) memh(##$global+$offset) = $src2", 2607 []>, 2608 Requires<[HasV4T]>; 2609 2610 let neverHasSideEffects = 1, isPredicated = 1 in 2611 def STrih_GP_cNotPt_V4 : STInst2<(outs), 2612 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2613 IntRegs:$src2), 2614 "if (!$src1) memh(##$global+$offset) = $src2", 2615 []>, 2616 Requires<[HasV4T]>; 2617 2618 let neverHasSideEffects = 1, isPredicated = 1 in 2619 def STrih_GP_cdnPt_V4 : STInst2<(outs), 2620 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2621 IntRegs:$src2), 2622 "if ($src1.new) memh(##$global+$offset) = $src2", 2623 []>, 2624 Requires<[HasV4T]>; 2625 2626 let neverHasSideEffects = 1, isPredicated = 1 in 2627 def STrih_GP_cdnNotPt_V4 : STInst2<(outs), 2628 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2629 IntRegs:$src2), 2630 "if (!$src1.new) memh(##$global+$offset) = $src2", 2631 []>, 2632 Requires<[HasV4T]>; 2633 2634 let isPredicable = 1, neverHasSideEffects = 1 in 2635 def STriw_GP_V4 : STInst2<(outs), 2636 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), 2637 "memw(#$global+$offset) = $src", 2638 []>, 2639 Requires<[HasV4T]>; 2640 2641 let neverHasSideEffects = 1, isPredicated = 1 in 2642 def STriw_GP_cPt_V4 : STInst2<(outs), 2643 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2644 IntRegs:$src2), 2645 "if ($src1) memw(##$global+$offset) = $src2", 2646 []>, 2647 Requires<[HasV4T]>; 2648 2649 let neverHasSideEffects = 1, isPredicated = 1 in 2650 def STriw_GP_cNotPt_V4 : STInst2<(outs), 2651 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2652 IntRegs:$src2), 2653 "if (!$src1) memw(##$global+$offset) = $src2", 2654 []>, 2655 Requires<[HasV4T]>; 2656 2657 let neverHasSideEffects = 1, isPredicated = 1 in 2658 def STriw_GP_cdnPt_V4 : STInst2<(outs), 2659 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2660 IntRegs:$src2), 2661 "if ($src1.new) memw(##$global+$offset) = $src2", 2662 []>, 2663 Requires<[HasV4T]>; 2664 2665 let neverHasSideEffects = 1, isPredicated = 1 in 2666 def STriw_GP_cdnNotPt_V4 : STInst2<(outs), 2667 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 2668 IntRegs:$src2), 2669 "if (!$src1.new) memw(##$global+$offset) = $src2", 2670 []>, 2671 Requires<[HasV4T]>; 2672 2673 // memd(#global)=Rtt 2674 let isPredicable = 1, neverHasSideEffects = 1 in 2675 def STd_GP_V4 : STInst2<(outs), 2676 (ins globaladdress:$global, DoubleRegs:$src), 2677 "memd(#$global) = $src", 2678 []>, 2679 Requires<[HasV4T]>; 2680 2681 // if (Pv) memd(##global) = Rtt 2682 let neverHasSideEffects = 1, isPredicated = 1 in 2683 def STd_GP_cPt_V4 : STInst2<(outs), 2684 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2), 2685 "if ($src1) memd(##$global) = $src2", 2686 []>, 2687 Requires<[HasV4T]>; 2688 2689 // if (!Pv) memd(##global) = Rtt 2690 let neverHasSideEffects = 1, isPredicated = 1 in 2691 def STd_GP_cNotPt_V4 : STInst2<(outs), 2692 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2), 2693 "if (!$src1) memd(##$global) = $src2", 2694 []>, 2695 Requires<[HasV4T]>; 2696 2697 // if (Pv) memd(##global) = Rtt 2698 let neverHasSideEffects = 1, isPredicated = 1 in 2699 def STd_GP_cdnPt_V4 : STInst2<(outs), 2700 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2), 2701 "if ($src1.new) memd(##$global) = $src2", 2702 []>, 2703 Requires<[HasV4T]>; 2704 2705 // if (!Pv) memd(##global) = Rtt 2706 let neverHasSideEffects = 1, isPredicated = 1 in 2707 def STd_GP_cdnNotPt_V4 : STInst2<(outs), 2708 (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2), 2709 "if (!$src1.new) memd(##$global) = $src2", 2710 []>, 2711 Requires<[HasV4T]>; 2712 2713 // memb(#global)=Rt 2714 let isPredicable = 1, neverHasSideEffects = 1 in 2715 def STb_GP_V4 : STInst2<(outs), 2716 (ins globaladdress:$global, IntRegs:$src), 2717 "memb(#$global) = $src", 2718 []>, 2719 Requires<[HasV4T]>; 2720 2721 // if (Pv) memb(##global) = Rt 2722 let neverHasSideEffects = 1, isPredicated = 1 in 2723 def STb_GP_cPt_V4 : STInst2<(outs), 2724 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2725 "if ($src1) memb(##$global) = $src2", 2726 []>, 2727 Requires<[HasV4T]>; 2728 2729 // if (!Pv) memb(##global) = Rt 2730 let neverHasSideEffects = 1, isPredicated = 1 in 2731 def STb_GP_cNotPt_V4 : STInst2<(outs), 2732 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2733 "if (!$src1) memb(##$global) = $src2", 2734 []>, 2735 Requires<[HasV4T]>; 2736 2737 // if (Pv) memb(##global) = Rt 2738 let neverHasSideEffects = 1, isPredicated = 1 in 2739 def STb_GP_cdnPt_V4 : STInst2<(outs), 2740 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2741 "if ($src1.new) memb(##$global) = $src2", 2742 []>, 2743 Requires<[HasV4T]>; 2744 2745 // if (!Pv) memb(##global) = Rt 2746 let neverHasSideEffects = 1, isPredicated = 1 in 2747 def STb_GP_cdnNotPt_V4 : STInst2<(outs), 2748 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2749 "if (!$src1.new) memb(##$global) = $src2", 2750 []>, 2751 Requires<[HasV4T]>; 2752 2753 // memh(#global)=Rt 2754 let isPredicable = 1, neverHasSideEffects = 1 in 2755 def STh_GP_V4 : STInst2<(outs), 2756 (ins globaladdress:$global, IntRegs:$src), 2757 "memh(#$global) = $src", 2758 []>, 2759 Requires<[HasV4T]>; 2760 2761 // if (Pv) memh(##global) = Rt 2762 let neverHasSideEffects = 1, isPredicated = 1 in 2763 def STh_GP_cPt_V4 : STInst2<(outs), 2764 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2765 "if ($src1) memh(##$global) = $src2", 2766 []>, 2767 Requires<[HasV4T]>; 2768 2769 // if (!Pv) memh(##global) = Rt 2770 let neverHasSideEffects = 1, isPredicated = 1 in 2771 def STh_GP_cNotPt_V4 : STInst2<(outs), 2772 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2773 "if (!$src1) memh(##$global) = $src2", 2774 []>, 2775 Requires<[HasV4T]>; 2776 2777 // if (Pv) memh(##global) = Rt 2778 let neverHasSideEffects = 1, isPredicated = 1 in 2779 def STh_GP_cdnPt_V4 : STInst2<(outs), 2780 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2781 "if ($src1.new) memh(##$global) = $src2", 2782 []>, 2783 Requires<[HasV4T]>; 2784 2785 // if (!Pv) memh(##global) = Rt 2786 let neverHasSideEffects = 1, isPredicated = 1 in 2787 def STh_GP_cdnNotPt_V4 : STInst2<(outs), 2788 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2789 "if (!$src1.new) memh(##$global) = $src2", 2790 []>, 2791 Requires<[HasV4T]>; 2792 2793 // memw(#global)=Rt 2794 let isPredicable = 1, neverHasSideEffects = 1 in 2795 def STw_GP_V4 : STInst2<(outs), 2796 (ins globaladdress:$global, IntRegs:$src), 2797 "memw(#$global) = $src", 2798 []>, 2799 Requires<[HasV4T]>; 2800 2801 // if (Pv) memw(##global) = Rt 2802 let neverHasSideEffects = 1, isPredicated = 1 in 2803 def STw_GP_cPt_V4 : STInst2<(outs), 2804 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2805 "if ($src1) memw(##$global) = $src2", 2806 []>, 2807 Requires<[HasV4T]>; 2808 2809 // if (!Pv) memw(##global) = Rt 2810 let neverHasSideEffects = 1, isPredicated = 1 in 2811 def STw_GP_cNotPt_V4 : STInst2<(outs), 2812 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2813 "if (!$src1) memw(##$global) = $src2", 2814 []>, 2815 Requires<[HasV4T]>; 2816 2817 // if (Pv) memw(##global) = Rt 2818 let neverHasSideEffects = 1, isPredicated = 1 in 2819 def STw_GP_cdnPt_V4 : STInst2<(outs), 2820 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2821 "if ($src1.new) memw(##$global) = $src2", 2822 []>, 2823 Requires<[HasV4T]>; 2824 2825 // if (!Pv) memw(##global) = Rt 2826 let neverHasSideEffects = 1, isPredicated = 1 in 2827 def STw_GP_cdnNotPt_V4 : STInst2<(outs), 2828 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 2829 "if (!$src1.new) memw(##$global) = $src2", 2830 []>, 2831 Requires<[HasV4T]>; 2832 2833 // 64 bit atomic store 2834 def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global), 2835 (i64 DoubleRegs:$src1)), 2836 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>, 2837 Requires<[HasV4T]>; 2838 2839 // Map from store(globaladdress) -> memd(#foo) 2840 let AddedComplexity = 100 in 2841 def : Pat <(store (i64 DoubleRegs:$src1), 2842 (HexagonCONST32_GP tglobaladdr:$global)), 2843 (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>, 2844 Requires<[HasV4T]>; 2845 2846 // 8 bit atomic store 2847 def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global), 2848 (i32 IntRegs:$src1)), 2849 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>, 2850 Requires<[HasV4T]>; 2851 2852 // Map from store(globaladdress) -> memb(#foo) 2853 let AddedComplexity = 100 in 2854 def : Pat<(truncstorei8 (i32 IntRegs:$src1), 2855 (HexagonCONST32_GP tglobaladdr:$global)), 2856 (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>, 2857 Requires<[HasV4T]>; 2858 2859 // Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1" 2860 // to "r0 = 1; memw(#foo) = r0" 2861 let AddedComplexity = 100 in 2862 def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)), 2863 (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>, 2864 Requires<[HasV4T]>; 2865 2866 def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global), 2867 (i32 IntRegs:$src1)), 2868 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>, 2869 Requires<[HasV4T]>; 2870 2871 // Map from store(globaladdress) -> memh(#foo) 2872 let AddedComplexity = 100 in 2873 def : Pat<(truncstorei16 (i32 IntRegs:$src1), 2874 (HexagonCONST32_GP tglobaladdr:$global)), 2875 (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>, 2876 Requires<[HasV4T]>; 2877 2878 // 32 bit atomic store 2879 def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global), 2880 (i32 IntRegs:$src1)), 2881 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>, 2882 Requires<[HasV4T]>; 2883 2884 // Map from store(globaladdress) -> memw(#foo) 2885 let AddedComplexity = 100 in 2886 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)), 2887 (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>, 2888 Requires<[HasV4T]>; 2889 2890 def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global), 2891 u16ImmPred:$offset), 2892 (i64 DoubleRegs:$src1)), 2893 (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2894 (i64 DoubleRegs:$src1))>, 2895 Requires<[HasV4T]>; 2896 2897 def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global), 2898 u16ImmPred:$offset), 2899 (i32 IntRegs:$src1)), 2900 (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2901 (i32 IntRegs:$src1))>, 2902 Requires<[HasV4T]>; 2903 2904 def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global), 2905 u16ImmPred:$offset), 2906 (i32 IntRegs:$src1)), 2907 (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2908 (i32 IntRegs:$src1))>, 2909 Requires<[HasV4T]>; 2910 2911 def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global), 2912 u16ImmPred:$offset), 2913 (i32 IntRegs:$src1)), 2914 (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2915 (i32 IntRegs:$src1))>, 2916 Requires<[HasV4T]>; 2917 2918 // Map from store(globaladdress + x) -> memd(#foo + x) 2919 let AddedComplexity = 100 in 2920 def : Pat<(store (i64 DoubleRegs:$src1), 2921 (add (HexagonCONST32_GP tglobaladdr:$global), 2922 u16ImmPred:$offset)), 2923 (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2924 (i64 DoubleRegs:$src1))>, 2925 Requires<[HasV4T]>; 2926 2927 // Map from store(globaladdress + x) -> memb(#foo + x) 2928 let AddedComplexity = 100 in 2929 def : Pat<(truncstorei8 (i32 IntRegs:$src1), 2930 (add (HexagonCONST32_GP tglobaladdr:$global), 2931 u16ImmPred:$offset)), 2932 (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2933 (i32 IntRegs:$src1))>, 2934 Requires<[HasV4T]>; 2935 2936 // Map from store(globaladdress + x) -> memh(#foo + x) 2937 let AddedComplexity = 100 in 2938 def : Pat<(truncstorei16 (i32 IntRegs:$src1), 2939 (add (HexagonCONST32_GP tglobaladdr:$global), 2940 u16ImmPred:$offset)), 2941 (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2942 (i32 IntRegs:$src1))>, 2943 Requires<[HasV4T]>; 2944 2945 // Map from store(globaladdress + x) -> memw(#foo + x) 2946 let AddedComplexity = 100 in 2947 def : Pat<(store (i32 IntRegs:$src1), 2948 (add (HexagonCONST32_GP tglobaladdr:$global), 2949 u16ImmPred:$offset)), 2950 (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, 2951 (i32 IntRegs:$src1))>, 2952 Requires<[HasV4T]>; 2953 2954 2955 2956 //===----------------------------------------------------------------------=== 2957 // ST - 2958 //===----------------------------------------------------------------------=== 2959 2960 2961 //===----------------------------------------------------------------------===// 2962 // NV/ST + 2963 //===----------------------------------------------------------------------===// 2964 2965 // Store new-value byte. 2966 2967 // memb(Re=#U6)=Nt.new 2968 // memb(Rs+#s11:0)=Nt.new 2969 let mayStore = 1, isPredicable = 1 in 2970 def STrib_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1), 2971 "memb($addr) = $src1.new", 2972 []>, 2973 Requires<[HasV4T]>; 2974 2975 let mayStore = 1, isPredicable = 1 in 2976 def STrib_indexed_nv_V4 : NVInst_V4<(outs), 2977 (ins IntRegs:$src1, s11_0Imm:$src2, IntRegs:$src3), 2978 "memb($src1+#$src2) = $src3.new", 2979 []>, 2980 Requires<[HasV4T]>; 2981 2982 // memb(Rs+Ru<<#u2)=Nt.new 2983 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in 2984 def STrib_indexed_shl_nv_V4 : NVInst_V4<(outs), 2985 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4), 2986 "memb($src1+$src2<<#$src3) = $src4.new", 2987 []>, 2988 Requires<[HasV4T]>; 2989 2990 // memb(Ru<<#u2+#U6)=Nt.new 2991 let mayStore = 1, AddedComplexity = 10 in 2992 def STrib_shl_nv_V4 : NVInst_V4<(outs), 2993 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4), 2994 "memb($src1<<#$src2+#$src3) = $src4.new", 2995 []>, 2996 Requires<[HasV4T]>; 2997 2998 // memb(Rx++#s4:0)=Nt.new 2999 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in 3000 def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3001 (ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset), 3002 "memb($src2++#$offset) = $src1.new", 3003 [], 3004 "$src2 = $dst">, 3005 Requires<[HasV4T]>; 3006 3007 // memb(Rx++#s4:0:circ(Mu))=Nt.new 3008 // memb(Rx++I:circ(Mu))=Nt.new 3009 // memb(Rx++Mu)=Nt.new 3010 // memb(Rx++Mu:brev)=Nt.new 3011 3012 // memb(gp+#u16:0)=Nt.new 3013 let mayStore = 1, neverHasSideEffects = 1 in 3014 def STrib_GP_nv_V4 : NVInst_V4<(outs), 3015 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), 3016 "memb(#$global+$offset) = $src.new", 3017 []>, 3018 Requires<[HasV4T]>; 3019 3020 // memb(#global)=Nt.new 3021 let mayStore = 1, neverHasSideEffects = 1 in 3022 def STb_GP_nv_V4 : NVInst_V4<(outs), 3023 (ins globaladdress:$global, IntRegs:$src), 3024 "memb(#$global) = $src.new", 3025 []>, 3026 Requires<[HasV4T]>; 3027 3028 // Store new-value byte conditionally. 3029 // if ([!]Pv[.new]) memb(#u6)=Nt.new 3030 // if (Pv) memb(Rs+#u6:0)=Nt.new 3031 let mayStore = 1, neverHasSideEffects = 1, 3032 isPredicated = 1 in 3033 def STrib_cPt_nv_V4 : NVInst_V4<(outs), 3034 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3035 "if ($src1) memb($addr) = $src2.new", 3036 []>, 3037 Requires<[HasV4T]>; 3038 3039 // if (Pv.new) memb(Rs+#u6:0)=Nt.new 3040 let mayStore = 1, neverHasSideEffects = 1, 3041 isPredicated = 1 in 3042 def STrib_cdnPt_nv_V4 : NVInst_V4<(outs), 3043 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3044 "if ($src1.new) memb($addr) = $src2.new", 3045 []>, 3046 Requires<[HasV4T]>; 3047 3048 // if (!Pv) memb(Rs+#u6:0)=Nt.new 3049 let mayStore = 1, neverHasSideEffects = 1, 3050 isPredicated = 1 in 3051 def STrib_cNotPt_nv_V4 : NVInst_V4<(outs), 3052 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3053 "if (!$src1) memb($addr) = $src2.new", 3054 []>, 3055 Requires<[HasV4T]>; 3056 3057 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new 3058 let mayStore = 1, neverHasSideEffects = 1, 3059 isPredicated = 1 in 3060 def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3061 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3062 "if (!$src1.new) memb($addr) = $src2.new", 3063 []>, 3064 Requires<[HasV4T]>; 3065 3066 // if (Pv) memb(Rs+#u6:0)=Nt.new 3067 let mayStore = 1, neverHasSideEffects = 1, 3068 isPredicated = 1 in 3069 def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs), 3070 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4), 3071 "if ($src1) memb($src2+#$src3) = $src4.new", 3072 []>, 3073 Requires<[HasV4T]>; 3074 3075 // if (Pv.new) memb(Rs+#u6:0)=Nt.new 3076 let mayStore = 1, neverHasSideEffects = 1, 3077 isPredicated = 1 in 3078 def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs), 3079 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4), 3080 "if ($src1.new) memb($src2+#$src3) = $src4.new", 3081 []>, 3082 Requires<[HasV4T]>; 3083 3084 // if (!Pv) memb(Rs+#u6:0)=Nt.new 3085 let mayStore = 1, neverHasSideEffects = 1, 3086 isPredicated = 1 in 3087 def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs), 3088 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4), 3089 "if (!$src1) memb($src2+#$src3) = $src4.new", 3090 []>, 3091 Requires<[HasV4T]>; 3092 3093 // if (!Pv.new) memb(Rs+#u6:0)=Nt.new 3094 let mayStore = 1, neverHasSideEffects = 1, 3095 isPredicated = 1 in 3096 def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3097 (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4), 3098 "if (!$src1.new) memb($src2+#$src3) = $src4.new", 3099 []>, 3100 Requires<[HasV4T]>; 3101 3102 3103 // if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new 3104 // if (Pv) memb(Rs+Ru<<#u2)=Nt.new 3105 let mayStore = 1, AddedComplexity = 10, 3106 isPredicated = 1 in 3107 def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs), 3108 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3109 IntRegs:$src5), 3110 "if ($src1) memb($src2+$src3<<#$src4) = $src5.new", 3111 []>, 3112 Requires<[HasV4T]>; 3113 3114 // if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new 3115 let mayStore = 1, AddedComplexity = 10, 3116 isPredicated = 1 in 3117 def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs), 3118 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3119 IntRegs:$src5), 3120 "if ($src1.new) memb($src2+$src3<<#$src4) = $src5.new", 3121 []>, 3122 Requires<[HasV4T]>; 3123 3124 // if (!Pv) memb(Rs+Ru<<#u2)=Nt.new 3125 let mayStore = 1, AddedComplexity = 10, 3126 isPredicated = 1 in 3127 def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs), 3128 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3129 IntRegs:$src5), 3130 "if (!$src1) memb($src2+$src3<<#$src4) = $src5.new", 3131 []>, 3132 Requires<[HasV4T]>; 3133 3134 // if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new 3135 let mayStore = 1, AddedComplexity = 10, 3136 isPredicated = 1 in 3137 def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3138 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3139 IntRegs:$src5), 3140 "if (!$src1.new) memb($src2+$src3<<#$src4) = $src5.new", 3141 []>, 3142 Requires<[HasV4T]>; 3143 3144 // if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new 3145 // if (Pv) memb(Rx++#s4:0)=Nt.new 3146 let mayStore = 1, hasCtrlDep = 1, 3147 isPredicated = 1 in 3148 def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3149 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), 3150 "if ($src1) memb($src3++#$offset) = $src2.new", 3151 [],"$src3 = $dst">, 3152 Requires<[HasV4T]>; 3153 3154 // if (Pv.new) memb(Rx++#s4:0)=Nt.new 3155 let mayStore = 1, hasCtrlDep = 1, 3156 isPredicated = 1 in 3157 def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3158 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), 3159 "if ($src1.new) memb($src3++#$offset) = $src2.new", 3160 [],"$src3 = $dst">, 3161 Requires<[HasV4T]>; 3162 3163 // if (!Pv) memb(Rx++#s4:0)=Nt.new 3164 let mayStore = 1, hasCtrlDep = 1, 3165 isPredicated = 1 in 3166 def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3167 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), 3168 "if (!$src1) memb($src3++#$offset) = $src2.new", 3169 [],"$src3 = $dst">, 3170 Requires<[HasV4T]>; 3171 3172 // if (!Pv.new) memb(Rx++#s4:0)=Nt.new 3173 let mayStore = 1, hasCtrlDep = 1, 3174 isPredicated = 1 in 3175 def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3176 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), 3177 "if (!$src1.new) memb($src3++#$offset) = $src2.new", 3178 [],"$src3 = $dst">, 3179 Requires<[HasV4T]>; 3180 3181 3182 // Store new-value halfword. 3183 // memh(Re=#U6)=Nt.new 3184 // memh(Rs+#s11:1)=Nt.new 3185 let mayStore = 1, isPredicable = 1 in 3186 def STrih_nv_V4 : NVInst_V4<(outs), (ins MEMri:$addr, IntRegs:$src1), 3187 "memh($addr) = $src1.new", 3188 []>, 3189 Requires<[HasV4T]>; 3190 3191 let mayStore = 1, isPredicable = 1 in 3192 def STrih_indexed_nv_V4 : NVInst_V4<(outs), 3193 (ins IntRegs:$src1, s11_1Imm:$src2, IntRegs:$src3), 3194 "memh($src1+#$src2) = $src3.new", 3195 []>, 3196 Requires<[HasV4T]>; 3197 3198 // memh(Rs+Ru<<#u2)=Nt.new 3199 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in 3200 def STrih_indexed_shl_nv_V4 : NVInst_V4<(outs), 3201 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4), 3202 "memh($src1+$src2<<#$src3) = $src4.new", 3203 []>, 3204 Requires<[HasV4T]>; 3205 3206 // memh(Ru<<#u2+#U6)=Nt.new 3207 let mayStore = 1, AddedComplexity = 10 in 3208 def STrih_shl_nv_V4 : NVInst_V4<(outs), 3209 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4), 3210 "memh($src1<<#$src2+#$src3) = $src4.new", 3211 []>, 3212 Requires<[HasV4T]>; 3213 3214 // memh(Rx++#s4:1)=Nt.new 3215 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in 3216 def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3217 (ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset), 3218 "memh($src2++#$offset) = $src1.new", 3219 [], 3220 "$src2 = $dst">, 3221 Requires<[HasV4T]>; 3222 3223 // memh(Rx++#s4:1:circ(Mu))=Nt.new 3224 // memh(Rx++I:circ(Mu))=Nt.new 3225 // memh(Rx++Mu)=Nt.new 3226 // memh(Rx++Mu:brev)=Nt.new 3227 3228 // memh(gp+#u16:1)=Nt.new 3229 let mayStore = 1, neverHasSideEffects = 1 in 3230 def STrih_GP_nv_V4 : NVInst_V4<(outs), 3231 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), 3232 "memh(#$global+$offset) = $src.new", 3233 []>, 3234 Requires<[HasV4T]>; 3235 3236 // memh(#global)=Nt.new 3237 let mayStore = 1, neverHasSideEffects = 1 in 3238 def STh_GP_nv_V4 : NVInst_V4<(outs), 3239 (ins globaladdress:$global, IntRegs:$src), 3240 "memh(#$global) = $src.new", 3241 []>, 3242 Requires<[HasV4T]>; 3243 3244 3245 // Store new-value halfword conditionally. 3246 3247 // if ([!]Pv[.new]) memh(#u6)=Nt.new 3248 3249 // if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new 3250 // if (Pv) memh(Rs+#u6:1)=Nt.new 3251 let mayStore = 1, neverHasSideEffects = 1, 3252 isPredicated = 1 in 3253 def STrih_cPt_nv_V4 : NVInst_V4<(outs), 3254 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3255 "if ($src1) memh($addr) = $src2.new", 3256 []>, 3257 Requires<[HasV4T]>; 3258 3259 // if (Pv.new) memh(Rs+#u6:1)=Nt.new 3260 let mayStore = 1, neverHasSideEffects = 1, 3261 isPredicated = 1 in 3262 def STrih_cdnPt_nv_V4 : NVInst_V4<(outs), 3263 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3264 "if ($src1.new) memh($addr) = $src2.new", 3265 []>, 3266 Requires<[HasV4T]>; 3267 3268 // if (!Pv) memh(Rs+#u6:1)=Nt.new 3269 let mayStore = 1, neverHasSideEffects = 1, 3270 isPredicated = 1 in 3271 def STrih_cNotPt_nv_V4 : NVInst_V4<(outs), 3272 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3273 "if (!$src1) memh($addr) = $src2.new", 3274 []>, 3275 Requires<[HasV4T]>; 3276 3277 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new 3278 let mayStore = 1, neverHasSideEffects = 1, 3279 isPredicated = 1 in 3280 def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3281 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3282 "if (!$src1.new) memh($addr) = $src2.new", 3283 []>, 3284 Requires<[HasV4T]>; 3285 3286 // if (Pv) memh(Rs+#u6:1)=Nt.new 3287 let mayStore = 1, neverHasSideEffects = 1, 3288 isPredicated = 1 in 3289 def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs), 3290 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4), 3291 "if ($src1) memh($src2+#$src3) = $src4.new", 3292 []>, 3293 Requires<[HasV4T]>; 3294 3295 // if (Pv.new) memh(Rs+#u6:1)=Nt.new 3296 let mayStore = 1, neverHasSideEffects = 1, 3297 isPredicated = 1 in 3298 def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs), 3299 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4), 3300 "if ($src1.new) memh($src2+#$src3) = $src4.new", 3301 []>, 3302 Requires<[HasV4T]>; 3303 3304 // if (!Pv) memh(Rs+#u6:1)=Nt.new 3305 let mayStore = 1, neverHasSideEffects = 1, 3306 isPredicated = 1 in 3307 def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs), 3308 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4), 3309 "if (!$src1) memh($src2+#$src3) = $src4.new", 3310 []>, 3311 Requires<[HasV4T]>; 3312 3313 // if (!Pv.new) memh(Rs+#u6:1)=Nt.new 3314 let mayStore = 1, neverHasSideEffects = 1, 3315 isPredicated = 1 in 3316 def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3317 (ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4), 3318 "if (!$src1.new) memh($src2+#$src3) = $src4.new", 3319 []>, 3320 Requires<[HasV4T]>; 3321 3322 // if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new 3323 // if (Pv) memh(Rs+Ru<<#u2)=Nt.new 3324 let mayStore = 1, AddedComplexity = 10, 3325 isPredicated = 1 in 3326 def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs), 3327 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3328 IntRegs:$src5), 3329 "if ($src1) memh($src2+$src3<<#$src4) = $src5.new", 3330 []>, 3331 Requires<[HasV4T]>; 3332 3333 // if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new 3334 let mayStore = 1, AddedComplexity = 10, 3335 isPredicated = 1 in 3336 def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs), 3337 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3338 IntRegs:$src5), 3339 "if ($src1.new) memh($src2+$src3<<#$src4) = $src5.new", 3340 []>, 3341 Requires<[HasV4T]>; 3342 3343 // if (!Pv) memh(Rs+Ru<<#u2)=Nt.new 3344 let mayStore = 1, AddedComplexity = 10, 3345 isPredicated = 1 in 3346 def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs), 3347 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3348 IntRegs:$src5), 3349 "if (!$src1) memh($src2+$src3<<#$src4) = $src5.new", 3350 []>, 3351 Requires<[HasV4T]>; 3352 3353 // if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new 3354 let mayStore = 1, AddedComplexity = 10, 3355 isPredicated = 1 in 3356 def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3357 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3358 IntRegs:$src5), 3359 "if (!$src1.new) memh($src2+$src3<<#$src4) = $src5.new", 3360 []>, 3361 Requires<[HasV4T]>; 3362 3363 // if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new 3364 // if (Pv) memh(Rx++#s4:1)=Nt.new 3365 let mayStore = 1, hasCtrlDep = 1, 3366 isPredicated = 1 in 3367 def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3368 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), 3369 "if ($src1) memh($src3++#$offset) = $src2.new", 3370 [],"$src3 = $dst">, 3371 Requires<[HasV4T]>; 3372 3373 // if (Pv.new) memh(Rx++#s4:1)=Nt.new 3374 let mayStore = 1, hasCtrlDep = 1, 3375 isPredicated = 1 in 3376 def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3377 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), 3378 "if ($src1.new) memh($src3++#$offset) = $src2.new", 3379 [],"$src3 = $dst">, 3380 Requires<[HasV4T]>; 3381 3382 // if (!Pv) memh(Rx++#s4:1)=Nt.new 3383 let mayStore = 1, hasCtrlDep = 1, 3384 isPredicated = 1 in 3385 def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3386 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), 3387 "if (!$src1) memh($src3++#$offset) = $src2.new", 3388 [],"$src3 = $dst">, 3389 Requires<[HasV4T]>; 3390 3391 // if (!Pv.new) memh(Rx++#s4:1)=Nt.new 3392 let mayStore = 1, hasCtrlDep = 1, 3393 isPredicated = 1 in 3394 def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3395 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), 3396 "if (!$src1.new) memh($src3++#$offset) = $src2.new", 3397 [],"$src3 = $dst">, 3398 Requires<[HasV4T]>; 3399 3400 3401 // Store new-value word. 3402 3403 // memw(Re=#U6)=Nt.new 3404 // memw(Rs+#s11:2)=Nt.new 3405 let mayStore = 1, isPredicable = 1 in 3406 def STriw_nv_V4 : NVInst_V4<(outs), 3407 (ins MEMri:$addr, IntRegs:$src1), 3408 "memw($addr) = $src1.new", 3409 []>, 3410 Requires<[HasV4T]>; 3411 3412 let mayStore = 1, isPredicable = 1 in 3413 def STriw_indexed_nv_V4 : NVInst_V4<(outs), 3414 (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3), 3415 "memw($src1+#$src2) = $src3.new", 3416 []>, 3417 Requires<[HasV4T]>; 3418 3419 // memw(Rs+Ru<<#u2)=Nt.new 3420 let mayStore = 1, AddedComplexity = 10, isPredicable = 1 in 3421 def STriw_indexed_shl_nv_V4 : NVInst_V4<(outs), 3422 (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4), 3423 "memw($src1+$src2<<#$src3) = $src4.new", 3424 []>, 3425 Requires<[HasV4T]>; 3426 3427 // memw(Ru<<#u2+#U6)=Nt.new 3428 let mayStore = 1, AddedComplexity = 10 in 3429 def STriw_shl_nv_V4 : NVInst_V4<(outs), 3430 (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4), 3431 "memw($src1<<#$src2+#$src3) = $src4.new", 3432 []>, 3433 Requires<[HasV4T]>; 3434 3435 // memw(Rx++#s4:2)=Nt.new 3436 let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in 3437 def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3438 (ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset), 3439 "memw($src2++#$offset) = $src1.new", 3440 [], 3441 "$src2 = $dst">, 3442 Requires<[HasV4T]>; 3443 3444 // memw(Rx++#s4:2:circ(Mu))=Nt.new 3445 // memw(Rx++I:circ(Mu))=Nt.new 3446 // memw(Rx++Mu)=Nt.new 3447 // memw(Rx++Mu:brev)=Nt.new 3448 // memw(gp+#u16:2)=Nt.new 3449 let mayStore = 1, neverHasSideEffects = 1 in 3450 def STriw_GP_nv_V4 : NVInst_V4<(outs), 3451 (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), 3452 "memw(#$global+$offset) = $src.new", 3453 []>, 3454 Requires<[HasV4T]>; 3455 3456 let mayStore = 1, neverHasSideEffects = 1 in 3457 def STw_GP_nv_V4 : NVInst_V4<(outs), 3458 (ins globaladdress:$global, IntRegs:$src), 3459 "memw(#$global) = $src.new", 3460 []>, 3461 Requires<[HasV4T]>; 3462 3463 // Store new-value word conditionally. 3464 3465 // if ([!]Pv[.new]) memw(#u6)=Nt.new 3466 3467 // if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new 3468 // if (Pv) memw(Rs+#u6:2)=Nt.new 3469 let mayStore = 1, neverHasSideEffects = 1, 3470 isPredicated = 1 in 3471 def STriw_cPt_nv_V4 : NVInst_V4<(outs), 3472 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3473 "if ($src1) memw($addr) = $src2.new", 3474 []>, 3475 Requires<[HasV4T]>; 3476 3477 // if (Pv.new) memw(Rs+#u6:2)=Nt.new 3478 let mayStore = 1, neverHasSideEffects = 1, 3479 isPredicated = 1 in 3480 def STriw_cdnPt_nv_V4 : NVInst_V4<(outs), 3481 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3482 "if ($src1.new) memw($addr) = $src2.new", 3483 []>, 3484 Requires<[HasV4T]>; 3485 3486 // if (!Pv) memw(Rs+#u6:2)=Nt.new 3487 let mayStore = 1, neverHasSideEffects = 1, 3488 isPredicated = 1 in 3489 def STriw_cNotPt_nv_V4 : NVInst_V4<(outs), 3490 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3491 "if (!$src1) memw($addr) = $src2.new", 3492 []>, 3493 Requires<[HasV4T]>; 3494 3495 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new 3496 let mayStore = 1, neverHasSideEffects = 1, 3497 isPredicated = 1 in 3498 def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3499 (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2), 3500 "if (!$src1.new) memw($addr) = $src2.new", 3501 []>, 3502 Requires<[HasV4T]>; 3503 3504 // if (Pv) memw(Rs+#u6:2)=Nt.new 3505 let mayStore = 1, neverHasSideEffects = 1, 3506 isPredicated = 1 in 3507 def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs), 3508 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4), 3509 "if ($src1) memw($src2+#$src3) = $src4.new", 3510 []>, 3511 Requires<[HasV4T]>; 3512 3513 // if (Pv.new) memw(Rs+#u6:2)=Nt.new 3514 let mayStore = 1, neverHasSideEffects = 1, 3515 isPredicated = 1 in 3516 def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs), 3517 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4), 3518 "if ($src1.new) memw($src2+#$src3) = $src4.new", 3519 []>, 3520 Requires<[HasV4T]>; 3521 3522 // if (!Pv) memw(Rs+#u6:2)=Nt.new 3523 let mayStore = 1, neverHasSideEffects = 1, 3524 isPredicated = 1 in 3525 def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs), 3526 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4), 3527 "if (!$src1) memw($src2+#$src3) = $src4.new", 3528 []>, 3529 Requires<[HasV4T]>; 3530 3531 // if (!Pv.new) memw(Rs+#u6:2)=Nt.new 3532 let mayStore = 1, neverHasSideEffects = 1, 3533 isPredicated = 1 in 3534 def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3535 (ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4), 3536 "if (!$src1.new) memw($src2+#$src3) = $src4.new", 3537 []>, 3538 Requires<[HasV4T]>; 3539 3540 3541 // if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new 3542 // if (Pv) memw(Rs+Ru<<#u2)=Nt.new 3543 let mayStore = 1, AddedComplexity = 10, 3544 isPredicated = 1 in 3545 def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs), 3546 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3547 IntRegs:$src5), 3548 "if ($src1) memw($src2+$src3<<#$src4) = $src5.new", 3549 []>, 3550 Requires<[HasV4T]>; 3551 3552 // if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new 3553 let mayStore = 1, AddedComplexity = 10, 3554 isPredicated = 1 in 3555 def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs), 3556 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3557 IntRegs:$src5), 3558 "if ($src1.new) memw($src2+$src3<<#$src4) = $src5.new", 3559 []>, 3560 Requires<[HasV4T]>; 3561 3562 // if (!Pv) memw(Rs+Ru<<#u2)=Nt.new 3563 let mayStore = 1, AddedComplexity = 10, 3564 isPredicated = 1 in 3565 def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs), 3566 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3567 IntRegs:$src5), 3568 "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new", 3569 []>, 3570 Requires<[HasV4T]>; 3571 3572 // if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new 3573 let mayStore = 1, AddedComplexity = 10, 3574 isPredicated = 1 in 3575 def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3576 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4, 3577 IntRegs:$src5), 3578 "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new", 3579 []>, 3580 Requires<[HasV4T]>; 3581 3582 // if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new 3583 // if (Pv) memw(Rx++#s4:2)=Nt.new 3584 let mayStore = 1, hasCtrlDep = 1, 3585 isPredicated = 1 in 3586 def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3587 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), 3588 "if ($src1) memw($src3++#$offset) = $src2.new", 3589 [],"$src3 = $dst">, 3590 Requires<[HasV4T]>; 3591 3592 // if (Pv.new) memw(Rx++#s4:2)=Nt.new 3593 let mayStore = 1, hasCtrlDep = 1, 3594 isPredicated = 1 in 3595 def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3596 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), 3597 "if ($src1.new) memw($src3++#$offset) = $src2.new", 3598 [],"$src3 = $dst">, 3599 Requires<[HasV4T]>; 3600 3601 // if (!Pv) memw(Rx++#s4:2)=Nt.new 3602 let mayStore = 1, hasCtrlDep = 1, 3603 isPredicated = 1 in 3604 def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3605 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), 3606 "if (!$src1) memw($src3++#$offset) = $src2.new", 3607 [],"$src3 = $dst">, 3608 Requires<[HasV4T]>; 3609 3610 // if (!Pv.new) memw(Rx++#s4:2)=Nt.new 3611 let mayStore = 1, hasCtrlDep = 1, 3612 isPredicated = 1 in 3613 def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), 3614 (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), 3615 "if (!$src1.new) memw($src3++#$offset) = $src2.new", 3616 [],"$src3 = $dst">, 3617 Requires<[HasV4T]>; 3618 3619 3620 3621 // if (Pv) memb(##global) = Rt 3622 let mayStore = 1, neverHasSideEffects = 1 in 3623 def STb_GP_cPt_nv_V4 : NVInst_V4<(outs), 3624 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3625 "if ($src1) memb(##$global) = $src2.new", 3626 []>, 3627 Requires<[HasV4T]>; 3628 3629 // if (!Pv) memb(##global) = Rt 3630 let mayStore = 1, neverHasSideEffects = 1 in 3631 def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs), 3632 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3633 "if (!$src1) memb(##$global) = $src2.new", 3634 []>, 3635 Requires<[HasV4T]>; 3636 3637 // if (Pv) memb(##global) = Rt 3638 let mayStore = 1, neverHasSideEffects = 1 in 3639 def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs), 3640 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3641 "if ($src1.new) memb(##$global) = $src2.new", 3642 []>, 3643 Requires<[HasV4T]>; 3644 3645 // if (!Pv) memb(##global) = Rt 3646 let mayStore = 1, neverHasSideEffects = 1 in 3647 def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3648 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3649 "if (!$src1.new) memb(##$global) = $src2.new", 3650 []>, 3651 Requires<[HasV4T]>; 3652 3653 // if (Pv) memh(##global) = Rt 3654 let mayStore = 1, neverHasSideEffects = 1 in 3655 def STh_GP_cPt_nv_V4 : NVInst_V4<(outs), 3656 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3657 "if ($src1) memh(##$global) = $src2.new", 3658 []>, 3659 Requires<[HasV4T]>; 3660 3661 // if (!Pv) memh(##global) = Rt 3662 let mayStore = 1, neverHasSideEffects = 1 in 3663 def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs), 3664 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3665 "if (!$src1) memh(##$global) = $src2.new", 3666 []>, 3667 Requires<[HasV4T]>; 3668 3669 // if (Pv) memh(##global) = Rt 3670 let mayStore = 1, neverHasSideEffects = 1 in 3671 def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs), 3672 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3673 "if ($src1.new) memh(##$global) = $src2.new", 3674 []>, 3675 Requires<[HasV4T]>; 3676 3677 // if (!Pv) memh(##global) = Rt 3678 let mayStore = 1, neverHasSideEffects = 1 in 3679 def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3680 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3681 "if (!$src1.new) memh(##$global) = $src2.new", 3682 []>, 3683 Requires<[HasV4T]>; 3684 3685 // if (Pv) memw(##global) = Rt 3686 let mayStore = 1, neverHasSideEffects = 1 in 3687 def STw_GP_cPt_nv_V4 : NVInst_V4<(outs), 3688 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3689 "if ($src1) memw(##$global) = $src2.new", 3690 []>, 3691 Requires<[HasV4T]>; 3692 3693 // if (!Pv) memw(##global) = Rt 3694 let mayStore = 1, neverHasSideEffects = 1 in 3695 def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs), 3696 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3697 "if (!$src1) memw(##$global) = $src2.new", 3698 []>, 3699 Requires<[HasV4T]>; 3700 3701 // if (Pv) memw(##global) = Rt 3702 let mayStore = 1, neverHasSideEffects = 1 in 3703 def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs), 3704 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3705 "if ($src1.new) memw(##$global) = $src2.new", 3706 []>, 3707 Requires<[HasV4T]>; 3708 3709 // if (!Pv) memw(##global) = Rt 3710 let mayStore = 1, neverHasSideEffects = 1 in 3711 def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3712 (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2), 3713 "if (!$src1.new) memw(##$global) = $src2.new", 3714 []>, 3715 Requires<[HasV4T]>; 3716 3717 let mayStore = 1, neverHasSideEffects = 1 in 3718 def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs), 3719 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3720 IntRegs:$src2), 3721 "if ($src1) memb(##$global+$offset) = $src2.new", 3722 []>, 3723 Requires<[HasV4T]>; 3724 3725 let mayStore = 1, neverHasSideEffects = 1 in 3726 def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs), 3727 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3728 IntRegs:$src2), 3729 "if (!$src1) memb(##$global+$offset) = $src2.new", 3730 []>, 3731 Requires<[HasV4T]>; 3732 3733 let mayStore = 1, neverHasSideEffects = 1 in 3734 def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs), 3735 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3736 IntRegs:$src2), 3737 "if ($src1.new) memb(##$global+$offset) = $src2.new", 3738 []>, 3739 Requires<[HasV4T]>; 3740 3741 let mayStore = 1, neverHasSideEffects = 1 in 3742 def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3743 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3744 IntRegs:$src2), 3745 "if (!$src1.new) memb(##$global+$offset) = $src2.new", 3746 []>, 3747 Requires<[HasV4T]>; 3748 3749 let mayStore = 1, neverHasSideEffects = 1 in 3750 def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs), 3751 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3752 IntRegs:$src2), 3753 "if ($src1) memh(##$global+$offset) = $src2.new", 3754 []>, 3755 Requires<[HasV4T]>; 3756 3757 let mayStore = 1, neverHasSideEffects = 1 in 3758 def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs), 3759 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3760 IntRegs:$src2), 3761 "if (!$src1) memh(##$global+$offset) = $src2.new", 3762 []>, 3763 Requires<[HasV4T]>; 3764 3765 let mayStore = 1, neverHasSideEffects = 1 in 3766 def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs), 3767 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3768 IntRegs:$src2), 3769 "if ($src1.new) memh(##$global+$offset) = $src2.new", 3770 []>, 3771 Requires<[HasV4T]>; 3772 3773 let mayStore = 1, neverHasSideEffects = 1 in 3774 def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3775 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3776 IntRegs:$src2), 3777 "if (!$src1.new) memh(##$global+$offset) = $src2.new", 3778 []>, 3779 Requires<[HasV4T]>; 3780 3781 let mayStore = 1, neverHasSideEffects = 1 in 3782 def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs), 3783 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3784 IntRegs:$src2), 3785 "if ($src1) memw(##$global+$offset) = $src2.new", 3786 []>, 3787 Requires<[HasV4T]>; 3788 3789 let mayStore = 1, neverHasSideEffects = 1 in 3790 def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs), 3791 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3792 IntRegs:$src2), 3793 "if (!$src1) memw(##$global+$offset) = $src2.new", 3794 []>, 3795 Requires<[HasV4T]>; 3796 3797 let mayStore = 1, neverHasSideEffects = 1 in 3798 def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs), 3799 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3800 IntRegs:$src2), 3801 "if ($src1.new) memw(##$global+$offset) = $src2.new", 3802 []>, 3803 Requires<[HasV4T]>; 3804 3805 let mayStore = 1, neverHasSideEffects = 1 in 3806 def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs), 3807 (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset, 3808 IntRegs:$src2), 3809 "if (!$src1.new) memw(##$global+$offset) = $src2.new", 3810 []>, 3811 Requires<[HasV4T]>; 3812 3813 //===----------------------------------------------------------------------===// 3814 // NV/ST - 3815 //===----------------------------------------------------------------------===// 3816 3817 //===----------------------------------------------------------------------===// 3818 // NV/J + 3819 //===----------------------------------------------------------------------===// 3820 3821 multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> { 3822 def _ie_nv_V4 : NVInst_V4<(outs), 3823 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), 3824 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3825 !strconcat("($src1.new, $src2)) jump:", 3826 !strconcat(TakenStr, " $offset"))))), 3827 []>, 3828 Requires<[HasV4T]>; 3829 3830 def _nv_V4 : NVInst_V4<(outs), 3831 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), 3832 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3833 !strconcat("($src1.new, $src2)) jump:", 3834 !strconcat(TakenStr, " $offset"))))), 3835 []>, 3836 Requires<[HasV4T]>; 3837 } 3838 3839 multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr, 3840 string TakenStr> { 3841 def _ie_nv_V4 : NVInst_V4<(outs), 3842 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), 3843 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3844 !strconcat("($src1, $src2.new)) jump:", 3845 !strconcat(TakenStr, " $offset"))))), 3846 []>, 3847 Requires<[HasV4T]>; 3848 3849 def _nv_V4 : NVInst_V4<(outs), 3850 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), 3851 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3852 !strconcat("($src1, $src2.new)) jump:", 3853 !strconcat(TakenStr, " $offset"))))), 3854 []>, 3855 Requires<[HasV4T]>; 3856 } 3857 3858 multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> { 3859 def _ie_nv_V4 : NVInst_V4<(outs), 3860 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset), 3861 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3862 !strconcat("($src1.new, #$src2)) jump:", 3863 !strconcat(TakenStr, " $offset"))))), 3864 []>, 3865 Requires<[HasV4T]>; 3866 3867 def _nv_V4 : NVInst_V4<(outs), 3868 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset), 3869 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3870 !strconcat("($src1.new, #$src2)) jump:", 3871 !strconcat(TakenStr, " $offset"))))), 3872 []>, 3873 Requires<[HasV4T]>; 3874 } 3875 3876 multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> { 3877 def _ie_nv_V4 : NVInst_V4<(outs), 3878 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset), 3879 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3880 !strconcat("($src1.new, #$src2)) jump:", 3881 !strconcat(TakenStr, " $offset"))))), 3882 []>, 3883 Requires<[HasV4T]>; 3884 3885 def _nv_V4 : NVInst_V4<(outs), 3886 (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset), 3887 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3888 !strconcat("($src1.new, #$src2)) jump:", 3889 !strconcat(TakenStr, " $offset"))))), 3890 []>, 3891 Requires<[HasV4T]>; 3892 } 3893 3894 multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr, 3895 string TakenStr> { 3896 def _ie_nv_V4 : NVInst_V4<(outs), 3897 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset), 3898 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3899 !strconcat("($src1.new, #$src2)) jump:", 3900 !strconcat(TakenStr, " $offset"))))), 3901 []>, 3902 Requires<[HasV4T]>; 3903 3904 def _nv_V4 : NVInst_V4<(outs), 3905 (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset), 3906 !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, 3907 !strconcat("($src1.new, #$src2)) jump:", 3908 !strconcat(TakenStr, " $offset"))))), 3909 []>, 3910 Requires<[HasV4T]>; 3911 } 3912 3913 // Multiclass for regular dot new of Ist operand register. 3914 multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> { 3915 defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">; 3916 defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">; 3917 } 3918 3919 // Multiclass for dot new of 2nd operand register. 3920 multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> { 3921 defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">; 3922 defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">; 3923 } 3924 3925 // Multiclass for 2nd operand immediate, including -1. 3926 multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> { 3927 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">; 3928 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">; 3929 defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">; 3930 defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">; 3931 } 3932 3933 // Multiclass for 2nd operand immediate, excluding -1. 3934 multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> { 3935 defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">; 3936 defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">; 3937 } 3938 3939 // Multiclass for tstbit, where 2nd operand is always #0. 3940 multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> { 3941 defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">; 3942 defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">; 3943 } 3944 3945 // Multiclass for GT. 3946 multiclass NVJ_type_rr_ri<string OpcStr> { 3947 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>; 3948 defm rr : NVJ_type_br_pred_reg<"", OpcStr>; 3949 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>; 3950 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>; 3951 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>; 3952 defm ri : NVJ_type_br_pred_imm<"", OpcStr>; 3953 } 3954 3955 // Multiclass for EQ. 3956 multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> { 3957 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>; 3958 defm rr : NVJ_type_br_pred_reg<"", OpcStr>; 3959 defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>; 3960 defm ri : NVJ_type_br_pred_imm<"", OpcStr>; 3961 } 3962 3963 // Multiclass for GTU. 3964 multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> { 3965 defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>; 3966 defm rr : NVJ_type_br_pred_reg<"", OpcStr>; 3967 defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>; 3968 defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>; 3969 defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>; 3970 defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>; 3971 } 3972 3973 // Multiclass for tstbit. 3974 multiclass NVJ_type_r0<string OpcStr> { 3975 defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>; 3976 defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>; 3977 } 3978 3979 // Base Multiclass for New Value Jump. 3980 multiclass NVJ_type { 3981 defm GT : NVJ_type_rr_ri<"cmp.gt">; 3982 defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">; 3983 defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">; 3984 defm TSTBIT : NVJ_type_r0<"tstbit">; 3985 } 3986 3987 let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in { 3988 defm JMP_ : NVJ_type; 3989 } 3990 3991 //===----------------------------------------------------------------------===// 3992 // NV/J - 3993 //===----------------------------------------------------------------------===// 3994 3995 //===----------------------------------------------------------------------===// 3996 // XTYPE/ALU + 3997 //===----------------------------------------------------------------------===// 3998 3999 // Add and accumulate. 4000 // Rd=add(Rs,add(Ru,#s6)) 4001 def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst), 4002 (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3), 4003 "$dst = add($src1, add($src2, #$src3))", 4004 [(set (i32 IntRegs:$dst), 4005 (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2), 4006 s6ImmPred:$src3)))]>, 4007 Requires<[HasV4T]>; 4008 4009 // Rd=add(Rs,sub(#s6,Ru)) 4010 def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst), 4011 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3), 4012 "$dst = add($src1, sub(#$src2, $src3))", 4013 [(set (i32 IntRegs:$dst), 4014 (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2, 4015 (i32 IntRegs:$src3))))]>, 4016 Requires<[HasV4T]>; 4017 4018 // Generates the same instruction as ADDr_SUBri_V4 but matches different 4019 // pattern. 4020 // Rd=add(Rs,sub(#s6,Ru)) 4021 def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst), 4022 (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3), 4023 "$dst = add($src1, sub(#$src2, $src3))", 4024 [(set (i32 IntRegs:$dst), 4025 (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2), 4026 (i32 IntRegs:$src3)))]>, 4027 Requires<[HasV4T]>; 4028 4029 4030 // Add or subtract doublewords with carry. 4031 //TODO: 4032 // Rdd=add(Rss,Rtt,Px):carry 4033 //TODO: 4034 // Rdd=sub(Rss,Rtt,Px):carry 4035 4036 4037 // Logical doublewords. 4038 // Rdd=and(Rtt,~Rss) 4039 def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst), 4040 (ins DoubleRegs:$src1, DoubleRegs:$src2), 4041 "$dst = and($src1, ~$src2)", 4042 [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1), 4043 (not (i64 DoubleRegs:$src2))))]>, 4044 Requires<[HasV4T]>; 4045 4046 // Rdd=or(Rtt,~Rss) 4047 def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst), 4048 (ins DoubleRegs:$src1, DoubleRegs:$src2), 4049 "$dst = or($src1, ~$src2)", 4050 [(set (i64 DoubleRegs:$dst), 4051 (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>, 4052 Requires<[HasV4T]>; 4053 4054 4055 // Logical-logical doublewords. 4056 // Rxx^=xor(Rss,Rtt) 4057 def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst), 4058 (ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), 4059 "$dst ^= xor($src2, $src3)", 4060 [(set (i64 DoubleRegs:$dst), 4061 (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2), 4062 (i64 DoubleRegs:$src3))))], 4063 "$src1 = $dst">, 4064 Requires<[HasV4T]>; 4065 4066 4067 // Logical-logical words. 4068 // Rx=or(Ru,and(Rx,#s10)) 4069 def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst), 4070 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3), 4071 "$dst = or($src1, and($src2, #$src3))", 4072 [(set (i32 IntRegs:$dst), 4073 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4074 s10ImmPred:$src3)))], 4075 "$src2 = $dst">, 4076 Requires<[HasV4T]>; 4077 4078 // Rx[&|^]=and(Rs,Rt) 4079 // Rx&=and(Rs,Rt) 4080 def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst), 4081 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4082 "$dst &= and($src2, $src3)", 4083 [(set (i32 IntRegs:$dst), 4084 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4085 (i32 IntRegs:$src3))))], 4086 "$src1 = $dst">, 4087 Requires<[HasV4T]>; 4088 4089 // Rx|=and(Rs,Rt) 4090 def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst), 4091 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4092 "$dst |= and($src2, $src3)", 4093 [(set (i32 IntRegs:$dst), 4094 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4095 (i32 IntRegs:$src3))))], 4096 "$src1 = $dst">, 4097 Requires<[HasV4T]>; 4098 4099 // Rx^=and(Rs,Rt) 4100 def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst), 4101 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4102 "$dst ^= and($src2, $src3)", 4103 [(set (i32 IntRegs:$dst), 4104 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4105 (i32 IntRegs:$src3))))], 4106 "$src1 = $dst">, 4107 Requires<[HasV4T]>; 4108 4109 // Rx[&|^]=and(Rs,~Rt) 4110 // Rx&=and(Rs,~Rt) 4111 def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst), 4112 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4113 "$dst &= and($src2, ~$src3)", 4114 [(set (i32 IntRegs:$dst), 4115 (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4116 (not (i32 IntRegs:$src3)))))], 4117 "$src1 = $dst">, 4118 Requires<[HasV4T]>; 4119 4120 // Rx|=and(Rs,~Rt) 4121 def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst), 4122 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4123 "$dst |= and($src2, ~$src3)", 4124 [(set (i32 IntRegs:$dst), 4125 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4126 (not (i32 IntRegs:$src3)))))], 4127 "$src1 = $dst">, 4128 Requires<[HasV4T]>; 4129 4130 // Rx^=and(Rs,~Rt) 4131 def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst), 4132 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4133 "$dst ^= and($src2, ~$src3)", 4134 [(set (i32 IntRegs:$dst), 4135 (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4136 (not (i32 IntRegs:$src3)))))], 4137 "$src1 = $dst">, 4138 Requires<[HasV4T]>; 4139 4140 // Rx[&|^]=or(Rs,Rt) 4141 // Rx&=or(Rs,Rt) 4142 def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst), 4143 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4144 "$dst &= or($src2, $src3)", 4145 [(set (i32 IntRegs:$dst), 4146 (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2), 4147 (i32 IntRegs:$src3))))], 4148 "$src1 = $dst">, 4149 Requires<[HasV4T]>; 4150 4151 // Rx|=or(Rs,Rt) 4152 def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst), 4153 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4154 "$dst |= or($src2, $src3)", 4155 [(set (i32 IntRegs:$dst), 4156 (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2), 4157 (i32 IntRegs:$src3))))], 4158 "$src1 = $dst">, 4159 Requires<[HasV4T]>; 4160 4161 // Rx^=or(Rs,Rt) 4162 def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst), 4163 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4164 "$dst ^= or($src2, $src3)", 4165 [(set (i32 IntRegs:$dst), 4166 (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2), 4167 (i32 IntRegs:$src3))))], 4168 "$src1 = $dst">, 4169 Requires<[HasV4T]>; 4170 4171 // Rx[&|^]=xor(Rs,Rt) 4172 // Rx&=xor(Rs,Rt) 4173 def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst), 4174 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4175 "$dst &= xor($src2, $src3)", 4176 [(set (i32 IntRegs:$dst), 4177 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2), 4178 (i32 IntRegs:$src3))))], 4179 "$src1 = $dst">, 4180 Requires<[HasV4T]>; 4181 4182 // Rx|=xor(Rs,Rt) 4183 def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst), 4184 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4185 "$dst |= xor($src2, $src3)", 4186 [(set (i32 IntRegs:$dst), 4187 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2), 4188 (i32 IntRegs:$src3))))], 4189 "$src1 = $dst">, 4190 Requires<[HasV4T]>; 4191 4192 // Rx^=xor(Rs,Rt) 4193 def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst), 4194 (ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3), 4195 "$dst ^= xor($src2, $src3)", 4196 [(set (i32 IntRegs:$dst), 4197 (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2), 4198 (i32 IntRegs:$src3))))], 4199 "$src1 = $dst">, 4200 Requires<[HasV4T]>; 4201 4202 // Rx|=and(Rs,#s10) 4203 def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst), 4204 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3), 4205 "$dst |= and($src2, #$src3)", 4206 [(set (i32 IntRegs:$dst), 4207 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4208 s10ImmPred:$src3)))], 4209 "$src1 = $dst">, 4210 Requires<[HasV4T]>; 4211 4212 // Rx|=or(Rs,#s10) 4213 def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst), 4214 (ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3), 4215 "$dst |= or($src2, #$src3)", 4216 [(set (i32 IntRegs:$dst), 4217 (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2), 4218 s10ImmPred:$src3)))], 4219 "$src1 = $dst">, 4220 Requires<[HasV4T]>; 4221 4222 4223 // Modulo wrap 4224 // Rd=modwrap(Rs,Rt) 4225 // Round 4226 // Rd=cround(Rs,#u5) 4227 // Rd=cround(Rs,Rt) 4228 // Rd=round(Rs,#u5)[:sat] 4229 // Rd=round(Rs,Rt)[:sat] 4230 // Vector reduce add unsigned halfwords 4231 // Rd=vraddh(Rss,Rtt) 4232 // Vector add bytes 4233 // Rdd=vaddb(Rss,Rtt) 4234 // Vector conditional negate 4235 // Rdd=vcnegh(Rss,Rt) 4236 // Rxx+=vrcnegh(Rss,Rt) 4237 // Vector maximum bytes 4238 // Rdd=vmaxb(Rtt,Rss) 4239 // Vector reduce maximum halfwords 4240 // Rxx=vrmaxh(Rss,Ru) 4241 // Rxx=vrmaxuh(Rss,Ru) 4242 // Vector reduce maximum words 4243 // Rxx=vrmaxuw(Rss,Ru) 4244 // Rxx=vrmaxw(Rss,Ru) 4245 // Vector minimum bytes 4246 // Rdd=vminb(Rtt,Rss) 4247 // Vector reduce minimum halfwords 4248 // Rxx=vrminh(Rss,Ru) 4249 // Rxx=vrminuh(Rss,Ru) 4250 // Vector reduce minimum words 4251 // Rxx=vrminuw(Rss,Ru) 4252 // Rxx=vrminw(Rss,Ru) 4253 // Vector subtract bytes 4254 // Rdd=vsubb(Rss,Rtt) 4255 4256 //===----------------------------------------------------------------------===// 4257 // XTYPE/ALU - 4258 //===----------------------------------------------------------------------===// 4259 4260 4261 //===----------------------------------------------------------------------===// 4262 // XTYPE/MPY + 4263 //===----------------------------------------------------------------------===// 4264 4265 // Multiply and user lower result. 4266 // Rd=add(#u6,mpyi(Rs,#U6)) 4267 def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst), 4268 (ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3), 4269 "$dst = add(#$src1, mpyi($src2, #$src3))", 4270 [(set (i32 IntRegs:$dst), 4271 (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3), 4272 u6ImmPred:$src1))]>, 4273 Requires<[HasV4T]>; 4274 4275 // Rd=add(#u6,mpyi(Rs,Rt)) 4276 4277 def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst), 4278 (ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3), 4279 "$dst = add(#$src1, mpyi($src2, $src3))", 4280 [(set (i32 IntRegs:$dst), 4281 (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)), 4282 u6ImmPred:$src1))]>, 4283 Requires<[HasV4T]>; 4284 4285 // Rd=add(Ru,mpyi(#u6:2,Rs)) 4286 def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst), 4287 (ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3), 4288 "$dst = add($src1, mpyi(#$src2, $src3))", 4289 [(set (i32 IntRegs:$dst), 4290 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3), 4291 u6_2ImmPred:$src2)))]>, 4292 Requires<[HasV4T]>; 4293 4294 // Rd=add(Ru,mpyi(Rs,#u6)) 4295 def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst), 4296 (ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3), 4297 "$dst = add($src1, mpyi($src2, #$src3))", 4298 [(set (i32 IntRegs:$dst), 4299 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2), 4300 u6ImmPred:$src3)))]>, 4301 Requires<[HasV4T]>; 4302 4303 // Rx=add(Ru,mpyi(Rx,Rs)) 4304 def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst), 4305 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), 4306 "$dst = add($src1, mpyi($src2, $src3))", 4307 [(set (i32 IntRegs:$dst), 4308 (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2), 4309 (i32 IntRegs:$src3))))], 4310 "$src2 = $dst">, 4311 Requires<[HasV4T]>; 4312 4313 4314 // Polynomial multiply words 4315 // Rdd=pmpyw(Rs,Rt) 4316 // Rxx^=pmpyw(Rs,Rt) 4317 4318 // Vector reduce multiply word by signed half (32x16) 4319 // Rdd=vrmpyweh(Rss,Rtt)[:<<1] 4320 // Rdd=vrmpywoh(Rss,Rtt)[:<<1] 4321 // Rxx+=vrmpyweh(Rss,Rtt)[:<<1] 4322 // Rxx+=vrmpywoh(Rss,Rtt)[:<<1] 4323 4324 // Multiply and use upper result 4325 // Rd=mpy(Rs,Rt.H):<<1:sat 4326 // Rd=mpy(Rs,Rt.L):<<1:sat 4327 // Rd=mpy(Rs,Rt):<<1 4328 // Rd=mpy(Rs,Rt):<<1:sat 4329 // Rd=mpysu(Rs,Rt) 4330 // Rx+=mpy(Rs,Rt):<<1:sat 4331 // Rx-=mpy(Rs,Rt):<<1:sat 4332 4333 // Vector multiply bytes 4334 // Rdd=vmpybsu(Rs,Rt) 4335 // Rdd=vmpybu(Rs,Rt) 4336 // Rxx+=vmpybsu(Rs,Rt) 4337 // Rxx+=vmpybu(Rs,Rt) 4338 4339 // Vector polynomial multiply halfwords 4340 // Rdd=vpmpyh(Rs,Rt) 4341 // Rxx^=vpmpyh(Rs,Rt) 4342 4343 //===----------------------------------------------------------------------===// 4344 // XTYPE/MPY - 4345 //===----------------------------------------------------------------------===// 4346 4347 4348 //===----------------------------------------------------------------------===// 4349 // XTYPE/SHIFT + 4350 //===----------------------------------------------------------------------===// 4351 4352 // Shift by immediate and accumulate. 4353 // Rx=add(#u8,asl(Rx,#U5)) 4354 def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), 4355 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4356 "$dst = add(#$src1, asl($src2, #$src3))", 4357 [(set (i32 IntRegs:$dst), 4358 (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3), 4359 u8ImmPred:$src1))], 4360 "$src2 = $dst">, 4361 Requires<[HasV4T]>; 4362 4363 // Rx=add(#u8,lsr(Rx,#U5)) 4364 def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), 4365 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4366 "$dst = add(#$src1, lsr($src2, #$src3))", 4367 [(set (i32 IntRegs:$dst), 4368 (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3), 4369 u8ImmPred:$src1))], 4370 "$src2 = $dst">, 4371 Requires<[HasV4T]>; 4372 4373 // Rx=sub(#u8,asl(Rx,#U5)) 4374 def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), 4375 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4376 "$dst = sub(#$src1, asl($src2, #$src3))", 4377 [(set (i32 IntRegs:$dst), 4378 (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3), 4379 u8ImmPred:$src1))], 4380 "$src2 = $dst">, 4381 Requires<[HasV4T]>; 4382 4383 // Rx=sub(#u8,lsr(Rx,#U5)) 4384 def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), 4385 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4386 "$dst = sub(#$src1, lsr($src2, #$src3))", 4387 [(set (i32 IntRegs:$dst), 4388 (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3), 4389 u8ImmPred:$src1))], 4390 "$src2 = $dst">, 4391 Requires<[HasV4T]>; 4392 4393 4394 //Shift by immediate and logical. 4395 //Rx=and(#u8,asl(Rx,#U5)) 4396 def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), 4397 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4398 "$dst = and(#$src1, asl($src2, #$src3))", 4399 [(set (i32 IntRegs:$dst), 4400 (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3), 4401 u8ImmPred:$src1))], 4402 "$src2 = $dst">, 4403 Requires<[HasV4T]>; 4404 4405 //Rx=and(#u8,lsr(Rx,#U5)) 4406 def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), 4407 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4408 "$dst = and(#$src1, lsr($src2, #$src3))", 4409 [(set (i32 IntRegs:$dst), 4410 (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3), 4411 u8ImmPred:$src1))], 4412 "$src2 = $dst">, 4413 Requires<[HasV4T]>; 4414 4415 //Rx=or(#u8,asl(Rx,#U5)) 4416 let AddedComplexity = 30 in 4417 def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), 4418 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4419 "$dst = or(#$src1, asl($src2, #$src3))", 4420 [(set (i32 IntRegs:$dst), 4421 (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3), 4422 u8ImmPred:$src1))], 4423 "$src2 = $dst">, 4424 Requires<[HasV4T]>; 4425 4426 //Rx=or(#u8,lsr(Rx,#U5)) 4427 let AddedComplexity = 30 in 4428 def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), 4429 (ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3), 4430 "$dst = or(#$src1, lsr($src2, #$src3))", 4431 [(set (i32 IntRegs:$dst), 4432 (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3), 4433 u8ImmPred:$src1))], 4434 "$src2 = $dst">, 4435 Requires<[HasV4T]>; 4436 4437 4438 //Shift by register. 4439 //Rd=lsl(#s6,Rt) 4440 def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2), 4441 "$dst = lsl(#$src1, $src2)", 4442 [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1, 4443 (i32 IntRegs:$src2)))]>, 4444 Requires<[HasV4T]>; 4445 4446 4447 //Shift by register and logical. 4448 //Rxx^=asl(Rss,Rt) 4449 def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), 4450 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), 4451 "$dst ^= asl($src2, $src3)", 4452 [(set (i64 DoubleRegs:$dst), 4453 (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2), 4454 (i32 IntRegs:$src3))))], 4455 "$src1 = $dst">, 4456 Requires<[HasV4T]>; 4457 4458 //Rxx^=asr(Rss,Rt) 4459 def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), 4460 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), 4461 "$dst ^= asr($src2, $src3)", 4462 [(set (i64 DoubleRegs:$dst), 4463 (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2), 4464 (i32 IntRegs:$src3))))], 4465 "$src1 = $dst">, 4466 Requires<[HasV4T]>; 4467 4468 //Rxx^=lsl(Rss,Rt) 4469 def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), 4470 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), 4471 "$dst ^= lsl($src2, $src3)", 4472 [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1), 4473 (shl (i64 DoubleRegs:$src2), 4474 (i32 IntRegs:$src3))))], 4475 "$src1 = $dst">, 4476 Requires<[HasV4T]>; 4477 4478 //Rxx^=lsr(Rss,Rt) 4479 def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), 4480 (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), 4481 "$dst ^= lsr($src2, $src3)", 4482 [(set (i64 DoubleRegs:$dst), 4483 (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2), 4484 (i32 IntRegs:$src3))))], 4485 "$src1 = $dst">, 4486 Requires<[HasV4T]>; 4487 4488 4489 //===----------------------------------------------------------------------===// 4490 // XTYPE/SHIFT - 4491 //===----------------------------------------------------------------------===// 4492 4493 //===----------------------------------------------------------------------===// 4494 // MEMOP: Word, Half, Byte 4495 //===----------------------------------------------------------------------===// 4496 4497 //===----------------------------------------------------------------------===// 4498 // MEMOP: Word 4499 // 4500 // Implemented: 4501 // MEMw_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5 4502 // MEMw_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5 4503 // MEMw_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt 4504 // MEMw_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt 4505 // MEMw_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt 4506 // MEMw_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt 4507 // MEMw_ADDi_V4 : memw(Rs+#u6:2)+=#U5 4508 // MEMw_SUBi_V4 : memw(Rs+#u6:2)-=#U5 4509 // MEMw_ADDr_V4 : memw(Rs+#u6:2)+=Rt 4510 // MEMw_SUBr_V4 : memw(Rs+#u6:2)-=Rt 4511 // MEMw_CLRr_V4 : memw(Rs+#u6:2)&=Rt 4512 // MEMw_SETr_V4 : memw(Rs+#u6:2)|=Rt 4513 // 4514 // Not implemented: 4515 // MEMw_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5) 4516 // MEMw_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5) 4517 // MEMw_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5) 4518 // MEMw_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5) 4519 //===----------------------------------------------------------------------===// 4520 4521 4522 // MEMw_ADDSUBi_indexed_V4: 4523 // pseudo operation for MEMw_ADDi_indexed_V4 and 4524 // MEMw_SUBi_indexed_V4 a later pass will change it 4525 // to the corresponding pattern. 4526 let AddedComplexity = 30 in 4527 def MEMw_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs), 4528 (ins IntRegs:$base, u6_2Imm:$offset, m6Imm:$addend), 4529 "Error; should not emit", 4530 [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)), 4531 m6ImmPred:$addend), 4532 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>, 4533 Requires<[HasV4T, UseMEMOP]>; 4534 4535 // memw(Rs+#u6:2) += #U5 4536 let AddedComplexity = 30 in 4537 def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs), 4538 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend), 4539 "memw($base+#$offset) += #$addend", 4540 []>, 4541 Requires<[HasV4T, UseMEMOP]>; 4542 4543 // memw(Rs+#u6:2) -= #U5 4544 let AddedComplexity = 30 in 4545 def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs), 4546 (ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend), 4547 "memw($base+#$offset) -= #$subend", 4548 []>, 4549 Requires<[HasV4T, UseMEMOP]>; 4550 4551 // memw(Rs+#u6:2) += Rt 4552 let AddedComplexity = 30 in 4553 def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs), 4554 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend), 4555 "memw($base+#$offset) += $addend", 4556 [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)), 4557 (i32 IntRegs:$addend)), 4558 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>, 4559 Requires<[HasV4T, UseMEMOP]>; 4560 4561 // memw(Rs+#u6:2) -= Rt 4562 let AddedComplexity = 30 in 4563 def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs), 4564 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend), 4565 "memw($base+#$offset) -= $subend", 4566 [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)), 4567 (i32 IntRegs:$subend)), 4568 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>, 4569 Requires<[HasV4T, UseMEMOP]>; 4570 4571 // memw(Rs+#u6:2) &= Rt 4572 let AddedComplexity = 30 in 4573 def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs), 4574 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend), 4575 "memw($base+#$offset) &= $andend", 4576 [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)), 4577 (i32 IntRegs:$andend)), 4578 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>, 4579 Requires<[HasV4T, UseMEMOP]>; 4580 4581 // memw(Rs+#u6:2) |= Rt 4582 let AddedComplexity = 30 in 4583 def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs), 4584 (ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend), 4585 "memw($base+#$offset) |= $orend", 4586 [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)), 4587 (i32 IntRegs:$orend)), 4588 (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>, 4589 Requires<[HasV4T, UseMEMOP]>; 4590 4591 // MEMw_ADDSUBi_V4: 4592 // Pseudo operation for MEMw_ADDi_V4 and MEMw_SUBi_V4 4593 // a later pass will change it to the right pattern. 4594 let AddedComplexity = 30 in 4595 def MEMw_ADDSUBi_MEM_V4 : MEMInst_V4<(outs), 4596 (ins MEMri:$addr, m6Imm:$addend), 4597 "Error; should not emit", 4598 [(store (add (load ADDRriU6_2:$addr), m6ImmPred:$addend), 4599 ADDRriU6_2:$addr)]>, 4600 Requires<[HasV4T, UseMEMOP]>; 4601 4602 // memw(Rs+#u6:2) += #U5 4603 let AddedComplexity = 30 in 4604 def MEMw_ADDi_MEM_V4 : MEMInst_V4<(outs), 4605 (ins MEMri:$addr, u5Imm:$addend), 4606 "memw($addr) += $addend", 4607 []>, 4608 Requires<[HasV4T, UseMEMOP]>; 4609 4610 // memw(Rs+#u6:2) -= #U5 4611 let AddedComplexity = 30 in 4612 def MEMw_SUBi_MEM_V4 : MEMInst_V4<(outs), 4613 (ins MEMri:$addr, u5Imm:$subend), 4614 "memw($addr) -= $subend", 4615 []>, 4616 Requires<[HasV4T, UseMEMOP]>; 4617 4618 // memw(Rs+#u6:2) += Rt 4619 let AddedComplexity = 30 in 4620 def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs), 4621 (ins MEMri:$addr, IntRegs:$addend), 4622 "memw($addr) += $addend", 4623 [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)), 4624 ADDRriU6_2:$addr)]>, 4625 Requires<[HasV4T, UseMEMOP]>; 4626 4627 // memw(Rs+#u6:2) -= Rt 4628 let AddedComplexity = 30 in 4629 def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs), 4630 (ins MEMri:$addr, IntRegs:$subend), 4631 "memw($addr) -= $subend", 4632 [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)), 4633 ADDRriU6_2:$addr)]>, 4634 Requires<[HasV4T, UseMEMOP]>; 4635 4636 // memw(Rs+#u6:2) &= Rt 4637 let AddedComplexity = 30 in 4638 def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs), 4639 (ins MEMri:$addr, IntRegs:$andend), 4640 "memw($addr) &= $andend", 4641 [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)), 4642 ADDRriU6_2:$addr)]>, 4643 Requires<[HasV4T, UseMEMOP]>; 4644 4645 // memw(Rs+#u6:2) |= Rt 4646 let AddedComplexity = 30 in 4647 def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs), 4648 (ins MEMri:$addr, IntRegs:$orend), 4649 "memw($addr) |= $orend", 4650 [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)), 4651 ADDRriU6_2:$addr)]>, 4652 Requires<[HasV4T, UseMEMOP]>; 4653 4654 //===----------------------------------------------------------------------===// 4655 // MEMOP: Halfword 4656 // 4657 // Implemented: 4658 // MEMh_ADDi_indexed_V4 : memw(Rs+#u6:2)+=#U5 4659 // MEMh_SUBi_indexed_V4 : memw(Rs+#u6:2)-=#U5 4660 // MEMh_ADDr_indexed_V4 : memw(Rs+#u6:2)+=Rt 4661 // MEMh_SUBr_indexed_V4 : memw(Rs+#u6:2)-=Rt 4662 // MEMh_CLRr_indexed_V4 : memw(Rs+#u6:2)&=Rt 4663 // MEMh_SETr_indexed_V4 : memw(Rs+#u6:2)|=Rt 4664 // MEMh_ADDi_V4 : memw(Rs+#u6:2)+=#U5 4665 // MEMh_SUBi_V4 : memw(Rs+#u6:2)-=#U5 4666 // MEMh_ADDr_V4 : memw(Rs+#u6:2)+=Rt 4667 // MEMh_SUBr_V4 : memw(Rs+#u6:2)-=Rt 4668 // MEMh_CLRr_V4 : memw(Rs+#u6:2)&=Rt 4669 // MEMh_SETr_V4 : memw(Rs+#u6:2)|=Rt 4670 // 4671 // Not implemented: 4672 // MEMh_CLRi_indexed_V4 : memw(Rs+#u6:2)=clrbit(#U5) 4673 // MEMh_SETi_indexed_V4 : memw(Rs+#u6:2)=setbit(#U5) 4674 // MEMh_CLRi_V4 : memw(Rs+#u6:2)=clrbit(#U5) 4675 // MEMh_SETi_V4 : memw(Rs+#u6:2)=setbit(#U5) 4676 //===----------------------------------------------------------------------===// 4677 4678 4679 // MEMh_ADDSUBi_indexed_V4: 4680 // Pseudo operation for MEMh_ADDi_indexed_V4 and 4681 // MEMh_SUBi_indexed_V4 a later pass will change it 4682 // to the corresponding pattern. 4683 let AddedComplexity = 30 in 4684 def MEMh_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs), 4685 (ins IntRegs:$base, u6_1Imm:$offset, m6Imm:$addend), 4686 "Error; should not emit", 4687 [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base), 4688 u6_1ImmPred:$offset)), 4689 m6ImmPred:$addend), 4690 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>, 4691 Requires<[HasV4T, UseMEMOP]>; 4692 4693 // memh(Rs+#u6:1) += #U5 4694 let AddedComplexity = 30 in 4695 def MEMh_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs), 4696 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$addend), 4697 "memh($base+#$offset) += $addend", 4698 []>, 4699 Requires<[HasV4T, UseMEMOP]>; 4700 4701 // memh(Rs+#u6:1) -= #U5 4702 let AddedComplexity = 30 in 4703 def MEMh_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs), 4704 (ins IntRegs:$base, u6_1Imm:$offset, u5Imm:$subend), 4705 "memh($base+#$offset) -= $subend", 4706 []>, 4707 Requires<[HasV4T, UseMEMOP]>; 4708 4709 // memh(Rs+#u6:1) += Rt 4710 let AddedComplexity = 30 in 4711 def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs), 4712 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend), 4713 "memh($base+#$offset) += $addend", 4714 [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base), 4715 u6_1ImmPred:$offset)), 4716 (i32 IntRegs:$addend)), 4717 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>, 4718 Requires<[HasV4T, UseMEMOP]>; 4719 4720 // memh(Rs+#u6:1) -= Rt 4721 let AddedComplexity = 30 in 4722 def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs), 4723 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend), 4724 "memh($base+#$offset) -= $subend", 4725 [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base), 4726 u6_1ImmPred:$offset)), 4727 (i32 IntRegs:$subend)), 4728 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>, 4729 Requires<[HasV4T, UseMEMOP]>; 4730 4731 // memh(Rs+#u6:1) &= Rt 4732 let AddedComplexity = 30 in 4733 def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs), 4734 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend), 4735 "memh($base+#$offset) += $andend", 4736 [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base), 4737 u6_1ImmPred:$offset)), 4738 (i32 IntRegs:$andend)), 4739 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>, 4740 Requires<[HasV4T, UseMEMOP]>; 4741 4742 // memh(Rs+#u6:1) |= Rt 4743 let AddedComplexity = 30 in 4744 def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs), 4745 (ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend), 4746 "memh($base+#$offset) |= $orend", 4747 [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base), 4748 u6_1ImmPred:$offset)), 4749 (i32 IntRegs:$orend)), 4750 (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>, 4751 Requires<[HasV4T, UseMEMOP]>; 4752 4753 // MEMh_ADDSUBi_V4: 4754 // Pseudo operation for MEMh_ADDi_V4 and MEMh_SUBi_V4 4755 // a later pass will change it to the right pattern. 4756 let AddedComplexity = 30 in 4757 def MEMh_ADDSUBi_MEM_V4 : MEMInst_V4<(outs), 4758 (ins MEMri:$addr, m6Imm:$addend), 4759 "Error; should not emit", 4760 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr), 4761 m6ImmPred:$addend), ADDRriU6_1:$addr)]>, 4762 Requires<[HasV4T, UseMEMOP]>; 4763 4764 // memh(Rs+#u6:1) += #U5 4765 let AddedComplexity = 30 in 4766 def MEMh_ADDi_MEM_V4 : MEMInst_V4<(outs), 4767 (ins MEMri:$addr, u5Imm:$addend), 4768 "memh($addr) += $addend", 4769 []>, 4770 Requires<[HasV4T, UseMEMOP]>; 4771 4772 // memh(Rs+#u6:1) -= #U5 4773 let AddedComplexity = 30 in 4774 def MEMh_SUBi_MEM_V4 : MEMInst_V4<(outs), 4775 (ins MEMri:$addr, u5Imm:$subend), 4776 "memh($addr) -= $subend", 4777 []>, 4778 Requires<[HasV4T, UseMEMOP]>; 4779 4780 // memh(Rs+#u6:1) += Rt 4781 let AddedComplexity = 30 in 4782 def MEMh_ADDr_MEM_V4 : MEMInst_V4<(outs), 4783 (ins MEMri:$addr, IntRegs:$addend), 4784 "memh($addr) += $addend", 4785 [(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr), 4786 (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>, 4787 Requires<[HasV4T, UseMEMOP]>; 4788 4789 // memh(Rs+#u6:1) -= Rt 4790 let AddedComplexity = 30 in 4791 def MEMh_SUBr_MEM_V4 : MEMInst_V4<(outs), 4792 (ins MEMri:$addr, IntRegs:$subend), 4793 "memh($addr) -= $subend", 4794 [(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr), 4795 (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>, 4796 Requires<[HasV4T, UseMEMOP]>; 4797 4798 // memh(Rs+#u6:1) &= Rt 4799 let AddedComplexity = 30 in 4800 def MEMh_ANDr_MEM_V4 : MEMInst_V4<(outs), 4801 (ins MEMri:$addr, IntRegs:$andend), 4802 "memh($addr) &= $andend", 4803 [(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr), 4804 (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>, 4805 Requires<[HasV4T, UseMEMOP]>; 4806 4807 // memh(Rs+#u6:1) |= Rt 4808 let AddedComplexity = 30 in 4809 def MEMh_ORr_MEM_V4 : MEMInst_V4<(outs), 4810 (ins MEMri:$addr, IntRegs:$orend), 4811 "memh($addr) |= $orend", 4812 [(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr), 4813 (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>, 4814 Requires<[HasV4T, UseMEMOP]>; 4815 4816 4817 //===----------------------------------------------------------------------===// 4818 // MEMOP: Byte 4819 // 4820 // Implemented: 4821 // MEMb_ADDi_indexed_V4 : memb(Rs+#u6:0)+=#U5 4822 // MEMb_SUBi_indexed_V4 : memb(Rs+#u6:0)-=#U5 4823 // MEMb_ADDr_indexed_V4 : memb(Rs+#u6:0)+=Rt 4824 // MEMb_SUBr_indexed_V4 : memb(Rs+#u6:0)-=Rt 4825 // MEMb_CLRr_indexed_V4 : memb(Rs+#u6:0)&=Rt 4826 // MEMb_SETr_indexed_V4 : memb(Rs+#u6:0)|=Rt 4827 // MEMb_ADDi_V4 : memb(Rs+#u6:0)+=#U5 4828 // MEMb_SUBi_V4 : memb(Rs+#u6:0)-=#U5 4829 // MEMb_ADDr_V4 : memb(Rs+#u6:0)+=Rt 4830 // MEMb_SUBr_V4 : memb(Rs+#u6:0)-=Rt 4831 // MEMb_CLRr_V4 : memb(Rs+#u6:0)&=Rt 4832 // MEMb_SETr_V4 : memb(Rs+#u6:0)|=Rt 4833 // 4834 // Not implemented: 4835 // MEMb_CLRi_indexed_V4 : memb(Rs+#u6:0)=clrbit(#U5) 4836 // MEMb_SETi_indexed_V4 : memb(Rs+#u6:0)=setbit(#U5) 4837 // MEMb_CLRi_V4 : memb(Rs+#u6:0)=clrbit(#U5) 4838 // MEMb_SETi_V4 : memb(Rs+#u6:0)=setbit(#U5) 4839 //===----------------------------------------------------------------------===// 4840 4841 4842 // MEMb_ADDSUBi_indexed_V4: 4843 // Pseudo operation for MEMb_ADDi_indexed_V4 and 4844 // MEMb_SUBi_indexed_V4 a later pass will change it 4845 // to the corresponding pattern. 4846 let AddedComplexity = 30 in 4847 def MEMb_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs), 4848 (ins IntRegs:$base, u6_0Imm:$offset, m6Imm:$addend), 4849 "Error; should not emit", 4850 [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base), 4851 u6_0ImmPred:$offset)), 4852 m6ImmPred:$addend), 4853 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>, 4854 Requires<[HasV4T, UseMEMOP]>; 4855 4856 // memb(Rs+#u6:0) += #U5 4857 let AddedComplexity = 30 in 4858 def MEMb_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs), 4859 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$addend), 4860 "memb($base+#$offset) += $addend", 4861 []>, 4862 Requires<[HasV4T, UseMEMOP]>; 4863 4864 // memb(Rs+#u6:0) -= #U5 4865 let AddedComplexity = 30 in 4866 def MEMb_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs), 4867 (ins IntRegs:$base, u6_0Imm:$offset, u5Imm:$subend), 4868 "memb($base+#$offset) -= $subend", 4869 []>, 4870 Requires<[HasV4T, UseMEMOP]>; 4871 4872 // memb(Rs+#u6:0) += Rt 4873 let AddedComplexity = 30 in 4874 def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs), 4875 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend), 4876 "memb($base+#$offset) += $addend", 4877 [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base), 4878 u6_0ImmPred:$offset)), 4879 (i32 IntRegs:$addend)), 4880 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>, 4881 Requires<[HasV4T, UseMEMOP]>; 4882 4883 // memb(Rs+#u6:0) -= Rt 4884 let AddedComplexity = 30 in 4885 def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs), 4886 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend), 4887 "memb($base+#$offset) -= $subend", 4888 [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base), 4889 u6_0ImmPred:$offset)), 4890 (i32 IntRegs:$subend)), 4891 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>, 4892 Requires<[HasV4T, UseMEMOP]>; 4893 4894 // memb(Rs+#u6:0) &= Rt 4895 let AddedComplexity = 30 in 4896 def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs), 4897 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend), 4898 "memb($base+#$offset) += $andend", 4899 [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base), 4900 u6_0ImmPred:$offset)), 4901 (i32 IntRegs:$andend)), 4902 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>, 4903 Requires<[HasV4T, UseMEMOP]>; 4904 4905 // memb(Rs+#u6:0) |= Rt 4906 let AddedComplexity = 30 in 4907 def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs), 4908 (ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend), 4909 "memb($base+#$offset) |= $orend", 4910 [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base), 4911 u6_0ImmPred:$offset)), 4912 (i32 IntRegs:$orend)), 4913 (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>, 4914 Requires<[HasV4T, UseMEMOP]>; 4915 4916 // MEMb_ADDSUBi_V4: 4917 // Pseudo operation for MEMb_ADDi_V4 and MEMb_SUBi_V4 4918 // a later pass will change it to the right pattern. 4919 let AddedComplexity = 30 in 4920 def MEMb_ADDSUBi_MEM_V4 : MEMInst_V4<(outs), 4921 (ins MEMri:$addr, m6Imm:$addend), 4922 "Error; should not emit", 4923 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr), 4924 m6ImmPred:$addend), ADDRriU6_0:$addr)]>, 4925 Requires<[HasV4T, UseMEMOP]>; 4926 4927 // memb(Rs+#u6:0) += #U5 4928 let AddedComplexity = 30 in 4929 def MEMb_ADDi_MEM_V4 : MEMInst_V4<(outs), 4930 (ins MEMri:$addr, u5Imm:$addend), 4931 "memb($addr) += $addend", 4932 []>, 4933 Requires<[HasV4T, UseMEMOP]>; 4934 4935 // memb(Rs+#u6:0) -= #U5 4936 let AddedComplexity = 30 in 4937 def MEMb_SUBi_MEM_V4 : MEMInst_V4<(outs), 4938 (ins MEMri:$addr, u5Imm:$subend), 4939 "memb($addr) -= $subend", 4940 []>, 4941 Requires<[HasV4T, UseMEMOP]>; 4942 4943 // memb(Rs+#u6:0) += Rt 4944 let AddedComplexity = 30 in 4945 def MEMb_ADDr_MEM_V4 : MEMInst_V4<(outs), 4946 (ins MEMri:$addr, IntRegs:$addend), 4947 "memb($addr) += $addend", 4948 [(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr), 4949 (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>, 4950 Requires<[HasV4T, UseMEMOP]>; 4951 4952 // memb(Rs+#u6:0) -= Rt 4953 let AddedComplexity = 30 in 4954 def MEMb_SUBr_MEM_V4 : MEMInst_V4<(outs), 4955 (ins MEMri:$addr, IntRegs:$subend), 4956 "memb($addr) -= $subend", 4957 [(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr), 4958 (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>, 4959 Requires<[HasV4T, UseMEMOP]>; 4960 4961 // memb(Rs+#u6:0) &= Rt 4962 let AddedComplexity = 30 in 4963 def MEMb_ANDr_MEM_V4 : MEMInst_V4<(outs), 4964 (ins MEMri:$addr, IntRegs:$andend), 4965 "memb($addr) &= $andend", 4966 [(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr), 4967 (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>, 4968 Requires<[HasV4T, UseMEMOP]>; 4969 4970 // memb(Rs+#u6:0) |= Rt 4971 let AddedComplexity = 30 in 4972 def MEMb_ORr_MEM_V4 : MEMInst_V4<(outs), 4973 (ins MEMri:$addr, IntRegs:$orend), 4974 "memb($addr) |= $orend", 4975 [(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr), 4976 (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>, 4977 Requires<[HasV4T, UseMEMOP]>; 4978 4979 4980 //===----------------------------------------------------------------------===// 4981 // XTYPE/PRED + 4982 //===----------------------------------------------------------------------===// 4983 4984 // Hexagon V4 only supports these flavors of byte/half compare instructions: 4985 // EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by 4986 // hardware. However, compiler can still implement these patterns through 4987 // appropriate patterns combinations based on current implemented patterns. 4988 // The implemented patterns are: EQ/GT/GTU. 4989 // Missing patterns are: GE/GEU/LT/LTU/LE/LEU. 4990 4991 // Following instruction is not being extended as it results into the 4992 // incorrect code for negative numbers. 4993 // Pd=cmpb.eq(Rs,#u8) 4994 4995 let isCompare = 1 in 4996 def CMPbEQri_V4 : MInst<(outs PredRegs:$dst), 4997 (ins IntRegs:$src1, u8Imm:$src2), 4998 "$dst = cmpb.eq($src1, #$src2)", 4999 [(set (i1 PredRegs:$dst), 5000 (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>, 5001 Requires<[HasV4T]>; 5002 5003 // Pd=cmpb.eq(Rs,Rt) 5004 let isCompare = 1 in 5005 def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst), 5006 (ins IntRegs:$src1, IntRegs:$src2), 5007 "$dst = cmpb.eq($src1, $src2)", 5008 [(set (i1 PredRegs:$dst), 5009 (seteq (and (xor (i32 IntRegs:$src1), 5010 (i32 IntRegs:$src2)), 255), 0))]>, 5011 Requires<[HasV4T]>; 5012 5013 // Pd=cmpb.eq(Rs,Rt) 5014 let isCompare = 1 in 5015 def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst), 5016 (ins IntRegs:$src1, IntRegs:$src2), 5017 "$dst = cmpb.eq($src1, $src2)", 5018 [(set (i1 PredRegs:$dst), 5019 (seteq (shl (i32 IntRegs:$src1), (i32 24)), 5020 (shl (i32 IntRegs:$src2), (i32 24))))]>, 5021 Requires<[HasV4T]>; 5022 5023 // Pd=cmpb.gt(Rs,Rt) 5024 let isCompare = 1 in 5025 def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst), 5026 (ins IntRegs:$src1, IntRegs:$src2), 5027 "$dst = cmpb.gt($src1, $src2)", 5028 [(set (i1 PredRegs:$dst), 5029 (setgt (shl (i32 IntRegs:$src1), (i32 24)), 5030 (shl (i32 IntRegs:$src2), (i32 24))))]>, 5031 Requires<[HasV4T]>; 5032 5033 // Pd=cmpb.gtu(Rs,#u7) 5034 let isCompare = 1 in 5035 def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst), 5036 (ins IntRegs:$src1, u7Imm:$src2), 5037 "$dst = cmpb.gtu($src1, #$src2)", 5038 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255), 5039 u7ImmPred:$src2))]>, 5040 Requires<[HasV4T]>; 5041 5042 // Pd=cmpb.gtu(Rs,Rt) 5043 let isCompare = 1 in 5044 def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst), 5045 (ins IntRegs:$src1, IntRegs:$src2), 5046 "$dst = cmpb.gtu($src1, $src2)", 5047 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255), 5048 (and (i32 IntRegs:$src2), 255)))]>, 5049 Requires<[HasV4T]>; 5050 5051 // Following instruction is not being extended as it results into the incorrect 5052 // code for negative numbers. 5053 5054 // Signed half compare(.eq) ri. 5055 // Pd=cmph.eq(Rs,#s8) 5056 let isCompare = 1 in 5057 def CMPhEQri_V4 : MInst<(outs PredRegs:$dst), 5058 (ins IntRegs:$src1, s8Imm:$src2), 5059 "$dst = cmph.eq($src1, #$src2)", 5060 [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535), 5061 s8ImmPred:$src2))]>, 5062 Requires<[HasV4T]>; 5063 5064 // Signed half compare(.eq) rr. 5065 // Case 1: xor + and, then compare: 5066 // r0=xor(r0,r1) 5067 // r0=and(r0,#0xffff) 5068 // p0=cmp.eq(r0,#0) 5069 // Pd=cmph.eq(Rs,Rt) 5070 let isCompare = 1 in 5071 def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst), 5072 (ins IntRegs:$src1, IntRegs:$src2), 5073 "$dst = cmph.eq($src1, $src2)", 5074 [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1), 5075 (i32 IntRegs:$src2)), 5076 65535), 0))]>, 5077 Requires<[HasV4T]>; 5078 5079 // Signed half compare(.eq) rr. 5080 // Case 2: shift left 16 bits then compare: 5081 // r0=asl(r0,16) 5082 // r1=asl(r1,16) 5083 // p0=cmp.eq(r0,r1) 5084 // Pd=cmph.eq(Rs,Rt) 5085 let isCompare = 1 in 5086 def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst), 5087 (ins IntRegs:$src1, IntRegs:$src2), 5088 "$dst = cmph.eq($src1, $src2)", 5089 [(set (i1 PredRegs:$dst), 5090 (seteq (shl (i32 IntRegs:$src1), (i32 16)), 5091 (shl (i32 IntRegs:$src2), (i32 16))))]>, 5092 Requires<[HasV4T]>; 5093 5094 /* Incorrect Pattern -- immediate should be right shifted before being 5095 used in the cmph.gt instruction. 5096 // Signed half compare(.gt) ri. 5097 // Pd=cmph.gt(Rs,#s8) 5098 5099 let isCompare = 1 in 5100 def CMPhGTri_V4 : MInst<(outs PredRegs:$dst), 5101 (ins IntRegs:$src1, s8Imm:$src2), 5102 "$dst = cmph.gt($src1, #$src2)", 5103 [(set (i1 PredRegs:$dst), 5104 (setgt (shl (i32 IntRegs:$src1), (i32 16)), 5105 s8ImmPred:$src2))]>, 5106 Requires<[HasV4T]>; 5107 */ 5108 5109 // Signed half compare(.gt) rr. 5110 // Pd=cmph.gt(Rs,Rt) 5111 let isCompare = 1 in 5112 def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst), 5113 (ins IntRegs:$src1, IntRegs:$src2), 5114 "$dst = cmph.gt($src1, $src2)", 5115 [(set (i1 PredRegs:$dst), 5116 (setgt (shl (i32 IntRegs:$src1), (i32 16)), 5117 (shl (i32 IntRegs:$src2), (i32 16))))]>, 5118 Requires<[HasV4T]>; 5119 5120 // Unsigned half compare rr (.gtu). 5121 // Pd=cmph.gtu(Rs,Rt) 5122 let isCompare = 1 in 5123 def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst), 5124 (ins IntRegs:$src1, IntRegs:$src2), 5125 "$dst = cmph.gtu($src1, $src2)", 5126 [(set (i1 PredRegs:$dst), 5127 (setugt (and (i32 IntRegs:$src1), 65535), 5128 (and (i32 IntRegs:$src2), 65535)))]>, 5129 Requires<[HasV4T]>; 5130 5131 // Unsigned half compare ri (.gtu). 5132 // Pd=cmph.gtu(Rs,#u7) 5133 let isCompare = 1 in 5134 def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst), 5135 (ins IntRegs:$src1, u7Imm:$src2), 5136 "$dst = cmph.gtu($src1, #$src2)", 5137 [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535), 5138 u7ImmPred:$src2))]>, 5139 Requires<[HasV4T]>; 5140 5141 //===----------------------------------------------------------------------===// 5142 // XTYPE/PRED - 5143 //===----------------------------------------------------------------------===// 5144 5145 //Deallocate frame and return. 5146 // dealloc_return 5147 let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1, 5148 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in { 5149 def DEALLOC_RET_V4 : NVInst_V4<(outs), (ins i32imm:$amt1), 5150 "dealloc_return", 5151 []>, 5152 Requires<[HasV4T]>; 5153 } 5154 5155 // Restore registers and dealloc return function call. 5156 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, 5157 Defs = [R29, R30, R31, PC] in { 5158 def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs), 5159 (ins calltarget:$dst), 5160 "jump $dst // Restore_and_dealloc_return", 5161 []>, 5162 Requires<[HasV4T]>; 5163 } 5164 5165 // Restore registers and dealloc frame before a tail call. 5166 let isCall = 1, isBarrier = 1, 5167 Defs = [R29, R30, R31, PC] in { 5168 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs), 5169 (ins calltarget:$dst), 5170 "call $dst // Restore_and_dealloc_before_tailcall", 5171 []>, 5172 Requires<[HasV4T]>; 5173 } 5174 5175 // Save registers function call. 5176 let isCall = 1, isBarrier = 1, 5177 Uses = [R29, R31] in { 5178 def SAVE_REGISTERS_CALL_V4 : JInst<(outs), 5179 (ins calltarget:$dst), 5180 "call $dst // Save_calle_saved_registers", 5181 []>, 5182 Requires<[HasV4T]>; 5183 } 5184 5185 // if (Ps) dealloc_return 5186 let isReturn = 1, isTerminator = 1, 5187 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1, 5188 isPredicated = 1 in { 5189 def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs), 5190 (ins PredRegs:$src1, i32imm:$amt1), 5191 "if ($src1) dealloc_return", 5192 []>, 5193 Requires<[HasV4T]>; 5194 } 5195 5196 // if (!Ps) dealloc_return 5197 let isReturn = 1, isTerminator = 1, 5198 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1, 5199 isPredicated = 1 in { 5200 def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, 5201 i32imm:$amt1), 5202 "if (!$src1) dealloc_return", 5203 []>, 5204 Requires<[HasV4T]>; 5205 } 5206 5207 // if (Ps.new) dealloc_return:nt 5208 let isReturn = 1, isTerminator = 1, 5209 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1, 5210 isPredicated = 1 in { 5211 def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, 5212 i32imm:$amt1), 5213 "if ($src1.new) dealloc_return:nt", 5214 []>, 5215 Requires<[HasV4T]>; 5216 } 5217 5218 // if (!Ps.new) dealloc_return:nt 5219 let isReturn = 1, isTerminator = 1, 5220 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1, 5221 isPredicated = 1 in { 5222 def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, 5223 i32imm:$amt1), 5224 "if (!$src1.new) dealloc_return:nt", 5225 []>, 5226 Requires<[HasV4T]>; 5227 } 5228 5229 // if (Ps.new) dealloc_return:t 5230 let isReturn = 1, isTerminator = 1, 5231 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1, 5232 isPredicated = 1 in { 5233 def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, 5234 i32imm:$amt1), 5235 "if ($src1.new) dealloc_return:t", 5236 []>, 5237 Requires<[HasV4T]>; 5238 } 5239 5240 // if (!Ps.new) dealloc_return:nt 5241 let isReturn = 1, isTerminator = 1, 5242 Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1, 5243 isPredicated = 1 in { 5244 def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, 5245 i32imm:$amt1), 5246 "if (!$src1.new) dealloc_return:t", 5247 []>, 5248 Requires<[HasV4T]>; 5249 } 5250 5251 5252 // Load/Store with absolute addressing mode 5253 // memw(#u6)=Rt 5254 5255 multiclass ST_abs<string OpcStr> { 5256 let isPredicable = 1 in 5257 def _abs_V4 : STInst2<(outs), 5258 (ins globaladdress:$absaddr, IntRegs:$src), 5259 !strconcat(OpcStr, "(##$absaddr) = $src"), 5260 []>, 5261 Requires<[HasV4T]>; 5262 5263 let isPredicated = 1 in 5264 def _abs_cPt_V4 : STInst2<(outs), 5265 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5266 !strconcat("if ($src1)", 5267 !strconcat(OpcStr, "(##$absaddr) = $src2")), 5268 []>, 5269 Requires<[HasV4T]>; 5270 5271 let isPredicated = 1 in 5272 def _abs_cNotPt_V4 : STInst2<(outs), 5273 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5274 !strconcat("if (!$src1)", 5275 !strconcat(OpcStr, "(##$absaddr) = $src2")), 5276 []>, 5277 Requires<[HasV4T]>; 5278 5279 let isPredicated = 1 in 5280 def _abs_cdnPt_V4 : STInst2<(outs), 5281 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5282 !strconcat("if ($src1.new)", 5283 !strconcat(OpcStr, "(##$absaddr) = $src2")), 5284 []>, 5285 Requires<[HasV4T]>; 5286 5287 let isPredicated = 1 in 5288 def _abs_cdnNotPt_V4 : STInst2<(outs), 5289 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5290 !strconcat("if (!$src1.new)", 5291 !strconcat(OpcStr, "(##$absaddr) = $src2")), 5292 []>, 5293 Requires<[HasV4T]>; 5294 5295 def _abs_nv_V4 : STInst2<(outs), 5296 (ins globaladdress:$absaddr, IntRegs:$src), 5297 !strconcat(OpcStr, "(##$absaddr) = $src.new"), 5298 []>, 5299 Requires<[HasV4T]>; 5300 5301 let isPredicated = 1 in 5302 def _abs_cPt_nv_V4 : STInst2<(outs), 5303 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5304 !strconcat("if ($src1)", 5305 !strconcat(OpcStr, "(##$absaddr) = $src2.new")), 5306 []>, 5307 Requires<[HasV4T]>; 5308 5309 let isPredicated = 1 in 5310 def _abs_cNotPt_nv_V4 : STInst2<(outs), 5311 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5312 !strconcat("if (!$src1)", 5313 !strconcat(OpcStr, "(##$absaddr) = $src2.new")), 5314 []>, 5315 Requires<[HasV4T]>; 5316 5317 let isPredicated = 1 in 5318 def _abs_cdnPt_nv_V4 : STInst2<(outs), 5319 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5320 !strconcat("if ($src1.new)", 5321 !strconcat(OpcStr, "(##$absaddr) = $src2.new")), 5322 []>, 5323 Requires<[HasV4T]>; 5324 5325 let isPredicated = 1 in 5326 def _abs_cdnNotPt_nv_V4 : STInst2<(outs), 5327 (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2), 5328 !strconcat("if (!$src1.new)", 5329 !strconcat(OpcStr, "(##$absaddr) = $src2.new")), 5330 []>, 5331 Requires<[HasV4T]>; 5332 } 5333 5334 let AddedComplexity = 30, isPredicable = 1 in 5335 def STrid_abs_V4 : STInst<(outs), 5336 (ins globaladdress:$absaddr, DoubleRegs:$src), 5337 "memd(##$absaddr) = $src", 5338 [(store (i64 DoubleRegs:$src), 5339 (HexagonCONST32 tglobaladdr:$absaddr))]>, 5340 Requires<[HasV4T]>; 5341 5342 let AddedComplexity = 30, isPredicated = 1 in 5343 def STrid_abs_cPt_V4 : STInst2<(outs), 5344 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2), 5345 "if ($src1) memd(##$absaddr) = $src2", 5346 []>, 5347 Requires<[HasV4T]>; 5348 5349 let AddedComplexity = 30, isPredicated = 1 in 5350 def STrid_abs_cNotPt_V4 : STInst2<(outs), 5351 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2), 5352 "if (!$src1) memd(##$absaddr) = $src2", 5353 []>, 5354 Requires<[HasV4T]>; 5355 5356 let AddedComplexity = 30, isPredicated = 1 in 5357 def STrid_abs_cdnPt_V4 : STInst2<(outs), 5358 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2), 5359 "if ($src1.new) memd(##$absaddr) = $src2", 5360 []>, 5361 Requires<[HasV4T]>; 5362 5363 let AddedComplexity = 30, isPredicated = 1 in 5364 def STrid_abs_cdnNotPt_V4 : STInst2<(outs), 5365 (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2), 5366 "if (!$src1.new) memd(##$absaddr) = $src2", 5367 []>, 5368 Requires<[HasV4T]>; 5369 5370 defm STrib : ST_abs<"memb">; 5371 defm STrih : ST_abs<"memh">; 5372 defm STriw : ST_abs<"memw">; 5373 5374 let Predicates = [HasV4T], AddedComplexity = 30 in 5375 def : Pat<(truncstorei8 (i32 IntRegs:$src1), 5376 (HexagonCONST32 tglobaladdr:$absaddr)), 5377 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>; 5378 5379 let Predicates = [HasV4T], AddedComplexity = 30 in 5380 def : Pat<(truncstorei16 (i32 IntRegs:$src1), 5381 (HexagonCONST32 tglobaladdr:$absaddr)), 5382 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>; 5383 5384 let Predicates = [HasV4T], AddedComplexity = 30 in 5385 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)), 5386 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>; 5387 5388 5389 multiclass LD_abs<string OpcStr> { 5390 let isPredicable = 1 in 5391 def _abs_V4 : LDInst2<(outs IntRegs:$dst), 5392 (ins globaladdress:$absaddr), 5393 !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")), 5394 []>, 5395 Requires<[HasV4T]>; 5396 5397 let isPredicated = 1 in 5398 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst), 5399 (ins PredRegs:$src1, globaladdress:$absaddr), 5400 !strconcat("if ($src1) $dst = ", 5401 !strconcat(OpcStr, "(##$absaddr)")), 5402 []>, 5403 Requires<[HasV4T]>; 5404 5405 let isPredicated = 1 in 5406 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 5407 (ins PredRegs:$src1, globaladdress:$absaddr), 5408 !strconcat("if (!$src1) $dst = ", 5409 !strconcat(OpcStr, "(##$absaddr)")), 5410 []>, 5411 Requires<[HasV4T]>; 5412 5413 let isPredicated = 1 in 5414 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 5415 (ins PredRegs:$src1, globaladdress:$absaddr), 5416 !strconcat("if ($src1.new) $dst = ", 5417 !strconcat(OpcStr, "(##$absaddr)")), 5418 []>, 5419 Requires<[HasV4T]>; 5420 5421 let isPredicated = 1 in 5422 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 5423 (ins PredRegs:$src1, globaladdress:$absaddr), 5424 !strconcat("if (!$src1.new) $dst = ", 5425 !strconcat(OpcStr, "(##$absaddr)")), 5426 []>, 5427 Requires<[HasV4T]>; 5428 } 5429 5430 let AddedComplexity = 30 in 5431 def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst), 5432 (ins globaladdress:$absaddr), 5433 "$dst = memd(##$absaddr)", 5434 [(set (i64 DoubleRegs:$dst), 5435 (load (HexagonCONST32 tglobaladdr:$absaddr)))]>, 5436 Requires<[HasV4T]>; 5437 5438 let AddedComplexity = 30, isPredicated = 1 in 5439 def LDrid_abs_cPt_V4 : LDInst2<(outs DoubleRegs:$dst), 5440 (ins PredRegs:$src1, globaladdress:$absaddr), 5441 "if ($src1) $dst = memd(##$absaddr)", 5442 []>, 5443 Requires<[HasV4T]>; 5444 5445 let AddedComplexity = 30, isPredicated = 1 in 5446 def LDrid_abs_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 5447 (ins PredRegs:$src1, globaladdress:$absaddr), 5448 "if (!$src1) $dst = memd(##$absaddr)", 5449 []>, 5450 Requires<[HasV4T]>; 5451 5452 let AddedComplexity = 30, isPredicated = 1 in 5453 def LDrid_abs_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst), 5454 (ins PredRegs:$src1, globaladdress:$absaddr), 5455 "if ($src1.new) $dst = memd(##$absaddr)", 5456 []>, 5457 Requires<[HasV4T]>; 5458 5459 let AddedComplexity = 30, isPredicated = 1 in 5460 def LDrid_abs_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst), 5461 (ins PredRegs:$src1, globaladdress:$absaddr), 5462 "if (!$src1.new) $dst = memd(##$absaddr)", 5463 []>, 5464 Requires<[HasV4T]>; 5465 5466 defm LDrib : LD_abs<"memb">; 5467 defm LDriub : LD_abs<"memub">; 5468 defm LDrih : LD_abs<"memh">; 5469 defm LDriuh : LD_abs<"memuh">; 5470 defm LDriw : LD_abs<"memw">; 5471 5472 5473 let Predicates = [HasV4T], AddedComplexity = 30 in 5474 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))), 5475 (LDriw_abs_V4 tglobaladdr: $absaddr)>; 5476 5477 let Predicates = [HasV4T], AddedComplexity=30 in 5478 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))), 5479 (LDrib_abs_V4 tglobaladdr:$absaddr)>; 5480 5481 let Predicates = [HasV4T], AddedComplexity=30 in 5482 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))), 5483 (LDriub_abs_V4 tglobaladdr:$absaddr)>; 5484 5485 let Predicates = [HasV4T], AddedComplexity=30 in 5486 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))), 5487 (LDrih_abs_V4 tglobaladdr:$absaddr)>; 5488 5489 let Predicates = [HasV4T], AddedComplexity=30 in 5490 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))), 5491 (LDriuh_abs_V4 tglobaladdr:$absaddr)>; 5492 5493 // Transfer global address into a register 5494 let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in 5495 def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1), 5496 "$dst = ##$src1", 5497 [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>, 5498 Requires<[HasV4T]>; 5499 5500 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in 5501 def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst), 5502 (ins PredRegs:$src1, globaladdress:$src2), 5503 "if($src1) $dst = ##$src2", 5504 []>, 5505 Requires<[HasV4T]>; 5506 5507 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in 5508 def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst), 5509 (ins PredRegs:$src1, globaladdress:$src2), 5510 "if(!$src1) $dst = ##$src2", 5511 []>, 5512 Requires<[HasV4T]>; 5513 5514 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in 5515 def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst), 5516 (ins PredRegs:$src1, globaladdress:$src2), 5517 "if($src1.new) $dst = ##$src2", 5518 []>, 5519 Requires<[HasV4T]>; 5520 5521 let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in 5522 def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst), 5523 (ins PredRegs:$src1, globaladdress:$src2), 5524 "if(!$src1.new) $dst = ##$src2", 5525 []>, 5526 Requires<[HasV4T]>; 5527 5528 let AddedComplexity = 50, Predicates = [HasV4T] in 5529 def : Pat<(HexagonCONST32_GP tglobaladdr:$src1), 5530 (TFRI_V4 tglobaladdr:$src1)>; 5531 5532 5533 // Load - Indirect with long offset: These instructions take global address 5534 // as an operand 5535 let AddedComplexity = 10 in 5536 def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst), 5537 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset), 5538 "$dst=memd($src1<<#$src2+##$offset)", 5539 [(set (i64 DoubleRegs:$dst), 5540 (load (add (shl IntRegs:$src1, u2ImmPred:$src2), 5541 (HexagonCONST32 tglobaladdr:$offset))))]>, 5542 Requires<[HasV4T]>; 5543 5544 let AddedComplexity = 10 in 5545 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> { 5546 def _lo_V4 : LDInst<(outs IntRegs:$dst), 5547 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset), 5548 !strconcat("$dst = ", 5549 !strconcat(OpcStr, "($src1<<#$src2+##$offset)")), 5550 [(set IntRegs:$dst, 5551 (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2), 5552 (HexagonCONST32 tglobaladdr:$offset)))))]>, 5553 Requires<[HasV4T]>; 5554 } 5555 5556 defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>; 5557 defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>; 5558 defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>; 5559 defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>; 5560 defm LDriw_ind : LD_indirect_lo<"memw", load>; 5561 5562 // Store - Indirect with long offset: These instructions take global address 5563 // as an operand 5564 let AddedComplexity = 10 in 5565 def STrid_ind_lo_V4 : STInst<(outs), 5566 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3, 5567 DoubleRegs:$src4), 5568 "memd($src1<<#$src2+#$src3) = $src4", 5569 [(store (i64 DoubleRegs:$src4), 5570 (add (shl IntRegs:$src1, u2ImmPred:$src2), 5571 (HexagonCONST32 tglobaladdr:$src3)))]>, 5572 Requires<[HasV4T]>; 5573 5574 let AddedComplexity = 10 in 5575 multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> { 5576 def _lo_V4 : STInst<(outs), 5577 (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3, 5578 IntRegs:$src4), 5579 !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"), 5580 [(OpNode (i32 IntRegs:$src4), 5581 (add (shl IntRegs:$src1, u2ImmPred:$src2), 5582 (HexagonCONST32 tglobaladdr:$src3)))]>, 5583 Requires<[HasV4T]>; 5584 } 5585 5586 defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>; 5587 defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>; 5588 defm STriw_ind : ST_indirect_lo<"memw", store>; 5589 5590 // Store - absolute addressing mode: These instruction take constant 5591 // value as the extended operand 5592 multiclass ST_absimm<string OpcStr> { 5593 let isPredicable = 1 in 5594 def _abs_V4 : STInst2<(outs), 5595 (ins u6Imm:$src1, IntRegs:$src2), 5596 !strconcat(OpcStr, "(#$src1) = $src2"), 5597 []>, 5598 Requires<[HasV4T]>; 5599 5600 let isPredicated = 1 in 5601 def _abs_cPt_V4 : STInst2<(outs), 5602 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5603 !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")), 5604 []>, 5605 Requires<[HasV4T]>; 5606 5607 let isPredicated = 1 in 5608 def _abs_cNotPt_V4 : STInst2<(outs), 5609 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5610 !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")), 5611 []>, 5612 Requires<[HasV4T]>; 5613 5614 let isPredicated = 1 in 5615 def _abs_cdnPt_V4 : STInst2<(outs), 5616 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5617 !strconcat("if ($src1.new)", 5618 !strconcat(OpcStr, "(#$src2) = $src3")), 5619 []>, 5620 Requires<[HasV4T]>; 5621 5622 let isPredicated = 1 in 5623 def _abs_cdnNotPt_V4 : STInst2<(outs), 5624 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5625 !strconcat("if (!$src1.new)", 5626 !strconcat(OpcStr, "(#$src2) = $src3")), 5627 []>, 5628 Requires<[HasV4T]>; 5629 5630 def _abs_nv_V4 : STInst2<(outs), 5631 (ins u6Imm:$src1, IntRegs:$src2), 5632 !strconcat(OpcStr, "(#$src1) = $src2.new"), 5633 []>, 5634 Requires<[HasV4T]>; 5635 5636 let isPredicated = 1 in 5637 def _abs_cPt_nv_V4 : STInst2<(outs), 5638 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5639 !strconcat("if ($src1)", 5640 !strconcat(OpcStr, "(#$src2) = $src3.new")), 5641 []>, 5642 Requires<[HasV4T]>; 5643 5644 let isPredicated = 1 in 5645 def _abs_cNotPt_nv_V4 : STInst2<(outs), 5646 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5647 !strconcat("if (!$src1)", 5648 !strconcat(OpcStr, "(#$src2) = $src3.new")), 5649 []>, 5650 Requires<[HasV4T]>; 5651 5652 let isPredicated = 1 in 5653 def _abs_cdnPt_nv_V4 : STInst2<(outs), 5654 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5655 !strconcat("if ($src1.new)", 5656 !strconcat(OpcStr, "(#$src2) = $src3.new")), 5657 []>, 5658 Requires<[HasV4T]>; 5659 5660 let isPredicated = 1 in 5661 def _abs_cdnNotPt_nv_V4 : STInst2<(outs), 5662 (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3), 5663 !strconcat("if (!$src1.new)", 5664 !strconcat(OpcStr, "(#$src2) = $src3.new")), 5665 []>, 5666 Requires<[HasV4T]>; 5667 } 5668 5669 defm STrib_imm : ST_absimm<"memb">; 5670 defm STrih_imm : ST_absimm<"memh">; 5671 defm STriw_imm : ST_absimm<"memw">; 5672 5673 let Predicates = [HasV4T], AddedComplexity = 30 in 5674 def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2), 5675 (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>; 5676 5677 let Predicates = [HasV4T], AddedComplexity = 30 in 5678 def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2), 5679 (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>; 5680 5681 let Predicates = [HasV4T], AddedComplexity = 30 in 5682 def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2), 5683 (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>; 5684 5685 5686 // Load - absolute addressing mode: These instruction take constant 5687 // value as the extended operand 5688 5689 multiclass LD_absimm<string OpcStr> { 5690 let isPredicable = 1 in 5691 def _abs_V4 : LDInst2<(outs IntRegs:$dst), 5692 (ins u6Imm:$src), 5693 !strconcat("$dst = ", 5694 !strconcat(OpcStr, "(#$src)")), 5695 []>, 5696 Requires<[HasV4T]>; 5697 5698 let isPredicated = 1 in 5699 def _abs_cPt_V4 : LDInst2<(outs IntRegs:$dst), 5700 (ins PredRegs:$src1, u6Imm:$src2), 5701 !strconcat("if ($src1) $dst = ", 5702 !strconcat(OpcStr, "(#$src2)")), 5703 []>, 5704 Requires<[HasV4T]>; 5705 5706 let isPredicated = 1 in 5707 def _abs_cNotPt_V4 : LDInst2<(outs IntRegs:$dst), 5708 (ins PredRegs:$src1, u6Imm:$src2), 5709 !strconcat("if (!$src1) $dst = ", 5710 !strconcat(OpcStr, "(#$src2)")), 5711 []>, 5712 Requires<[HasV4T]>; 5713 5714 let isPredicated = 1 in 5715 def _abs_cdnPt_V4 : LDInst2<(outs IntRegs:$dst), 5716 (ins PredRegs:$src1, u6Imm:$src2), 5717 !strconcat("if ($src1.new) $dst = ", 5718 !strconcat(OpcStr, "(#$src2)")), 5719 []>, 5720 Requires<[HasV4T]>; 5721 5722 let isPredicated = 1 in 5723 def _abs_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst), 5724 (ins PredRegs:$src1, u6Imm:$src2), 5725 !strconcat("if (!$src1.new) $dst = ", 5726 !strconcat(OpcStr, "(#$src2)")), 5727 []>, 5728 Requires<[HasV4T]>; 5729 } 5730 5731 defm LDrib_imm : LD_absimm<"memb">; 5732 defm LDriub_imm : LD_absimm<"memub">; 5733 defm LDrih_imm : LD_absimm<"memh">; 5734 defm LDriuh_imm : LD_absimm<"memuh">; 5735 defm LDriw_imm : LD_absimm<"memw">; 5736 5737 let Predicates = [HasV4T], AddedComplexity = 30 in 5738 def : Pat<(i32 (load u6ImmPred:$src)), 5739 (LDriw_imm_abs_V4 u6ImmPred:$src)>; 5740 5741 let Predicates = [HasV4T], AddedComplexity=30 in 5742 def : Pat<(i32 (sextloadi8 u6ImmPred:$src)), 5743 (LDrib_imm_abs_V4 u6ImmPred:$src)>; 5744 5745 let Predicates = [HasV4T], AddedComplexity=30 in 5746 def : Pat<(i32 (zextloadi8 u6ImmPred:$src)), 5747 (LDriub_imm_abs_V4 u6ImmPred:$src)>; 5748 5749 let Predicates = [HasV4T], AddedComplexity=30 in 5750 def : Pat<(i32 (sextloadi16 u6ImmPred:$src)), 5751 (LDrih_imm_abs_V4 u6ImmPred:$src)>; 5752 5753 let Predicates = [HasV4T], AddedComplexity=30 in 5754 def : Pat<(i32 (zextloadi16 u6ImmPred:$src)), 5755 (LDriuh_imm_abs_V4 u6ImmPred:$src)>; 5756 5757 5758 // Indexed store double word - global address. 5759 // memw(Rs+#u6:2)=#S8 5760 let AddedComplexity = 10 in 5761 def STriw_offset_ext_V4 : STInst<(outs), 5762 (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3), 5763 "memw($src1+#$src2) = ##$src3", 5764 [(store (HexagonCONST32 tglobaladdr:$src3), 5765 (add IntRegs:$src1, u6_2ImmPred:$src2))]>, 5766 Requires<[HasV4T]>; 5767 5768 5769 // Indexed store double word - global address. 5770 // memw(Rs+#u6:2)=#S8 5771 let AddedComplexity = 10 in 5772 def STrih_offset_ext_V4 : STInst<(outs), 5773 (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3), 5774 "memh($src1+#$src2) = ##$src3", 5775 [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3), 5776 (add IntRegs:$src1, u6_1ImmPred:$src2))]>, 5777 Requires<[HasV4T]>; 5778
