1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // There are four SLOTS (four parallel pipelines) in Hexagon V4 machine. 11 // This file describes that machine information. 12 13 // 14 // |===========|==================================================| 15 // | PIPELINE | Instruction Classes | 16 // |===========|==================================================| 17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM | 18 // |-----------|--------------------------------------------------| 19 // | SLOT1 | LD ST ALU32 | 20 // |-----------|--------------------------------------------------| 21 // | SLOT2 | XTYPE ALU32 J JR | 22 // |-----------|--------------------------------------------------| 23 // | SLOT3 | XTYPE ALU32 J CR | 24 // |===========|==================================================| 25 26 // Functional Units. 27 def SLOT0 : FuncUnit; 28 def SLOT1 : FuncUnit; 29 def SLOT2 : FuncUnit; 30 def SLOT3 : FuncUnit; 31 32 // Itinerary classes. 33 def NV_V4 : InstrItinClass; 34 def MEM_V4 : InstrItinClass; 35 // ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4. 36 def PREFIX : InstrItinClass; 37 38 def HexagonItinerariesV4 : 39 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3], [], [ 40 InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 41 InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>, 42 InstrItinData<CR , [InstrStage<1, [SLOT3]>]>, 43 InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>, 44 InstrItinData<JR , [InstrStage<1, [SLOT2]>]>, 45 InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>, 46 InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>, 47 InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>, 48 InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>, 49 InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>, 50 InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>, 51 InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>, 52 InstrItinData<MARKER , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 53 InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 54 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]> 55 ]>; 56 57 def HexagonModelV4 : SchedMachineModel { 58 // Max issue per cycle == bundle width. 59 let IssueWidth = 4; 60 let Itineraries = HexagonItinerariesV4; 61 let LoadLatency = 1; 62 } 63 64 //===----------------------------------------------------------------------===// 65 // Hexagon V4 Resource Definitions - 66 //===----------------------------------------------------------------------===// 67
