1 //===-- MBlazeSubtarget.cpp - MBlaze Subtarget Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MBlaze specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MBlazeSubtarget.h" 15 #include "MBlaze.h" 16 #include "MBlazeRegisterInfo.h" 17 #include "llvm/Support/CommandLine.h" 18 #include "llvm/Support/TargetRegistry.h" 19 20 #define GET_SUBTARGETINFO_TARGET_DESC 21 #define GET_SUBTARGETINFO_CTOR 22 #include "MBlazeGenSubtargetInfo.inc" 23 24 using namespace llvm; 25 26 MBlazeSubtarget::MBlazeSubtarget(const std::string &TT, 27 const std::string &CPU, 28 const std::string &FS): 29 MBlazeGenSubtargetInfo(TT, CPU, FS), 30 HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false), 31 HasFPU(false), HasMul64(false), HasSqrt(false) 32 { 33 // Parse features string. 34 std::string CPUName = CPU; 35 if (CPUName.empty()) 36 CPUName = "mblaze"; 37 ParseSubtargetFeatures(CPUName, FS); 38 39 // Only use instruction scheduling if the selected CPU has an instruction 40 // itinerary (the default CPU is the only one that doesn't). 41 HasItin = CPUName != "mblaze"; 42 DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n"); 43 44 // Initialize scheduling itinerary for the specified CPU. 45 InstrItins = getInstrItineraryForCPU(CPUName); 46 } 47 48 bool MBlazeSubtarget:: 49 enablePostRAScheduler(CodeGenOpt::Level OptLevel, 50 TargetSubtargetInfo::AntiDepBreakMode& Mode, 51 RegClassVector& CriticalPathRCs) const { 52 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; 53 CriticalPathRCs.clear(); 54 CriticalPathRCs.push_back(&MBlaze::GPRRegClass); 55 return HasItin && OptLevel >= CodeGenOpt::Default; 56 } 57