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      1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "PPCSubtarget.h"
     15 #include "PPCRegisterInfo.h"
     16 #include "PPC.h"
     17 #include "llvm/GlobalValue.h"
     18 #include "llvm/Target/TargetMachine.h"
     19 #include "llvm/Support/Host.h"
     20 #include "llvm/Support/TargetRegistry.h"
     21 #include <cstdlib>
     22 
     23 #define GET_SUBTARGETINFO_TARGET_DESC
     24 #define GET_SUBTARGETINFO_CTOR
     25 #include "PPCGenSubtargetInfo.inc"
     26 
     27 using namespace llvm;
     28 
     29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
     30                            const std::string &FS, bool is64Bit)
     31   : PPCGenSubtargetInfo(TT, CPU, FS)
     32   , StackAlignment(16)
     33   , DarwinDirective(PPC::DIR_NONE)
     34   , HasMFOCRF(false)
     35   , Has64BitSupport(false)
     36   , Use64BitRegs(false)
     37   , IsPPC64(is64Bit)
     38   , HasAltivec(false)
     39   , HasFSQRT(false)
     40   , HasSTFIWX(false)
     41   , HasISEL(false)
     42   , IsBookE(false)
     43   , HasLazyResolverStubs(false)
     44   , IsJITCodeModel(false)
     45   , TargetTriple(TT) {
     46 
     47   // Determine default and user specified characteristics
     48   std::string CPUName = CPU;
     49   if (CPUName.empty())
     50     CPUName = "generic";
     51 #if (defined(__APPLE__) || defined(__linux__)) && \
     52     (defined(__ppc__) || defined(__powerpc__))
     53   if (CPUName == "generic")
     54     CPUName = sys::getHostCPUName();
     55 #endif
     56 
     57   // Parse features string.
     58   ParseSubtargetFeatures(CPUName, FS);
     59 
     60   // Initialize scheduling itinerary for the specified CPU.
     61   InstrItins = getInstrItineraryForCPU(CPUName);
     62 
     63   // If we are generating code for ppc64, verify that options make sense.
     64   if (is64Bit) {
     65     Has64BitSupport = true;
     66     // Silently force 64-bit register use on ppc64.
     67     Use64BitRegs = true;
     68   }
     69 
     70   // If the user requested use of 64-bit regs, but the cpu selected doesn't
     71   // support it, ignore.
     72   if (use64BitRegs() && !has64BitSupport())
     73     Use64BitRegs = false;
     74 
     75   // Set up darwin-specific properties.
     76   if (isDarwin())
     77     HasLazyResolverStubs = true;
     78 }
     79 
     80 /// SetJITMode - This is called to inform the subtarget info that we are
     81 /// producing code for the JIT.
     82 void PPCSubtarget::SetJITMode() {
     83   // JIT mode doesn't want lazy resolver stubs, it knows exactly where
     84   // everything is.  This matters for PPC64, which codegens in PIC mode without
     85   // stubs.
     86   HasLazyResolverStubs = false;
     87 
     88   // Calls to external functions need to use indirect calls
     89   IsJITCodeModel = true;
     90 }
     91 
     92 
     93 /// hasLazyResolverStub - Return true if accesses to the specified global have
     94 /// to go through a dyld lazy resolution stub.  This means that an extra load
     95 /// is required to get the address of the global.
     96 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
     97                                        const TargetMachine &TM) const {
     98   // We never have stubs if HasLazyResolverStubs=false or if in static mode.
     99   if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
    100     return false;
    101   // If symbol visibility is hidden, the extra load is not needed if
    102   // the symbol is definitely defined in the current translation unit.
    103   bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
    104   if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
    105     return false;
    106   return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
    107          GV->hasCommonLinkage() || isDecl;
    108 }
    109 
    110 bool PPCSubtarget::enablePostRAScheduler(
    111            CodeGenOpt::Level OptLevel,
    112            TargetSubtargetInfo::AntiDepBreakMode& Mode,
    113            RegClassVector& CriticalPathRCs) const {
    114   // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
    115   // but we can't because we can't reassign the cr registers. There is a
    116   // dependence between the cr register and the RLWINM instruction used
    117   // to extract its value which the anti-dependency breaker can't currently
    118   // see. Maybe we should make a late-expanded pseudo to encode this dependency.
    119   // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
    120 
    121   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
    122 
    123   CriticalPathRCs.clear();
    124 
    125   if (isPPC64())
    126     CriticalPathRCs.push_back(&PPC::G8RCRegClass);
    127   else
    128     CriticalPathRCs.push_back(&PPC::GPRCRegClass);
    129 
    130   CriticalPathRCs.push_back(&PPC::F8RCRegClass);
    131   CriticalPathRCs.push_back(&PPC::VRRCRegClass);
    132 
    133   return OptLevel >= CodeGenOpt::Default;
    134 }
    135 
    136