1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the SelectionDAGISel class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "isel" 15 #include "llvm/CodeGen/SelectionDAGISel.h" 16 #include "ScheduleDAGSDNodes.h" 17 #include "SelectionDAGBuilder.h" 18 #include "llvm/ADT/PostOrderIterator.h" 19 #include "llvm/ADT/Statistic.h" 20 #include "llvm/Analysis/AliasAnalysis.h" 21 #include "llvm/Analysis/BranchProbabilityInfo.h" 22 #include "llvm/Analysis/TargetTransformInfo.h" 23 #include "llvm/CodeGen/FastISel.h" 24 #include "llvm/CodeGen/FunctionLoweringInfo.h" 25 #include "llvm/CodeGen/GCMetadata.h" 26 #include "llvm/CodeGen/GCStrategy.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineModuleInfo.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33 #include "llvm/CodeGen/SchedulerRegistry.h" 34 #include "llvm/CodeGen/SelectionDAG.h" 35 #include "llvm/DebugInfo.h" 36 #include "llvm/IR/Constants.h" 37 #include "llvm/IR/Function.h" 38 #include "llvm/IR/InlineAsm.h" 39 #include "llvm/IR/Instructions.h" 40 #include "llvm/IR/IntrinsicInst.h" 41 #include "llvm/IR/Intrinsics.h" 42 #include "llvm/IR/LLVMContext.h" 43 #include "llvm/IR/Module.h" 44 #include "llvm/Support/Compiler.h" 45 #include "llvm/Support/Debug.h" 46 #include "llvm/Support/ErrorHandling.h" 47 #include "llvm/Support/Timer.h" 48 #include "llvm/Support/raw_ostream.h" 49 #include "llvm/Target/TargetInstrInfo.h" 50 #include "llvm/Target/TargetIntrinsicInfo.h" 51 #include "llvm/Target/TargetLibraryInfo.h" 52 #include "llvm/Target/TargetLowering.h" 53 #include "llvm/Target/TargetMachine.h" 54 #include "llvm/Target/TargetOptions.h" 55 #include "llvm/Target/TargetRegisterInfo.h" 56 #include "llvm/Target/TargetSubtargetInfo.h" 57 #include "llvm/Transforms/Utils/BasicBlockUtils.h" 58 #include <algorithm> 59 using namespace llvm; 60 61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 66 67 #ifndef NDEBUG 68 static cl::opt<bool> 69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 70 cl::desc("Enable extra verbose messages in the \"fast\" " 71 "instruction selector")); 72 // Terminators 73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 80 81 // Standard binary operators... 82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 94 95 // Logical operators... 96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 99 100 // Memory instructions... 101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 108 109 // Convert instructions... 110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 122 123 // Other instructions... 124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 139 #endif 140 141 static cl::opt<bool> 142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 143 cl::desc("Enable verbose messages in the \"fast\" " 144 "instruction selector")); 145 static cl::opt<bool> 146 EnableFastISelAbort("fast-isel-abort", cl::Hidden, 147 cl::desc("Enable abort calls when \"fast\" instruction selection " 148 "fails to lower an instruction")); 149 static cl::opt<bool> 150 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 151 cl::desc("Enable abort calls when \"fast\" instruction selection " 152 "fails to lower a formal argument")); 153 154 static cl::opt<bool> 155 UseMBPI("use-mbpi", 156 cl::desc("use Machine Branch Probability Info"), 157 cl::init(true), cl::Hidden); 158 159 #ifndef NDEBUG 160 static cl::opt<bool> 161 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 162 cl::desc("Pop up a window to show dags before the first " 163 "dag combine pass")); 164 static cl::opt<bool> 165 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 166 cl::desc("Pop up a window to show dags before legalize types")); 167 static cl::opt<bool> 168 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 169 cl::desc("Pop up a window to show dags before legalize")); 170 static cl::opt<bool> 171 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 172 cl::desc("Pop up a window to show dags before the second " 173 "dag combine pass")); 174 static cl::opt<bool> 175 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 176 cl::desc("Pop up a window to show dags before the post legalize types" 177 " dag combine pass")); 178 static cl::opt<bool> 179 ViewISelDAGs("view-isel-dags", cl::Hidden, 180 cl::desc("Pop up a window to show isel dags as they are selected")); 181 static cl::opt<bool> 182 ViewSchedDAGs("view-sched-dags", cl::Hidden, 183 cl::desc("Pop up a window to show sched dags as they are processed")); 184 static cl::opt<bool> 185 ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 186 cl::desc("Pop up a window to show SUnit dags after they are processed")); 187 #else 188 static const bool ViewDAGCombine1 = false, 189 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 190 ViewDAGCombine2 = false, 191 ViewDAGCombineLT = false, 192 ViewISelDAGs = false, ViewSchedDAGs = false, 193 ViewSUnitDAGs = false; 194 #endif 195 196 //===---------------------------------------------------------------------===// 197 /// 198 /// RegisterScheduler class - Track the registration of instruction schedulers. 199 /// 200 //===---------------------------------------------------------------------===// 201 MachinePassRegistry RegisterScheduler::Registry; 202 203 //===---------------------------------------------------------------------===// 204 /// 205 /// ISHeuristic command line option for instruction schedulers. 206 /// 207 //===---------------------------------------------------------------------===// 208 static cl::opt<RegisterScheduler::FunctionPassCtor, false, 209 RegisterPassParser<RegisterScheduler> > 210 ISHeuristic("pre-RA-sched", 211 cl::init(&createDefaultScheduler), 212 cl::desc("Instruction schedulers available (before register" 213 " allocation):")); 214 215 static RegisterScheduler 216 defaultListDAGScheduler("default", "Best scheduler for the target", 217 createDefaultScheduler); 218 219 namespace llvm { 220 //===--------------------------------------------------------------------===// 221 /// createDefaultScheduler - This creates an instruction scheduler appropriate 222 /// for the target. 223 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 224 CodeGenOpt::Level OptLevel) { 225 const TargetLowering &TLI = IS->getTargetLowering(); 226 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 227 228 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 229 TLI.getSchedulingPreference() == Sched::Source) 230 return createSourceListDAGScheduler(IS, OptLevel); 231 if (TLI.getSchedulingPreference() == Sched::RegPressure) 232 return createBURRListDAGScheduler(IS, OptLevel); 233 if (TLI.getSchedulingPreference() == Sched::Hybrid) 234 return createHybridListDAGScheduler(IS, OptLevel); 235 if (TLI.getSchedulingPreference() == Sched::VLIW) 236 return createVLIWDAGScheduler(IS, OptLevel); 237 assert(TLI.getSchedulingPreference() == Sched::ILP && 238 "Unknown sched type!"); 239 return createILPListDAGScheduler(IS, OptLevel); 240 } 241 } 242 243 // EmitInstrWithCustomInserter - This method should be implemented by targets 244 // that mark instructions with the 'usesCustomInserter' flag. These 245 // instructions are special in various ways, which require special support to 246 // insert. The specified MachineInstr is created but not inserted into any 247 // basic blocks, and this method is called to expand it into a sequence of 248 // instructions, potentially also creating new basic blocks and control flow. 249 // When new basic blocks are inserted and the edges from MBB to its successors 250 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the 251 // DenseMap. 252 MachineBasicBlock * 253 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 254 MachineBasicBlock *MBB) const { 255 #ifndef NDEBUG 256 dbgs() << "If a target marks an instruction with " 257 "'usesCustomInserter', it must implement " 258 "TargetLowering::EmitInstrWithCustomInserter!"; 259 #endif 260 llvm_unreachable(0); 261 } 262 263 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 264 SDNode *Node) const { 265 assert(!MI->hasPostISelHook() && 266 "If a target marks an instruction with 'hasPostISelHook', " 267 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 268 } 269 270 //===----------------------------------------------------------------------===// 271 // SelectionDAGISel code 272 //===----------------------------------------------------------------------===// 273 274 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 275 CodeGenOpt::Level OL) : 276 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 277 FuncInfo(new FunctionLoweringInfo(TLI)), 278 CurDAG(new SelectionDAG(tm, OL)), 279 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 280 GFI(), 281 OptLevel(OL), 282 DAGSize(0) { 283 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 284 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 285 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 286 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 287 } 288 289 SelectionDAGISel::~SelectionDAGISel() { 290 delete SDB; 291 delete CurDAG; 292 delete FuncInfo; 293 } 294 295 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 296 AU.addRequired<AliasAnalysis>(); 297 AU.addPreserved<AliasAnalysis>(); 298 AU.addRequired<GCModuleInfo>(); 299 AU.addPreserved<GCModuleInfo>(); 300 AU.addRequired<TargetLibraryInfo>(); 301 if (UseMBPI && OptLevel != CodeGenOpt::None) 302 AU.addRequired<BranchProbabilityInfo>(); 303 MachineFunctionPass::getAnalysisUsage(AU); 304 } 305 306 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 307 /// may trap on it. In this case we have to split the edge so that the path 308 /// through the predecessor block that doesn't go to the phi block doesn't 309 /// execute the possibly trapping instruction. 310 /// 311 /// This is required for correctness, so it must be done at -O0. 312 /// 313 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 314 // Loop for blocks with phi nodes. 315 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 316 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 317 if (PN == 0) continue; 318 319 ReprocessBlock: 320 // For each block with a PHI node, check to see if any of the input values 321 // are potentially trapping constant expressions. Constant expressions are 322 // the only potentially trapping value that can occur as the argument to a 323 // PHI. 324 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 325 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 326 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 327 if (CE == 0 || !CE->canTrap()) continue; 328 329 // The only case we have to worry about is when the edge is critical. 330 // Since this block has a PHI Node, we assume it has multiple input 331 // edges: check to see if the pred has multiple successors. 332 BasicBlock *Pred = PN->getIncomingBlock(i); 333 if (Pred->getTerminator()->getNumSuccessors() == 1) 334 continue; 335 336 // Okay, we have to split this edge. 337 SplitCriticalEdge(Pred->getTerminator(), 338 GetSuccessorNumber(Pred, BB), SDISel, true); 339 goto ReprocessBlock; 340 } 341 } 342 } 343 344 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 345 // Do some sanity-checking on the command-line options. 346 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 347 "-fast-isel-verbose requires -fast-isel"); 348 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 349 "-fast-isel-abort requires -fast-isel"); 350 351 const Function &Fn = *mf.getFunction(); 352 const TargetInstrInfo &TII = *TM.getInstrInfo(); 353 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 354 355 MF = &mf; 356 RegInfo = &MF->getRegInfo(); 357 AA = &getAnalysis<AliasAnalysis>(); 358 LibInfo = &getAnalysis<TargetLibraryInfo>(); 359 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 360 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 361 362 TargetSubtargetInfo &ST = 363 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 364 ST.resetSubtargetFeatures(MF); 365 TM.resetTargetOptions(MF); 366 367 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 368 369 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 370 371 CurDAG->init(*MF, TTI); 372 FuncInfo->set(Fn, *MF); 373 374 if (UseMBPI && OptLevel != CodeGenOpt::None) 375 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 376 else 377 FuncInfo->BPI = 0; 378 379 SDB->init(GFI, *AA, LibInfo); 380 381 MF->setHasMSInlineAsm(false); 382 SelectAllBasicBlocks(Fn); 383 384 // If the first basic block in the function has live ins that need to be 385 // copied into vregs, emit the copies into the top of the block before 386 // emitting the code for the block. 387 MachineBasicBlock *EntryMBB = MF->begin(); 388 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 389 390 DenseMap<unsigned, unsigned> LiveInMap; 391 if (!FuncInfo->ArgDbgValues.empty()) 392 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 393 E = RegInfo->livein_end(); LI != E; ++LI) 394 if (LI->second) 395 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 396 397 // Insert DBG_VALUE instructions for function arguments to the entry block. 398 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 399 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 400 unsigned Reg = MI->getOperand(0).getReg(); 401 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 402 EntryMBB->insert(EntryMBB->begin(), MI); 403 else { 404 MachineInstr *Def = RegInfo->getVRegDef(Reg); 405 MachineBasicBlock::iterator InsertPos = Def; 406 // FIXME: VR def may not be in entry block. 407 Def->getParent()->insert(llvm::next(InsertPos), MI); 408 } 409 410 // If Reg is live-in then update debug info to track its copy in a vreg. 411 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 412 if (LDI != LiveInMap.end()) { 413 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 414 MachineBasicBlock::iterator InsertPos = Def; 415 const MDNode *Variable = 416 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 417 unsigned Offset = MI->getOperand(1).getImm(); 418 // Def is never a terminator here, so it is ok to increment InsertPos. 419 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 420 TII.get(TargetOpcode::DBG_VALUE)) 421 .addReg(LDI->second, RegState::Debug) 422 .addImm(Offset).addMetadata(Variable); 423 424 // If this vreg is directly copied into an exported register then 425 // that COPY instructions also need DBG_VALUE, if it is the only 426 // user of LDI->second. 427 MachineInstr *CopyUseMI = NULL; 428 for (MachineRegisterInfo::use_iterator 429 UI = RegInfo->use_begin(LDI->second); 430 MachineInstr *UseMI = UI.skipInstruction();) { 431 if (UseMI->isDebugValue()) continue; 432 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 433 CopyUseMI = UseMI; continue; 434 } 435 // Otherwise this is another use or second copy use. 436 CopyUseMI = NULL; break; 437 } 438 if (CopyUseMI) { 439 MachineInstr *NewMI = 440 BuildMI(*MF, CopyUseMI->getDebugLoc(), 441 TII.get(TargetOpcode::DBG_VALUE)) 442 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 443 .addImm(Offset).addMetadata(Variable); 444 MachineBasicBlock::iterator Pos = CopyUseMI; 445 EntryMBB->insertAfter(Pos, NewMI); 446 } 447 } 448 } 449 450 // Determine if there are any calls in this machine function. 451 MachineFrameInfo *MFI = MF->getFrameInfo(); 452 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 453 ++I) { 454 455 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 456 break; 457 458 const MachineBasicBlock *MBB = I; 459 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 460 II != IE; ++II) { 461 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 462 if ((MCID.isCall() && !MCID.isReturn()) || 463 II->isStackAligningInlineAsm()) { 464 MFI->setHasCalls(true); 465 } 466 if (II->isMSInlineAsm()) { 467 MF->setHasMSInlineAsm(true); 468 } 469 } 470 } 471 472 // Determine if there is a call to setjmp in the machine function. 473 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 474 475 // Replace forward-declared registers with the registers containing 476 // the desired value. 477 MachineRegisterInfo &MRI = MF->getRegInfo(); 478 for (DenseMap<unsigned, unsigned>::iterator 479 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 480 I != E; ++I) { 481 unsigned From = I->first; 482 unsigned To = I->second; 483 // If To is also scheduled to be replaced, find what its ultimate 484 // replacement is. 485 for (;;) { 486 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 487 if (J == E) break; 488 To = J->second; 489 } 490 // Replace it. 491 MRI.replaceRegWith(From, To); 492 } 493 494 // Freeze the set of reserved registers now that MachineFrameInfo has been 495 // set up. All the information required by getReservedRegs() should be 496 // available now. 497 MRI.freezeReservedRegs(*MF); 498 499 // Release function-specific state. SDB and CurDAG are already cleared 500 // at this point. 501 FuncInfo->clear(); 502 503 return true; 504 } 505 506 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 507 BasicBlock::const_iterator End, 508 bool &HadTailCall) { 509 // Lower all of the non-terminator instructions. If a call is emitted 510 // as a tail call, cease emitting nodes for this block. Terminators 511 // are handled below. 512 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 513 SDB->visit(*I); 514 515 // Make sure the root of the DAG is up-to-date. 516 CurDAG->setRoot(SDB->getControlRoot()); 517 HadTailCall = SDB->HasTailCall; 518 SDB->clear(); 519 520 // Final step, emit the lowered DAG as machine code. 521 CodeGenAndEmitDAG(); 522 } 523 524 void SelectionDAGISel::ComputeLiveOutVRegInfo() { 525 SmallPtrSet<SDNode*, 128> VisitedNodes; 526 SmallVector<SDNode*, 128> Worklist; 527 528 Worklist.push_back(CurDAG->getRoot().getNode()); 529 530 APInt KnownZero; 531 APInt KnownOne; 532 533 do { 534 SDNode *N = Worklist.pop_back_val(); 535 536 // If we've already seen this node, ignore it. 537 if (!VisitedNodes.insert(N)) 538 continue; 539 540 // Otherwise, add all chain operands to the worklist. 541 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 542 if (N->getOperand(i).getValueType() == MVT::Other) 543 Worklist.push_back(N->getOperand(i).getNode()); 544 545 // If this is a CopyToReg with a vreg dest, process it. 546 if (N->getOpcode() != ISD::CopyToReg) 547 continue; 548 549 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 550 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 551 continue; 552 553 // Ignore non-scalar or non-integer values. 554 SDValue Src = N->getOperand(2); 555 EVT SrcVT = Src.getValueType(); 556 if (!SrcVT.isInteger() || SrcVT.isVector()) 557 continue; 558 559 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 560 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 561 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 562 } while (!Worklist.empty()); 563 } 564 565 void SelectionDAGISel::CodeGenAndEmitDAG() { 566 std::string GroupName; 567 if (TimePassesIsEnabled) 568 GroupName = "Instruction Selection and Scheduling"; 569 std::string BlockName; 570 int BlockNumber = -1; 571 (void)BlockNumber; 572 #ifdef NDEBUG 573 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 574 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 575 ViewSUnitDAGs) 576 #endif 577 { 578 BlockNumber = FuncInfo->MBB->getNumber(); 579 BlockName = MF->getName().str() + ":" + 580 FuncInfo->MBB->getBasicBlock()->getName().str(); 581 } 582 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 583 << " '" << BlockName << "'\n"; CurDAG->dump()); 584 585 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 586 587 // Run the DAG combiner in pre-legalize mode. 588 { 589 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 590 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 591 } 592 593 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 594 << " '" << BlockName << "'\n"; CurDAG->dump()); 595 596 // Second step, hack on the DAG until it only uses operations and types that 597 // the target supports. 598 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 599 BlockName); 600 601 bool Changed; 602 { 603 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 604 Changed = CurDAG->LegalizeTypes(); 605 } 606 607 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 608 << " '" << BlockName << "'\n"; CurDAG->dump()); 609 610 if (Changed) { 611 if (ViewDAGCombineLT) 612 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 613 614 // Run the DAG combiner in post-type-legalize mode. 615 { 616 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 617 TimePassesIsEnabled); 618 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 619 } 620 621 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 622 << " '" << BlockName << "'\n"; CurDAG->dump()); 623 } 624 625 { 626 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 627 Changed = CurDAG->LegalizeVectors(); 628 } 629 630 if (Changed) { 631 { 632 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 633 CurDAG->LegalizeTypes(); 634 } 635 636 if (ViewDAGCombineLT) 637 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 638 639 // Run the DAG combiner in post-type-legalize mode. 640 { 641 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 642 TimePassesIsEnabled); 643 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 644 } 645 646 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 647 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 648 } 649 650 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 651 652 { 653 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 654 CurDAG->Legalize(); 655 } 656 657 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 658 << " '" << BlockName << "'\n"; CurDAG->dump()); 659 660 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 661 662 // Run the DAG combiner in post-legalize mode. 663 { 664 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 665 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 666 } 667 668 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 669 << " '" << BlockName << "'\n"; CurDAG->dump()); 670 671 if (OptLevel != CodeGenOpt::None) 672 ComputeLiveOutVRegInfo(); 673 674 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 675 676 // Third, instruction select all of the operations to machine code, adding the 677 // code to the MachineBasicBlock. 678 { 679 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 680 DoInstructionSelection(); 681 } 682 683 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 684 << " '" << BlockName << "'\n"; CurDAG->dump()); 685 686 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 687 688 // Schedule machine code. 689 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 690 { 691 NamedRegionTimer T("Instruction Scheduling", GroupName, 692 TimePassesIsEnabled); 693 Scheduler->Run(CurDAG, FuncInfo->MBB); 694 } 695 696 if (ViewSUnitDAGs) Scheduler->viewGraph(); 697 698 // Emit machine code to BB. This can change 'BB' to the last block being 699 // inserted into. 700 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 701 { 702 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 703 704 // FuncInfo->InsertPt is passed by reference and set to the end of the 705 // scheduled instructions. 706 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 707 } 708 709 // If the block was split, make sure we update any references that are used to 710 // update PHI nodes later on. 711 if (FirstMBB != LastMBB) 712 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 713 714 // Free the scheduler state. 715 { 716 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 717 TimePassesIsEnabled); 718 delete Scheduler; 719 } 720 721 // Free the SelectionDAG state, now that we're finished with it. 722 CurDAG->clear(); 723 } 724 725 namespace { 726 /// ISelUpdater - helper class to handle updates of the instruction selection 727 /// graph. 728 class ISelUpdater : public SelectionDAG::DAGUpdateListener { 729 SelectionDAG::allnodes_iterator &ISelPosition; 730 public: 731 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 732 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 733 734 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 735 /// deleted is the current ISelPosition node, update ISelPosition. 736 /// 737 virtual void NodeDeleted(SDNode *N, SDNode *E) { 738 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 739 ++ISelPosition; 740 } 741 }; 742 } // end anonymous namespace 743 744 void SelectionDAGISel::DoInstructionSelection() { 745 DEBUG(errs() << "===== Instruction selection begins: BB#" 746 << FuncInfo->MBB->getNumber() 747 << " '" << FuncInfo->MBB->getName() << "'\n"); 748 749 PreprocessISelDAG(); 750 751 // Select target instructions for the DAG. 752 { 753 // Number all nodes with a topological order and set DAGSize. 754 DAGSize = CurDAG->AssignTopologicalOrder(); 755 756 // Create a dummy node (which is not added to allnodes), that adds 757 // a reference to the root node, preventing it from being deleted, 758 // and tracking any changes of the root. 759 HandleSDNode Dummy(CurDAG->getRoot()); 760 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 761 ++ISelPosition; 762 763 // Make sure that ISelPosition gets properly updated when nodes are deleted 764 // in calls made from this function. 765 ISelUpdater ISU(*CurDAG, ISelPosition); 766 767 // The AllNodes list is now topological-sorted. Visit the 768 // nodes by starting at the end of the list (the root of the 769 // graph) and preceding back toward the beginning (the entry 770 // node). 771 while (ISelPosition != CurDAG->allnodes_begin()) { 772 SDNode *Node = --ISelPosition; 773 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 774 // but there are currently some corner cases that it misses. Also, this 775 // makes it theoretically possible to disable the DAGCombiner. 776 if (Node->use_empty()) 777 continue; 778 779 SDNode *ResNode = Select(Node); 780 781 // FIXME: This is pretty gross. 'Select' should be changed to not return 782 // anything at all and this code should be nuked with a tactical strike. 783 784 // If node should not be replaced, continue with the next one. 785 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 786 continue; 787 // Replace node. 788 if (ResNode) 789 ReplaceUses(Node, ResNode); 790 791 // If after the replacement this node is not used any more, 792 // remove this dead node. 793 if (Node->use_empty()) // Don't delete EntryToken, etc. 794 CurDAG->RemoveDeadNode(Node); 795 } 796 797 CurDAG->setRoot(Dummy.getValue()); 798 } 799 800 DEBUG(errs() << "===== Instruction selection ends:\n"); 801 802 PostprocessISelDAG(); 803 } 804 805 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 806 /// do other setup for EH landing-pad blocks. 807 void SelectionDAGISel::PrepareEHLandingPad() { 808 MachineBasicBlock *MBB = FuncInfo->MBB; 809 810 // Add a label to mark the beginning of the landing pad. Deletion of the 811 // landing pad can thus be detected via the MachineModuleInfo. 812 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 813 814 // Assign the call site to the landing pad's begin label. 815 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 816 817 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 818 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 819 .addSym(Label); 820 821 // Mark exception register as live in. 822 unsigned Reg = TLI.getExceptionPointerRegister(); 823 if (Reg) MBB->addLiveIn(Reg); 824 825 // Mark exception selector register as live in. 826 Reg = TLI.getExceptionSelectorRegister(); 827 if (Reg) MBB->addLiveIn(Reg); 828 } 829 830 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 831 /// load into the specified FoldInst. Note that we could have a sequence where 832 /// multiple LLVM IR instructions are folded into the same machineinstr. For 833 /// example we could have: 834 /// A: x = load i32 *P 835 /// B: y = icmp A, 42 836 /// C: br y, ... 837 /// 838 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 839 /// any other folded instructions) because it is between A and C. 840 /// 841 /// If we succeed in folding the load into the operation, return true. 842 /// 843 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 844 const Instruction *FoldInst, 845 FastISel *FastIS) { 846 // We know that the load has a single use, but don't know what it is. If it 847 // isn't one of the folded instructions, then we can't succeed here. Handle 848 // this by scanning the single-use users of the load until we get to FoldInst. 849 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 850 851 const Instruction *TheUser = LI->use_back(); 852 while (TheUser != FoldInst && // Scan up until we find FoldInst. 853 // Stay in the right block. 854 TheUser->getParent() == FoldInst->getParent() && 855 --MaxUsers) { // Don't scan too far. 856 // If there are multiple or no uses of this instruction, then bail out. 857 if (!TheUser->hasOneUse()) 858 return false; 859 860 TheUser = TheUser->use_back(); 861 } 862 863 // If we didn't find the fold instruction, then we failed to collapse the 864 // sequence. 865 if (TheUser != FoldInst) 866 return false; 867 868 // Don't try to fold volatile loads. Target has to deal with alignment 869 // constraints. 870 if (LI->isVolatile()) return false; 871 872 // Figure out which vreg this is going into. If there is no assigned vreg yet 873 // then there actually was no reference to it. Perhaps the load is referenced 874 // by a dead instruction. 875 unsigned LoadReg = FastIS->getRegForValue(LI); 876 if (LoadReg == 0) 877 return false; 878 879 // Check to see what the uses of this vreg are. If it has no uses, or more 880 // than one use (at the machine instr level) then we can't fold it. 881 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 882 if (RI == RegInfo->reg_end()) 883 return false; 884 885 // See if there is exactly one use of the vreg. If there are multiple uses, 886 // then the instruction got lowered to multiple machine instructions or the 887 // use of the loaded value ended up being multiple operands of the result, in 888 // either case, we can't fold this. 889 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 890 if (PostRI != RegInfo->reg_end()) 891 return false; 892 893 assert(RI.getOperand().isUse() && 894 "The only use of the vreg must be a use, we haven't emitted the def!"); 895 896 MachineInstr *User = &*RI; 897 898 // Set the insertion point properly. Folding the load can cause generation of 899 // other random instructions (like sign extends) for addressing modes, make 900 // sure they get inserted in a logical place before the new instruction. 901 FuncInfo->InsertPt = User; 902 FuncInfo->MBB = User->getParent(); 903 904 // Ask the target to try folding the load. 905 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 906 } 907 908 /// isFoldedOrDeadInstruction - Return true if the specified instruction is 909 /// side-effect free and is either dead or folded into a generated instruction. 910 /// Return false if it needs to be emitted. 911 static bool isFoldedOrDeadInstruction(const Instruction *I, 912 FunctionLoweringInfo *FuncInfo) { 913 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 914 !isa<TerminatorInst>(I) && // Terminators aren't folded. 915 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 916 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 917 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 918 } 919 920 #ifndef NDEBUG 921 // Collect per Instruction statistics for fast-isel misses. Only those 922 // instructions that cause the bail are accounted for. It does not account for 923 // instructions higher in the block. Thus, summing the per instructions stats 924 // will not add up to what is reported by NumFastIselFailures. 925 static void collectFailStats(const Instruction *I) { 926 switch (I->getOpcode()) { 927 default: assert (0 && "<Invalid operator> "); 928 929 // Terminators 930 case Instruction::Ret: NumFastIselFailRet++; return; 931 case Instruction::Br: NumFastIselFailBr++; return; 932 case Instruction::Switch: NumFastIselFailSwitch++; return; 933 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 934 case Instruction::Invoke: NumFastIselFailInvoke++; return; 935 case Instruction::Resume: NumFastIselFailResume++; return; 936 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 937 938 // Standard binary operators... 939 case Instruction::Add: NumFastIselFailAdd++; return; 940 case Instruction::FAdd: NumFastIselFailFAdd++; return; 941 case Instruction::Sub: NumFastIselFailSub++; return; 942 case Instruction::FSub: NumFastIselFailFSub++; return; 943 case Instruction::Mul: NumFastIselFailMul++; return; 944 case Instruction::FMul: NumFastIselFailFMul++; return; 945 case Instruction::UDiv: NumFastIselFailUDiv++; return; 946 case Instruction::SDiv: NumFastIselFailSDiv++; return; 947 case Instruction::FDiv: NumFastIselFailFDiv++; return; 948 case Instruction::URem: NumFastIselFailURem++; return; 949 case Instruction::SRem: NumFastIselFailSRem++; return; 950 case Instruction::FRem: NumFastIselFailFRem++; return; 951 952 // Logical operators... 953 case Instruction::And: NumFastIselFailAnd++; return; 954 case Instruction::Or: NumFastIselFailOr++; return; 955 case Instruction::Xor: NumFastIselFailXor++; return; 956 957 // Memory instructions... 958 case Instruction::Alloca: NumFastIselFailAlloca++; return; 959 case Instruction::Load: NumFastIselFailLoad++; return; 960 case Instruction::Store: NumFastIselFailStore++; return; 961 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 962 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 963 case Instruction::Fence: NumFastIselFailFence++; return; 964 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 965 966 // Convert instructions... 967 case Instruction::Trunc: NumFastIselFailTrunc++; return; 968 case Instruction::ZExt: NumFastIselFailZExt++; return; 969 case Instruction::SExt: NumFastIselFailSExt++; return; 970 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 971 case Instruction::FPExt: NumFastIselFailFPExt++; return; 972 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 973 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 974 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 975 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 976 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 977 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 978 case Instruction::BitCast: NumFastIselFailBitCast++; return; 979 980 // Other instructions... 981 case Instruction::ICmp: NumFastIselFailICmp++; return; 982 case Instruction::FCmp: NumFastIselFailFCmp++; return; 983 case Instruction::PHI: NumFastIselFailPHI++; return; 984 case Instruction::Select: NumFastIselFailSelect++; return; 985 case Instruction::Call: NumFastIselFailCall++; return; 986 case Instruction::Shl: NumFastIselFailShl++; return; 987 case Instruction::LShr: NumFastIselFailLShr++; return; 988 case Instruction::AShr: NumFastIselFailAShr++; return; 989 case Instruction::VAArg: NumFastIselFailVAArg++; return; 990 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 991 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 992 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 993 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 994 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 995 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 996 } 997 } 998 #endif 999 1000 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 1001 // Initialize the Fast-ISel state, if needed. 1002 FastISel *FastIS = 0; 1003 if (TM.Options.EnableFastISel) 1004 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 1005 1006 // Iterate over all basic blocks in the function. 1007 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 1008 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1009 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1010 const BasicBlock *LLVMBB = *I; 1011 1012 if (OptLevel != CodeGenOpt::None) { 1013 bool AllPredsVisited = true; 1014 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1015 PI != PE; ++PI) { 1016 if (!FuncInfo->VisitedBBs.count(*PI)) { 1017 AllPredsVisited = false; 1018 break; 1019 } 1020 } 1021 1022 if (AllPredsVisited) { 1023 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1024 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1025 FuncInfo->ComputePHILiveOutRegInfo(PN); 1026 } else { 1027 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1028 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1029 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1030 } 1031 1032 FuncInfo->VisitedBBs.insert(LLVMBB); 1033 } 1034 1035 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1036 BasicBlock::const_iterator const End = LLVMBB->end(); 1037 BasicBlock::const_iterator BI = End; 1038 1039 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1040 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1041 1042 // Setup an EH landing-pad block. 1043 if (FuncInfo->MBB->isLandingPad()) 1044 PrepareEHLandingPad(); 1045 1046 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1047 if (FastIS) { 1048 FastIS->startNewBlock(); 1049 1050 // Emit code for any incoming arguments. This must happen before 1051 // beginning FastISel on the entry block. 1052 if (LLVMBB == &Fn.getEntryBlock()) { 1053 // Lower any arguments needed in this block if this is the entry block. 1054 if (!FastIS->LowerArguments()) { 1055 // Fast isel failed to lower these arguments 1056 if (EnableFastISelAbortArgs) 1057 llvm_unreachable("FastISel didn't lower all arguments"); 1058 1059 // Use SelectionDAG argument lowering 1060 LowerArguments(Fn); 1061 CurDAG->setRoot(SDB->getControlRoot()); 1062 SDB->clear(); 1063 CodeGenAndEmitDAG(); 1064 } 1065 1066 // If we inserted any instructions at the beginning, make a note of 1067 // where they are, so we can be sure to emit subsequent instructions 1068 // after them. 1069 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1070 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1071 else 1072 FastIS->setLastLocalValue(0); 1073 } 1074 1075 unsigned NumFastIselRemaining = std::distance(Begin, End); 1076 // Do FastISel on as many instructions as possible. 1077 for (; BI != Begin; --BI) { 1078 const Instruction *Inst = llvm::prior(BI); 1079 1080 // If we no longer require this instruction, skip it. 1081 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1082 --NumFastIselRemaining; 1083 continue; 1084 } 1085 1086 // Bottom-up: reset the insert pos at the top, after any local-value 1087 // instructions. 1088 FastIS->recomputeInsertPt(); 1089 1090 // Try to select the instruction with FastISel. 1091 if (FastIS->SelectInstruction(Inst)) { 1092 --NumFastIselRemaining; 1093 ++NumFastIselSuccess; 1094 // If fast isel succeeded, skip over all the folded instructions, and 1095 // then see if there is a load right before the selected instructions. 1096 // Try to fold the load if so. 1097 const Instruction *BeforeInst = Inst; 1098 while (BeforeInst != Begin) { 1099 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1100 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1101 break; 1102 } 1103 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1104 BeforeInst->hasOneUse() && 1105 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) { 1106 // If we succeeded, don't re-select the load. 1107 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1108 --NumFastIselRemaining; 1109 ++NumFastIselSuccess; 1110 } 1111 continue; 1112 } 1113 1114 #ifndef NDEBUG 1115 if (EnableFastISelVerbose2) 1116 collectFailStats(Inst); 1117 #endif 1118 1119 // Then handle certain instructions as single-LLVM-Instruction blocks. 1120 if (isa<CallInst>(Inst)) { 1121 1122 if (EnableFastISelVerbose || EnableFastISelAbort) { 1123 dbgs() << "FastISel missed call: "; 1124 Inst->dump(); 1125 } 1126 1127 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1128 unsigned &R = FuncInfo->ValueMap[Inst]; 1129 if (!R) 1130 R = FuncInfo->CreateRegs(Inst->getType()); 1131 } 1132 1133 bool HadTailCall = false; 1134 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1135 SelectBasicBlock(Inst, BI, HadTailCall); 1136 1137 // If the call was emitted as a tail call, we're done with the block. 1138 // We also need to delete any previously emitted instructions. 1139 if (HadTailCall) { 1140 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1141 --BI; 1142 break; 1143 } 1144 1145 // Recompute NumFastIselRemaining as Selection DAG instruction 1146 // selection may have handled the call, input args, etc. 1147 unsigned RemainingNow = std::distance(Begin, BI); 1148 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1149 NumFastIselRemaining = RemainingNow; 1150 continue; 1151 } 1152 1153 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1154 // Don't abort, and use a different message for terminator misses. 1155 NumFastIselFailures += NumFastIselRemaining; 1156 if (EnableFastISelVerbose || EnableFastISelAbort) { 1157 dbgs() << "FastISel missed terminator: "; 1158 Inst->dump(); 1159 } 1160 } else { 1161 NumFastIselFailures += NumFastIselRemaining; 1162 if (EnableFastISelVerbose || EnableFastISelAbort) { 1163 dbgs() << "FastISel miss: "; 1164 Inst->dump(); 1165 } 1166 if (EnableFastISelAbort) 1167 // The "fast" selector couldn't handle something and bailed. 1168 // For the purpose of debugging, just abort. 1169 llvm_unreachable("FastISel didn't select the entire block"); 1170 } 1171 break; 1172 } 1173 1174 FastIS->recomputeInsertPt(); 1175 } else { 1176 // Lower any arguments needed in this block if this is the entry block. 1177 if (LLVMBB == &Fn.getEntryBlock()) 1178 LowerArguments(Fn); 1179 } 1180 1181 if (Begin != BI) 1182 ++NumDAGBlocks; 1183 else 1184 ++NumFastIselBlocks; 1185 1186 if (Begin != BI) { 1187 // Run SelectionDAG instruction selection on the remainder of the block 1188 // not handled by FastISel. If FastISel is not run, this is the entire 1189 // block. 1190 bool HadTailCall; 1191 SelectBasicBlock(Begin, BI, HadTailCall); 1192 } 1193 1194 FinishBasicBlock(); 1195 FuncInfo->PHINodesToUpdate.clear(); 1196 } 1197 1198 delete FastIS; 1199 SDB->clearDanglingDebugInfo(); 1200 } 1201 1202 void 1203 SelectionDAGISel::FinishBasicBlock() { 1204 1205 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1206 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1207 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1208 dbgs() << "Node " << i << " : (" 1209 << FuncInfo->PHINodesToUpdate[i].first 1210 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1211 1212 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1213 // PHI nodes in successors. 1214 if (SDB->SwitchCases.empty() && 1215 SDB->JTCases.empty() && 1216 SDB->BitTestCases.empty()) { 1217 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1218 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1219 assert(PHI->isPHI() && 1220 "This is not a machine PHI node that we are updating!"); 1221 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1222 continue; 1223 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1224 } 1225 return; 1226 } 1227 1228 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1229 // Lower header first, if it wasn't already lowered 1230 if (!SDB->BitTestCases[i].Emitted) { 1231 // Set the current basic block to the mbb we wish to insert the code into 1232 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1233 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1234 // Emit the code 1235 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1236 CurDAG->setRoot(SDB->getRoot()); 1237 SDB->clear(); 1238 CodeGenAndEmitDAG(); 1239 } 1240 1241 uint32_t UnhandledWeight = 0; 1242 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1243 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1244 1245 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1246 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1247 // Set the current basic block to the mbb we wish to insert the code into 1248 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1249 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1250 // Emit the code 1251 if (j+1 != ej) 1252 SDB->visitBitTestCase(SDB->BitTestCases[i], 1253 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1254 UnhandledWeight, 1255 SDB->BitTestCases[i].Reg, 1256 SDB->BitTestCases[i].Cases[j], 1257 FuncInfo->MBB); 1258 else 1259 SDB->visitBitTestCase(SDB->BitTestCases[i], 1260 SDB->BitTestCases[i].Default, 1261 UnhandledWeight, 1262 SDB->BitTestCases[i].Reg, 1263 SDB->BitTestCases[i].Cases[j], 1264 FuncInfo->MBB); 1265 1266 1267 CurDAG->setRoot(SDB->getRoot()); 1268 SDB->clear(); 1269 CodeGenAndEmitDAG(); 1270 } 1271 1272 // Update PHI Nodes 1273 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1274 pi != pe; ++pi) { 1275 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1276 MachineBasicBlock *PHIBB = PHI->getParent(); 1277 assert(PHI->isPHI() && 1278 "This is not a machine PHI node that we are updating!"); 1279 // This is "default" BB. We have two jumps to it. From "header" BB and 1280 // from last "case" BB. 1281 if (PHIBB == SDB->BitTestCases[i].Default) 1282 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1283 .addMBB(SDB->BitTestCases[i].Parent) 1284 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1285 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1286 // One of "cases" BB. 1287 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1288 j != ej; ++j) { 1289 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1290 if (cBB->isSuccessor(PHIBB)) 1291 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1292 } 1293 } 1294 } 1295 SDB->BitTestCases.clear(); 1296 1297 // If the JumpTable record is filled in, then we need to emit a jump table. 1298 // Updating the PHI nodes is tricky in this case, since we need to determine 1299 // whether the PHI is a successor of the range check MBB or the jump table MBB 1300 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1301 // Lower header first, if it wasn't already lowered 1302 if (!SDB->JTCases[i].first.Emitted) { 1303 // Set the current basic block to the mbb we wish to insert the code into 1304 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1305 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1306 // Emit the code 1307 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1308 FuncInfo->MBB); 1309 CurDAG->setRoot(SDB->getRoot()); 1310 SDB->clear(); 1311 CodeGenAndEmitDAG(); 1312 } 1313 1314 // Set the current basic block to the mbb we wish to insert the code into 1315 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1316 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1317 // Emit the code 1318 SDB->visitJumpTable(SDB->JTCases[i].second); 1319 CurDAG->setRoot(SDB->getRoot()); 1320 SDB->clear(); 1321 CodeGenAndEmitDAG(); 1322 1323 // Update PHI Nodes 1324 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1325 pi != pe; ++pi) { 1326 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1327 MachineBasicBlock *PHIBB = PHI->getParent(); 1328 assert(PHI->isPHI() && 1329 "This is not a machine PHI node that we are updating!"); 1330 // "default" BB. We can go there only from header BB. 1331 if (PHIBB == SDB->JTCases[i].second.Default) 1332 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1333 .addMBB(SDB->JTCases[i].first.HeaderBB); 1334 // JT BB. Just iterate over successors here 1335 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1336 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1337 } 1338 } 1339 SDB->JTCases.clear(); 1340 1341 // If the switch block involved a branch to one of the actual successors, we 1342 // need to update PHI nodes in that block. 1343 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1344 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1345 assert(PHI->isPHI() && 1346 "This is not a machine PHI node that we are updating!"); 1347 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1348 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1349 } 1350 1351 // If we generated any switch lowering information, build and codegen any 1352 // additional DAGs necessary. 1353 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1354 // Set the current basic block to the mbb we wish to insert the code into 1355 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1356 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1357 1358 // Determine the unique successors. 1359 SmallVector<MachineBasicBlock *, 2> Succs; 1360 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1361 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1362 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1363 1364 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1365 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1366 CurDAG->setRoot(SDB->getRoot()); 1367 SDB->clear(); 1368 CodeGenAndEmitDAG(); 1369 1370 // Remember the last block, now that any splitting is done, for use in 1371 // populating PHI nodes in successors. 1372 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1373 1374 // Handle any PHI nodes in successors of this chunk, as if we were coming 1375 // from the original BB before switch expansion. Note that PHI nodes can 1376 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1377 // handle them the right number of times. 1378 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1379 FuncInfo->MBB = Succs[i]; 1380 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1381 // FuncInfo->MBB may have been removed from the CFG if a branch was 1382 // constant folded. 1383 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1384 for (MachineBasicBlock::iterator 1385 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1386 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1387 MachineInstrBuilder PHI(*MF, MBBI); 1388 // This value for this PHI node is recorded in PHINodesToUpdate. 1389 for (unsigned pn = 0; ; ++pn) { 1390 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1391 "Didn't find PHI entry!"); 1392 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1393 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1394 break; 1395 } 1396 } 1397 } 1398 } 1399 } 1400 } 1401 SDB->SwitchCases.clear(); 1402 } 1403 1404 1405 /// Create the scheduler. If a specific scheduler was specified 1406 /// via the SchedulerRegistry, use it, otherwise select the 1407 /// one preferred by the target. 1408 /// 1409 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1410 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1411 1412 if (!Ctor) { 1413 Ctor = ISHeuristic; 1414 RegisterScheduler::setDefault(Ctor); 1415 } 1416 1417 return Ctor(this, OptLevel); 1418 } 1419 1420 //===----------------------------------------------------------------------===// 1421 // Helper functions used by the generated instruction selector. 1422 //===----------------------------------------------------------------------===// 1423 // Calls to these methods are generated by tblgen. 1424 1425 /// CheckAndMask - The isel is trying to match something like (and X, 255). If 1426 /// the dag combiner simplified the 255, we still want to match. RHS is the 1427 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1428 /// specified in the .td file (e.g. 255). 1429 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1430 int64_t DesiredMaskS) const { 1431 const APInt &ActualMask = RHS->getAPIntValue(); 1432 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1433 1434 // If the actual mask exactly matches, success! 1435 if (ActualMask == DesiredMask) 1436 return true; 1437 1438 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1439 if (ActualMask.intersects(~DesiredMask)) 1440 return false; 1441 1442 // Otherwise, the DAG Combiner may have proven that the value coming in is 1443 // either already zero or is not demanded. Check for known zero input bits. 1444 APInt NeededMask = DesiredMask & ~ActualMask; 1445 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1446 return true; 1447 1448 // TODO: check to see if missing bits are just not demanded. 1449 1450 // Otherwise, this pattern doesn't match. 1451 return false; 1452 } 1453 1454 /// CheckOrMask - The isel is trying to match something like (or X, 255). If 1455 /// the dag combiner simplified the 255, we still want to match. RHS is the 1456 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1457 /// specified in the .td file (e.g. 255). 1458 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1459 int64_t DesiredMaskS) const { 1460 const APInt &ActualMask = RHS->getAPIntValue(); 1461 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1462 1463 // If the actual mask exactly matches, success! 1464 if (ActualMask == DesiredMask) 1465 return true; 1466 1467 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1468 if (ActualMask.intersects(~DesiredMask)) 1469 return false; 1470 1471 // Otherwise, the DAG Combiner may have proven that the value coming in is 1472 // either already zero or is not demanded. Check for known zero input bits. 1473 APInt NeededMask = DesiredMask & ~ActualMask; 1474 1475 APInt KnownZero, KnownOne; 1476 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1477 1478 // If all the missing bits in the or are already known to be set, match! 1479 if ((NeededMask & KnownOne) == NeededMask) 1480 return true; 1481 1482 // TODO: check to see if missing bits are just not demanded. 1483 1484 // Otherwise, this pattern doesn't match. 1485 return false; 1486 } 1487 1488 1489 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1490 /// by tblgen. Others should not call it. 1491 void SelectionDAGISel:: 1492 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1493 std::vector<SDValue> InOps; 1494 std::swap(InOps, Ops); 1495 1496 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1497 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1498 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1499 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1500 1501 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1502 if (InOps[e-1].getValueType() == MVT::Glue) 1503 --e; // Don't process a glue operand if it is here. 1504 1505 while (i != e) { 1506 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1507 if (!InlineAsm::isMemKind(Flags)) { 1508 // Just skip over this operand, copying the operands verbatim. 1509 Ops.insert(Ops.end(), InOps.begin()+i, 1510 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1511 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1512 } else { 1513 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1514 "Memory operand with multiple values?"); 1515 // Otherwise, this is a memory operand. Ask the target to select it. 1516 std::vector<SDValue> SelOps; 1517 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1518 report_fatal_error("Could not match memory address. Inline asm" 1519 " failure!"); 1520 1521 // Add this to the output node. 1522 unsigned NewFlags = 1523 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1524 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1525 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1526 i += 2; 1527 } 1528 } 1529 1530 // Add the glue input back if present. 1531 if (e != InOps.size()) 1532 Ops.push_back(InOps.back()); 1533 } 1534 1535 /// findGlueUse - Return use of MVT::Glue value produced by the specified 1536 /// SDNode. 1537 /// 1538 static SDNode *findGlueUse(SDNode *N) { 1539 unsigned FlagResNo = N->getNumValues()-1; 1540 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1541 SDUse &Use = I.getUse(); 1542 if (Use.getResNo() == FlagResNo) 1543 return Use.getUser(); 1544 } 1545 return NULL; 1546 } 1547 1548 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1549 /// This function recursively traverses up the operand chain, ignoring 1550 /// certain nodes. 1551 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1552 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1553 bool IgnoreChains) { 1554 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1555 // greater than all of its (recursive) operands. If we scan to a point where 1556 // 'use' is smaller than the node we're scanning for, then we know we will 1557 // never find it. 1558 // 1559 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1560 // happen because we scan down to newly selected nodes in the case of glue 1561 // uses. 1562 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1563 return false; 1564 1565 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1566 // won't fail if we scan it again. 1567 if (!Visited.insert(Use)) 1568 return false; 1569 1570 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1571 // Ignore chain uses, they are validated by HandleMergeInputChains. 1572 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1573 continue; 1574 1575 SDNode *N = Use->getOperand(i).getNode(); 1576 if (N == Def) { 1577 if (Use == ImmedUse || Use == Root) 1578 continue; // We are not looking for immediate use. 1579 assert(N != Root); 1580 return true; 1581 } 1582 1583 // Traverse up the operand chain. 1584 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1585 return true; 1586 } 1587 return false; 1588 } 1589 1590 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 1591 /// operand node N of U during instruction selection that starts at Root. 1592 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1593 SDNode *Root) const { 1594 if (OptLevel == CodeGenOpt::None) return false; 1595 return N.hasOneUse(); 1596 } 1597 1598 /// IsLegalToFold - Returns true if the specific operand node N of 1599 /// U can be folded during instruction selection that starts at Root. 1600 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1601 CodeGenOpt::Level OptLevel, 1602 bool IgnoreChains) { 1603 if (OptLevel == CodeGenOpt::None) return false; 1604 1605 // If Root use can somehow reach N through a path that that doesn't contain 1606 // U then folding N would create a cycle. e.g. In the following 1607 // diagram, Root can reach N through X. If N is folded into into Root, then 1608 // X is both a predecessor and a successor of U. 1609 // 1610 // [N*] // 1611 // ^ ^ // 1612 // / \ // 1613 // [U*] [X]? // 1614 // ^ ^ // 1615 // \ / // 1616 // \ / // 1617 // [Root*] // 1618 // 1619 // * indicates nodes to be folded together. 1620 // 1621 // If Root produces glue, then it gets (even more) interesting. Since it 1622 // will be "glued" together with its glue use in the scheduler, we need to 1623 // check if it might reach N. 1624 // 1625 // [N*] // 1626 // ^ ^ // 1627 // / \ // 1628 // [U*] [X]? // 1629 // ^ ^ // 1630 // \ \ // 1631 // \ | // 1632 // [Root*] | // 1633 // ^ | // 1634 // f | // 1635 // | / // 1636 // [Y] / // 1637 // ^ / // 1638 // f / // 1639 // | / // 1640 // [GU] // 1641 // 1642 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1643 // (call it Fold), then X is a predecessor of GU and a successor of 1644 // Fold. But since Fold and GU are glued together, this will create 1645 // a cycle in the scheduling graph. 1646 1647 // If the node has glue, walk down the graph to the "lowest" node in the 1648 // glueged set. 1649 EVT VT = Root->getValueType(Root->getNumValues()-1); 1650 while (VT == MVT::Glue) { 1651 SDNode *GU = findGlueUse(Root); 1652 if (GU == NULL) 1653 break; 1654 Root = GU; 1655 VT = Root->getValueType(Root->getNumValues()-1); 1656 1657 // If our query node has a glue result with a use, we've walked up it. If 1658 // the user (which has already been selected) has a chain or indirectly uses 1659 // the chain, our WalkChainUsers predicate will not consider it. Because of 1660 // this, we cannot ignore chains in this predicate. 1661 IgnoreChains = false; 1662 } 1663 1664 1665 SmallPtrSet<SDNode*, 16> Visited; 1666 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1667 } 1668 1669 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1670 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1671 SelectInlineAsmMemoryOperands(Ops); 1672 1673 EVT VTs[] = { MVT::Other, MVT::Glue }; 1674 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1675 VTs, &Ops[0], Ops.size()); 1676 New->setNodeId(-1); 1677 return New.getNode(); 1678 } 1679 1680 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1681 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1682 } 1683 1684 /// GetVBR - decode a vbr encoding whose top bit is set. 1685 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1686 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1687 assert(Val >= 128 && "Not a VBR"); 1688 Val &= 127; // Remove first vbr bit. 1689 1690 unsigned Shift = 7; 1691 uint64_t NextBits; 1692 do { 1693 NextBits = MatcherTable[Idx++]; 1694 Val |= (NextBits&127) << Shift; 1695 Shift += 7; 1696 } while (NextBits & 128); 1697 1698 return Val; 1699 } 1700 1701 1702 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1703 /// interior glue and chain results to use the new glue and chain results. 1704 void SelectionDAGISel:: 1705 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1706 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1707 SDValue InputGlue, 1708 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1709 bool isMorphNodeTo) { 1710 SmallVector<SDNode*, 4> NowDeadNodes; 1711 1712 // Now that all the normal results are replaced, we replace the chain and 1713 // glue results if present. 1714 if (!ChainNodesMatched.empty()) { 1715 assert(InputChain.getNode() != 0 && 1716 "Matched input chains but didn't produce a chain"); 1717 // Loop over all of the nodes we matched that produced a chain result. 1718 // Replace all the chain results with the final chain we ended up with. 1719 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1720 SDNode *ChainNode = ChainNodesMatched[i]; 1721 1722 // If this node was already deleted, don't look at it. 1723 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1724 continue; 1725 1726 // Don't replace the results of the root node if we're doing a 1727 // MorphNodeTo. 1728 if (ChainNode == NodeToMatch && isMorphNodeTo) 1729 continue; 1730 1731 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1732 if (ChainVal.getValueType() == MVT::Glue) 1733 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1734 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1735 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1736 1737 // If the node became dead and we haven't already seen it, delete it. 1738 if (ChainNode->use_empty() && 1739 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1740 NowDeadNodes.push_back(ChainNode); 1741 } 1742 } 1743 1744 // If the result produces glue, update any glue results in the matched 1745 // pattern with the glue result. 1746 if (InputGlue.getNode() != 0) { 1747 // Handle any interior nodes explicitly marked. 1748 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1749 SDNode *FRN = GlueResultNodesMatched[i]; 1750 1751 // If this node was already deleted, don't look at it. 1752 if (FRN->getOpcode() == ISD::DELETED_NODE) 1753 continue; 1754 1755 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1756 "Doesn't have a glue result"); 1757 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1758 InputGlue); 1759 1760 // If the node became dead and we haven't already seen it, delete it. 1761 if (FRN->use_empty() && 1762 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1763 NowDeadNodes.push_back(FRN); 1764 } 1765 } 1766 1767 if (!NowDeadNodes.empty()) 1768 CurDAG->RemoveDeadNodes(NowDeadNodes); 1769 1770 DEBUG(errs() << "ISEL: Match complete!\n"); 1771 } 1772 1773 enum ChainResult { 1774 CR_Simple, 1775 CR_InducesCycle, 1776 CR_LeadsToInteriorNode 1777 }; 1778 1779 /// WalkChainUsers - Walk down the users of the specified chained node that is 1780 /// part of the pattern we're matching, looking at all of the users we find. 1781 /// This determines whether something is an interior node, whether we have a 1782 /// non-pattern node in between two pattern nodes (which prevent folding because 1783 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1784 /// between pattern nodes (in which case the TF becomes part of the pattern). 1785 /// 1786 /// The walk we do here is guaranteed to be small because we quickly get down to 1787 /// already selected nodes "below" us. 1788 static ChainResult 1789 WalkChainUsers(const SDNode *ChainedNode, 1790 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1791 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1792 ChainResult Result = CR_Simple; 1793 1794 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1795 E = ChainedNode->use_end(); UI != E; ++UI) { 1796 // Make sure the use is of the chain, not some other value we produce. 1797 if (UI.getUse().getValueType() != MVT::Other) continue; 1798 1799 SDNode *User = *UI; 1800 1801 // If we see an already-selected machine node, then we've gone beyond the 1802 // pattern that we're selecting down into the already selected chunk of the 1803 // DAG. 1804 if (User->isMachineOpcode() || 1805 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1806 continue; 1807 1808 unsigned UserOpcode = User->getOpcode(); 1809 if (UserOpcode == ISD::CopyToReg || 1810 UserOpcode == ISD::CopyFromReg || 1811 UserOpcode == ISD::INLINEASM || 1812 UserOpcode == ISD::EH_LABEL || 1813 UserOpcode == ISD::LIFETIME_START || 1814 UserOpcode == ISD::LIFETIME_END) { 1815 // If their node ID got reset to -1 then they've already been selected. 1816 // Treat them like a MachineOpcode. 1817 if (User->getNodeId() == -1) 1818 continue; 1819 } 1820 1821 // If we have a TokenFactor, we handle it specially. 1822 if (User->getOpcode() != ISD::TokenFactor) { 1823 // If the node isn't a token factor and isn't part of our pattern, then it 1824 // must be a random chained node in between two nodes we're selecting. 1825 // This happens when we have something like: 1826 // x = load ptr 1827 // call 1828 // y = x+4 1829 // store y -> ptr 1830 // Because we structurally match the load/store as a read/modify/write, 1831 // but the call is chained between them. We cannot fold in this case 1832 // because it would induce a cycle in the graph. 1833 if (!std::count(ChainedNodesInPattern.begin(), 1834 ChainedNodesInPattern.end(), User)) 1835 return CR_InducesCycle; 1836 1837 // Otherwise we found a node that is part of our pattern. For example in: 1838 // x = load ptr 1839 // y = x+4 1840 // store y -> ptr 1841 // This would happen when we're scanning down from the load and see the 1842 // store as a user. Record that there is a use of ChainedNode that is 1843 // part of the pattern and keep scanning uses. 1844 Result = CR_LeadsToInteriorNode; 1845 InteriorChainedNodes.push_back(User); 1846 continue; 1847 } 1848 1849 // If we found a TokenFactor, there are two cases to consider: first if the 1850 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1851 // uses of the TF are in our pattern) we just want to ignore it. Second, 1852 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1853 // [Load chain] 1854 // ^ 1855 // | 1856 // [Load] 1857 // ^ ^ 1858 // | \ DAG's like cheese 1859 // / \ do you? 1860 // / | 1861 // [TokenFactor] [Op] 1862 // ^ ^ 1863 // | | 1864 // \ / 1865 // \ / 1866 // [Store] 1867 // 1868 // In this case, the TokenFactor becomes part of our match and we rewrite it 1869 // as a new TokenFactor. 1870 // 1871 // To distinguish these two cases, do a recursive walk down the uses. 1872 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1873 case CR_Simple: 1874 // If the uses of the TokenFactor are just already-selected nodes, ignore 1875 // it, it is "below" our pattern. 1876 continue; 1877 case CR_InducesCycle: 1878 // If the uses of the TokenFactor lead to nodes that are not part of our 1879 // pattern that are not selected, folding would turn this into a cycle, 1880 // bail out now. 1881 return CR_InducesCycle; 1882 case CR_LeadsToInteriorNode: 1883 break; // Otherwise, keep processing. 1884 } 1885 1886 // Okay, we know we're in the interesting interior case. The TokenFactor 1887 // is now going to be considered part of the pattern so that we rewrite its 1888 // uses (it may have uses that are not part of the pattern) with the 1889 // ultimate chain result of the generated code. We will also add its chain 1890 // inputs as inputs to the ultimate TokenFactor we create. 1891 Result = CR_LeadsToInteriorNode; 1892 ChainedNodesInPattern.push_back(User); 1893 InteriorChainedNodes.push_back(User); 1894 continue; 1895 } 1896 1897 return Result; 1898 } 1899 1900 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1901 /// operation for when the pattern matched at least one node with a chains. The 1902 /// input vector contains a list of all of the chained nodes that we match. We 1903 /// must determine if this is a valid thing to cover (i.e. matching it won't 1904 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1905 /// be used as the input node chain for the generated nodes. 1906 static SDValue 1907 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1908 SelectionDAG *CurDAG) { 1909 // Walk all of the chained nodes we've matched, recursively scanning down the 1910 // users of the chain result. This adds any TokenFactor nodes that are caught 1911 // in between chained nodes to the chained and interior nodes list. 1912 SmallVector<SDNode*, 3> InteriorChainedNodes; 1913 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1914 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1915 InteriorChainedNodes) == CR_InducesCycle) 1916 return SDValue(); // Would induce a cycle. 1917 } 1918 1919 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1920 // that we are interested in. Form our input TokenFactor node. 1921 SmallVector<SDValue, 3> InputChains; 1922 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1923 // Add the input chain of this node to the InputChains list (which will be 1924 // the operands of the generated TokenFactor) if it's not an interior node. 1925 SDNode *N = ChainNodesMatched[i]; 1926 if (N->getOpcode() != ISD::TokenFactor) { 1927 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1928 continue; 1929 1930 // Otherwise, add the input chain. 1931 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1932 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1933 InputChains.push_back(InChain); 1934 continue; 1935 } 1936 1937 // If we have a token factor, we want to add all inputs of the token factor 1938 // that are not part of the pattern we're matching. 1939 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1940 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1941 N->getOperand(op).getNode())) 1942 InputChains.push_back(N->getOperand(op)); 1943 } 1944 } 1945 1946 SDValue Res; 1947 if (InputChains.size() == 1) 1948 return InputChains[0]; 1949 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1950 MVT::Other, &InputChains[0], InputChains.size()); 1951 } 1952 1953 /// MorphNode - Handle morphing a node in place for the selector. 1954 SDNode *SelectionDAGISel:: 1955 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1956 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1957 // It is possible we're using MorphNodeTo to replace a node with no 1958 // normal results with one that has a normal result (or we could be 1959 // adding a chain) and the input could have glue and chains as well. 1960 // In this case we need to shift the operands down. 1961 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1962 // than the old isel though. 1963 int OldGlueResultNo = -1, OldChainResultNo = -1; 1964 1965 unsigned NTMNumResults = Node->getNumValues(); 1966 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1967 OldGlueResultNo = NTMNumResults-1; 1968 if (NTMNumResults != 1 && 1969 Node->getValueType(NTMNumResults-2) == MVT::Other) 1970 OldChainResultNo = NTMNumResults-2; 1971 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1972 OldChainResultNo = NTMNumResults-1; 1973 1974 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1975 // that this deletes operands of the old node that become dead. 1976 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1977 1978 // MorphNodeTo can operate in two ways: if an existing node with the 1979 // specified operands exists, it can just return it. Otherwise, it 1980 // updates the node in place to have the requested operands. 1981 if (Res == Node) { 1982 // If we updated the node in place, reset the node ID. To the isel, 1983 // this should be just like a newly allocated machine node. 1984 Res->setNodeId(-1); 1985 } 1986 1987 unsigned ResNumResults = Res->getNumValues(); 1988 // Move the glue if needed. 1989 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1990 (unsigned)OldGlueResultNo != ResNumResults-1) 1991 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1992 SDValue(Res, ResNumResults-1)); 1993 1994 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1995 --ResNumResults; 1996 1997 // Move the chain reference if needed. 1998 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1999 (unsigned)OldChainResultNo != ResNumResults-1) 2000 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2001 SDValue(Res, ResNumResults-1)); 2002 2003 // Otherwise, no replacement happened because the node already exists. Replace 2004 // Uses of the old node with the new one. 2005 if (Res != Node) 2006 CurDAG->ReplaceAllUsesWith(Node, Res); 2007 2008 return Res; 2009 } 2010 2011 /// CheckSame - Implements OP_CheckSame. 2012 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2013 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2014 SDValue N, 2015 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2016 // Accept if it is exactly the same as a previously recorded node. 2017 unsigned RecNo = MatcherTable[MatcherIndex++]; 2018 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2019 return N == RecordedNodes[RecNo].first; 2020 } 2021 2022 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2023 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2024 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2025 const SelectionDAGISel &SDISel) { 2026 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2027 } 2028 2029 /// CheckNodePredicate - Implements OP_CheckNodePredicate. 2030 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2031 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2032 const SelectionDAGISel &SDISel, SDNode *N) { 2033 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2034 } 2035 2036 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2037 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2038 SDNode *N) { 2039 uint16_t Opc = MatcherTable[MatcherIndex++]; 2040 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2041 return N->getOpcode() == Opc; 2042 } 2043 2044 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2045 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2046 SDValue N, const TargetLowering &TLI) { 2047 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2048 if (N.getValueType() == VT) return true; 2049 2050 // Handle the case when VT is iPTR. 2051 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 2052 } 2053 2054 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2055 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2056 SDValue N, const TargetLowering &TLI, 2057 unsigned ChildNo) { 2058 if (ChildNo >= N.getNumOperands()) 2059 return false; // Match fails if out of range child #. 2060 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2061 } 2062 2063 2064 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2065 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2066 SDValue N) { 2067 return cast<CondCodeSDNode>(N)->get() == 2068 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2069 } 2070 2071 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2072 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2073 SDValue N, const TargetLowering &TLI) { 2074 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2075 if (cast<VTSDNode>(N)->getVT() == VT) 2076 return true; 2077 2078 // Handle the case when VT is iPTR. 2079 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2080 } 2081 2082 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2083 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2084 SDValue N) { 2085 int64_t Val = MatcherTable[MatcherIndex++]; 2086 if (Val & 128) 2087 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2088 2089 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2090 return C != 0 && C->getSExtValue() == Val; 2091 } 2092 2093 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2094 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2095 SDValue N, const SelectionDAGISel &SDISel) { 2096 int64_t Val = MatcherTable[MatcherIndex++]; 2097 if (Val & 128) 2098 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2099 2100 if (N->getOpcode() != ISD::AND) return false; 2101 2102 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2103 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2104 } 2105 2106 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2107 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2108 SDValue N, const SelectionDAGISel &SDISel) { 2109 int64_t Val = MatcherTable[MatcherIndex++]; 2110 if (Val & 128) 2111 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2112 2113 if (N->getOpcode() != ISD::OR) return false; 2114 2115 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2116 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2117 } 2118 2119 /// IsPredicateKnownToFail - If we know how and can do so without pushing a 2120 /// scope, evaluate the current node. If the current predicate is known to 2121 /// fail, set Result=true and return anything. If the current predicate is 2122 /// known to pass, set Result=false and return the MatcherIndex to continue 2123 /// with. If the current predicate is unknown, set Result=false and return the 2124 /// MatcherIndex to continue with. 2125 static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2126 unsigned Index, SDValue N, 2127 bool &Result, 2128 const SelectionDAGISel &SDISel, 2129 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2130 switch (Table[Index++]) { 2131 default: 2132 Result = false; 2133 return Index-1; // Could not evaluate this predicate. 2134 case SelectionDAGISel::OPC_CheckSame: 2135 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2136 return Index; 2137 case SelectionDAGISel::OPC_CheckPatternPredicate: 2138 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2139 return Index; 2140 case SelectionDAGISel::OPC_CheckPredicate: 2141 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2142 return Index; 2143 case SelectionDAGISel::OPC_CheckOpcode: 2144 Result = !::CheckOpcode(Table, Index, N.getNode()); 2145 return Index; 2146 case SelectionDAGISel::OPC_CheckType: 2147 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2148 return Index; 2149 case SelectionDAGISel::OPC_CheckChild0Type: 2150 case SelectionDAGISel::OPC_CheckChild1Type: 2151 case SelectionDAGISel::OPC_CheckChild2Type: 2152 case SelectionDAGISel::OPC_CheckChild3Type: 2153 case SelectionDAGISel::OPC_CheckChild4Type: 2154 case SelectionDAGISel::OPC_CheckChild5Type: 2155 case SelectionDAGISel::OPC_CheckChild6Type: 2156 case SelectionDAGISel::OPC_CheckChild7Type: 2157 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2158 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2159 return Index; 2160 case SelectionDAGISel::OPC_CheckCondCode: 2161 Result = !::CheckCondCode(Table, Index, N); 2162 return Index; 2163 case SelectionDAGISel::OPC_CheckValueType: 2164 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2165 return Index; 2166 case SelectionDAGISel::OPC_CheckInteger: 2167 Result = !::CheckInteger(Table, Index, N); 2168 return Index; 2169 case SelectionDAGISel::OPC_CheckAndImm: 2170 Result = !::CheckAndImm(Table, Index, N, SDISel); 2171 return Index; 2172 case SelectionDAGISel::OPC_CheckOrImm: 2173 Result = !::CheckOrImm(Table, Index, N, SDISel); 2174 return Index; 2175 } 2176 } 2177 2178 namespace { 2179 2180 struct MatchScope { 2181 /// FailIndex - If this match fails, this is the index to continue with. 2182 unsigned FailIndex; 2183 2184 /// NodeStack - The node stack when the scope was formed. 2185 SmallVector<SDValue, 4> NodeStack; 2186 2187 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2188 unsigned NumRecordedNodes; 2189 2190 /// NumMatchedMemRefs - The number of matched memref entries. 2191 unsigned NumMatchedMemRefs; 2192 2193 /// InputChain/InputGlue - The current chain/glue 2194 SDValue InputChain, InputGlue; 2195 2196 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2197 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2198 }; 2199 2200 } 2201 2202 SDNode *SelectionDAGISel:: 2203 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2204 unsigned TableSize) { 2205 // FIXME: Should these even be selected? Handle these cases in the caller? 2206 switch (NodeToMatch->getOpcode()) { 2207 default: 2208 break; 2209 case ISD::EntryToken: // These nodes remain the same. 2210 case ISD::BasicBlock: 2211 case ISD::Register: 2212 case ISD::RegisterMask: 2213 //case ISD::VALUETYPE: 2214 //case ISD::CONDCODE: 2215 case ISD::HANDLENODE: 2216 case ISD::MDNODE_SDNODE: 2217 case ISD::TargetConstant: 2218 case ISD::TargetConstantFP: 2219 case ISD::TargetConstantPool: 2220 case ISD::TargetFrameIndex: 2221 case ISD::TargetExternalSymbol: 2222 case ISD::TargetBlockAddress: 2223 case ISD::TargetJumpTable: 2224 case ISD::TargetGlobalTLSAddress: 2225 case ISD::TargetGlobalAddress: 2226 case ISD::TokenFactor: 2227 case ISD::CopyFromReg: 2228 case ISD::CopyToReg: 2229 case ISD::EH_LABEL: 2230 case ISD::LIFETIME_START: 2231 case ISD::LIFETIME_END: 2232 NodeToMatch->setNodeId(-1); // Mark selected. 2233 return 0; 2234 case ISD::AssertSext: 2235 case ISD::AssertZext: 2236 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2237 NodeToMatch->getOperand(0)); 2238 return 0; 2239 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2240 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2241 } 2242 2243 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2244 2245 // Set up the node stack with NodeToMatch as the only node on the stack. 2246 SmallVector<SDValue, 8> NodeStack; 2247 SDValue N = SDValue(NodeToMatch, 0); 2248 NodeStack.push_back(N); 2249 2250 // MatchScopes - Scopes used when matching, if a match failure happens, this 2251 // indicates where to continue checking. 2252 SmallVector<MatchScope, 8> MatchScopes; 2253 2254 // RecordedNodes - This is the set of nodes that have been recorded by the 2255 // state machine. The second value is the parent of the node, or null if the 2256 // root is recorded. 2257 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2258 2259 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2260 // pattern. 2261 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2262 2263 // These are the current input chain and glue for use when generating nodes. 2264 // Various Emit operations change these. For example, emitting a copytoreg 2265 // uses and updates these. 2266 SDValue InputChain, InputGlue; 2267 2268 // ChainNodesMatched - If a pattern matches nodes that have input/output 2269 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2270 // which ones they are. The result is captured into this list so that we can 2271 // update the chain results when the pattern is complete. 2272 SmallVector<SDNode*, 3> ChainNodesMatched; 2273 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2274 2275 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2276 NodeToMatch->dump(CurDAG); 2277 errs() << '\n'); 2278 2279 // Determine where to start the interpreter. Normally we start at opcode #0, 2280 // but if the state machine starts with an OPC_SwitchOpcode, then we 2281 // accelerate the first lookup (which is guaranteed to be hot) with the 2282 // OpcodeOffset table. 2283 unsigned MatcherIndex = 0; 2284 2285 if (!OpcodeOffset.empty()) { 2286 // Already computed the OpcodeOffset table, just index into it. 2287 if (N.getOpcode() < OpcodeOffset.size()) 2288 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2289 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2290 2291 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2292 // Otherwise, the table isn't computed, but the state machine does start 2293 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2294 // is the first time we're selecting an instruction. 2295 unsigned Idx = 1; 2296 while (1) { 2297 // Get the size of this case. 2298 unsigned CaseSize = MatcherTable[Idx++]; 2299 if (CaseSize & 128) 2300 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2301 if (CaseSize == 0) break; 2302 2303 // Get the opcode, add the index to the table. 2304 uint16_t Opc = MatcherTable[Idx++]; 2305 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2306 if (Opc >= OpcodeOffset.size()) 2307 OpcodeOffset.resize((Opc+1)*2); 2308 OpcodeOffset[Opc] = Idx; 2309 Idx += CaseSize; 2310 } 2311 2312 // Okay, do the lookup for the first opcode. 2313 if (N.getOpcode() < OpcodeOffset.size()) 2314 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2315 } 2316 2317 while (1) { 2318 assert(MatcherIndex < TableSize && "Invalid index"); 2319 #ifndef NDEBUG 2320 unsigned CurrentOpcodeIndex = MatcherIndex; 2321 #endif 2322 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2323 switch (Opcode) { 2324 case OPC_Scope: { 2325 // Okay, the semantics of this operation are that we should push a scope 2326 // then evaluate the first child. However, pushing a scope only to have 2327 // the first check fail (which then pops it) is inefficient. If we can 2328 // determine immediately that the first check (or first several) will 2329 // immediately fail, don't even bother pushing a scope for them. 2330 unsigned FailIndex; 2331 2332 while (1) { 2333 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2334 if (NumToSkip & 128) 2335 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2336 // Found the end of the scope with no match. 2337 if (NumToSkip == 0) { 2338 FailIndex = 0; 2339 break; 2340 } 2341 2342 FailIndex = MatcherIndex+NumToSkip; 2343 2344 unsigned MatcherIndexOfPredicate = MatcherIndex; 2345 (void)MatcherIndexOfPredicate; // silence warning. 2346 2347 // If we can't evaluate this predicate without pushing a scope (e.g. if 2348 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2349 // push the scope and evaluate the full predicate chain. 2350 bool Result; 2351 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2352 Result, *this, RecordedNodes); 2353 if (!Result) 2354 break; 2355 2356 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2357 << "index " << MatcherIndexOfPredicate 2358 << ", continuing at " << FailIndex << "\n"); 2359 ++NumDAGIselRetries; 2360 2361 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2362 // move to the next case. 2363 MatcherIndex = FailIndex; 2364 } 2365 2366 // If the whole scope failed to match, bail. 2367 if (FailIndex == 0) break; 2368 2369 // Push a MatchScope which indicates where to go if the first child fails 2370 // to match. 2371 MatchScope NewEntry; 2372 NewEntry.FailIndex = FailIndex; 2373 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2374 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2375 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2376 NewEntry.InputChain = InputChain; 2377 NewEntry.InputGlue = InputGlue; 2378 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2379 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2380 MatchScopes.push_back(NewEntry); 2381 continue; 2382 } 2383 case OPC_RecordNode: { 2384 // Remember this node, it may end up being an operand in the pattern. 2385 SDNode *Parent = 0; 2386 if (NodeStack.size() > 1) 2387 Parent = NodeStack[NodeStack.size()-2].getNode(); 2388 RecordedNodes.push_back(std::make_pair(N, Parent)); 2389 continue; 2390 } 2391 2392 case OPC_RecordChild0: case OPC_RecordChild1: 2393 case OPC_RecordChild2: case OPC_RecordChild3: 2394 case OPC_RecordChild4: case OPC_RecordChild5: 2395 case OPC_RecordChild6: case OPC_RecordChild7: { 2396 unsigned ChildNo = Opcode-OPC_RecordChild0; 2397 if (ChildNo >= N.getNumOperands()) 2398 break; // Match fails if out of range child #. 2399 2400 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2401 N.getNode())); 2402 continue; 2403 } 2404 case OPC_RecordMemRef: 2405 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2406 continue; 2407 2408 case OPC_CaptureGlueInput: 2409 // If the current node has an input glue, capture it in InputGlue. 2410 if (N->getNumOperands() != 0 && 2411 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2412 InputGlue = N->getOperand(N->getNumOperands()-1); 2413 continue; 2414 2415 case OPC_MoveChild: { 2416 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2417 if (ChildNo >= N.getNumOperands()) 2418 break; // Match fails if out of range child #. 2419 N = N.getOperand(ChildNo); 2420 NodeStack.push_back(N); 2421 continue; 2422 } 2423 2424 case OPC_MoveParent: 2425 // Pop the current node off the NodeStack. 2426 NodeStack.pop_back(); 2427 assert(!NodeStack.empty() && "Node stack imbalance!"); 2428 N = NodeStack.back(); 2429 continue; 2430 2431 case OPC_CheckSame: 2432 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2433 continue; 2434 case OPC_CheckPatternPredicate: 2435 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2436 continue; 2437 case OPC_CheckPredicate: 2438 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2439 N.getNode())) 2440 break; 2441 continue; 2442 case OPC_CheckComplexPat: { 2443 unsigned CPNum = MatcherTable[MatcherIndex++]; 2444 unsigned RecNo = MatcherTable[MatcherIndex++]; 2445 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2446 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2447 RecordedNodes[RecNo].first, CPNum, 2448 RecordedNodes)) 2449 break; 2450 continue; 2451 } 2452 case OPC_CheckOpcode: 2453 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2454 continue; 2455 2456 case OPC_CheckType: 2457 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2458 continue; 2459 2460 case OPC_SwitchOpcode: { 2461 unsigned CurNodeOpcode = N.getOpcode(); 2462 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2463 unsigned CaseSize; 2464 while (1) { 2465 // Get the size of this case. 2466 CaseSize = MatcherTable[MatcherIndex++]; 2467 if (CaseSize & 128) 2468 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2469 if (CaseSize == 0) break; 2470 2471 uint16_t Opc = MatcherTable[MatcherIndex++]; 2472 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2473 2474 // If the opcode matches, then we will execute this case. 2475 if (CurNodeOpcode == Opc) 2476 break; 2477 2478 // Otherwise, skip over this case. 2479 MatcherIndex += CaseSize; 2480 } 2481 2482 // If no cases matched, bail out. 2483 if (CaseSize == 0) break; 2484 2485 // Otherwise, execute the case we found. 2486 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2487 << " to " << MatcherIndex << "\n"); 2488 continue; 2489 } 2490 2491 case OPC_SwitchType: { 2492 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2493 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2494 unsigned CaseSize; 2495 while (1) { 2496 // Get the size of this case. 2497 CaseSize = MatcherTable[MatcherIndex++]; 2498 if (CaseSize & 128) 2499 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2500 if (CaseSize == 0) break; 2501 2502 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2503 if (CaseVT == MVT::iPTR) 2504 CaseVT = TLI.getPointerTy(); 2505 2506 // If the VT matches, then we will execute this case. 2507 if (CurNodeVT == CaseVT) 2508 break; 2509 2510 // Otherwise, skip over this case. 2511 MatcherIndex += CaseSize; 2512 } 2513 2514 // If no cases matched, bail out. 2515 if (CaseSize == 0) break; 2516 2517 // Otherwise, execute the case we found. 2518 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2519 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2520 continue; 2521 } 2522 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2523 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2524 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2525 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2526 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2527 Opcode-OPC_CheckChild0Type)) 2528 break; 2529 continue; 2530 case OPC_CheckCondCode: 2531 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2532 continue; 2533 case OPC_CheckValueType: 2534 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2535 continue; 2536 case OPC_CheckInteger: 2537 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2538 continue; 2539 case OPC_CheckAndImm: 2540 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2541 continue; 2542 case OPC_CheckOrImm: 2543 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2544 continue; 2545 2546 case OPC_CheckFoldableChainNode: { 2547 assert(NodeStack.size() != 1 && "No parent node"); 2548 // Verify that all intermediate nodes between the root and this one have 2549 // a single use. 2550 bool HasMultipleUses = false; 2551 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2552 if (!NodeStack[i].hasOneUse()) { 2553 HasMultipleUses = true; 2554 break; 2555 } 2556 if (HasMultipleUses) break; 2557 2558 // Check to see that the target thinks this is profitable to fold and that 2559 // we can fold it without inducing cycles in the graph. 2560 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2561 NodeToMatch) || 2562 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2563 NodeToMatch, OptLevel, 2564 true/*We validate our own chains*/)) 2565 break; 2566 2567 continue; 2568 } 2569 case OPC_EmitInteger: { 2570 MVT::SimpleValueType VT = 2571 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2572 int64_t Val = MatcherTable[MatcherIndex++]; 2573 if (Val & 128) 2574 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2575 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2576 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2577 continue; 2578 } 2579 case OPC_EmitRegister: { 2580 MVT::SimpleValueType VT = 2581 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2582 unsigned RegNo = MatcherTable[MatcherIndex++]; 2583 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2584 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2585 continue; 2586 } 2587 case OPC_EmitRegister2: { 2588 // For targets w/ more than 256 register names, the register enum 2589 // values are stored in two bytes in the matcher table (just like 2590 // opcodes). 2591 MVT::SimpleValueType VT = 2592 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2593 unsigned RegNo = MatcherTable[MatcherIndex++]; 2594 RegNo |= MatcherTable[MatcherIndex++] << 8; 2595 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2596 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2597 continue; 2598 } 2599 2600 case OPC_EmitConvertToTarget: { 2601 // Convert from IMM/FPIMM to target version. 2602 unsigned RecNo = MatcherTable[MatcherIndex++]; 2603 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2604 SDValue Imm = RecordedNodes[RecNo].first; 2605 2606 if (Imm->getOpcode() == ISD::Constant) { 2607 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2608 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2609 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2610 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2611 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2612 } 2613 2614 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2615 continue; 2616 } 2617 2618 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2619 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2620 // These are space-optimized forms of OPC_EmitMergeInputChains. 2621 assert(InputChain.getNode() == 0 && 2622 "EmitMergeInputChains should be the first chain producing node"); 2623 assert(ChainNodesMatched.empty() && 2624 "Should only have one EmitMergeInputChains per match"); 2625 2626 // Read all of the chained nodes. 2627 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2628 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2629 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2630 2631 // FIXME: What if other value results of the node have uses not matched 2632 // by this pattern? 2633 if (ChainNodesMatched.back() != NodeToMatch && 2634 !RecordedNodes[RecNo].first.hasOneUse()) { 2635 ChainNodesMatched.clear(); 2636 break; 2637 } 2638 2639 // Merge the input chains if they are not intra-pattern references. 2640 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2641 2642 if (InputChain.getNode() == 0) 2643 break; // Failed to merge. 2644 continue; 2645 } 2646 2647 case OPC_EmitMergeInputChains: { 2648 assert(InputChain.getNode() == 0 && 2649 "EmitMergeInputChains should be the first chain producing node"); 2650 // This node gets a list of nodes we matched in the input that have 2651 // chains. We want to token factor all of the input chains to these nodes 2652 // together. However, if any of the input chains is actually one of the 2653 // nodes matched in this pattern, then we have an intra-match reference. 2654 // Ignore these because the newly token factored chain should not refer to 2655 // the old nodes. 2656 unsigned NumChains = MatcherTable[MatcherIndex++]; 2657 assert(NumChains != 0 && "Can't TF zero chains"); 2658 2659 assert(ChainNodesMatched.empty() && 2660 "Should only have one EmitMergeInputChains per match"); 2661 2662 // Read all of the chained nodes. 2663 for (unsigned i = 0; i != NumChains; ++i) { 2664 unsigned RecNo = MatcherTable[MatcherIndex++]; 2665 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2666 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2667 2668 // FIXME: What if other value results of the node have uses not matched 2669 // by this pattern? 2670 if (ChainNodesMatched.back() != NodeToMatch && 2671 !RecordedNodes[RecNo].first.hasOneUse()) { 2672 ChainNodesMatched.clear(); 2673 break; 2674 } 2675 } 2676 2677 // If the inner loop broke out, the match fails. 2678 if (ChainNodesMatched.empty()) 2679 break; 2680 2681 // Merge the input chains if they are not intra-pattern references. 2682 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2683 2684 if (InputChain.getNode() == 0) 2685 break; // Failed to merge. 2686 2687 continue; 2688 } 2689 2690 case OPC_EmitCopyToReg: { 2691 unsigned RecNo = MatcherTable[MatcherIndex++]; 2692 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2693 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2694 2695 if (InputChain.getNode() == 0) 2696 InputChain = CurDAG->getEntryNode(); 2697 2698 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2699 DestPhysReg, RecordedNodes[RecNo].first, 2700 InputGlue); 2701 2702 InputGlue = InputChain.getValue(1); 2703 continue; 2704 } 2705 2706 case OPC_EmitNodeXForm: { 2707 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2708 unsigned RecNo = MatcherTable[MatcherIndex++]; 2709 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2710 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2711 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2712 continue; 2713 } 2714 2715 case OPC_EmitNode: 2716 case OPC_MorphNodeTo: { 2717 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2718 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2719 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2720 // Get the result VT list. 2721 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2722 SmallVector<EVT, 4> VTs; 2723 for (unsigned i = 0; i != NumVTs; ++i) { 2724 MVT::SimpleValueType VT = 2725 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2726 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2727 VTs.push_back(VT); 2728 } 2729 2730 if (EmitNodeInfo & OPFL_Chain) 2731 VTs.push_back(MVT::Other); 2732 if (EmitNodeInfo & OPFL_GlueOutput) 2733 VTs.push_back(MVT::Glue); 2734 2735 // This is hot code, so optimize the two most common cases of 1 and 2 2736 // results. 2737 SDVTList VTList; 2738 if (VTs.size() == 1) 2739 VTList = CurDAG->getVTList(VTs[0]); 2740 else if (VTs.size() == 2) 2741 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2742 else 2743 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2744 2745 // Get the operand list. 2746 unsigned NumOps = MatcherTable[MatcherIndex++]; 2747 SmallVector<SDValue, 8> Ops; 2748 for (unsigned i = 0; i != NumOps; ++i) { 2749 unsigned RecNo = MatcherTable[MatcherIndex++]; 2750 if (RecNo & 128) 2751 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2752 2753 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2754 Ops.push_back(RecordedNodes[RecNo].first); 2755 } 2756 2757 // If there are variadic operands to add, handle them now. 2758 if (EmitNodeInfo & OPFL_VariadicInfo) { 2759 // Determine the start index to copy from. 2760 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2761 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2762 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2763 "Invalid variadic node"); 2764 // Copy all of the variadic operands, not including a potential glue 2765 // input. 2766 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2767 i != e; ++i) { 2768 SDValue V = NodeToMatch->getOperand(i); 2769 if (V.getValueType() == MVT::Glue) break; 2770 Ops.push_back(V); 2771 } 2772 } 2773 2774 // If this has chain/glue inputs, add them. 2775 if (EmitNodeInfo & OPFL_Chain) 2776 Ops.push_back(InputChain); 2777 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2778 Ops.push_back(InputGlue); 2779 2780 // Create the node. 2781 SDNode *Res = 0; 2782 if (Opcode != OPC_MorphNodeTo) { 2783 // If this is a normal EmitNode command, just create the new node and 2784 // add the results to the RecordedNodes list. 2785 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2786 VTList, Ops.data(), Ops.size()); 2787 2788 // Add all the non-glue/non-chain results to the RecordedNodes list. 2789 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2790 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2791 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2792 (SDNode*) 0)); 2793 } 2794 2795 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2796 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2797 EmitNodeInfo); 2798 } else { 2799 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2800 // We will visit the equivalent node later. 2801 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2802 return 0; 2803 } 2804 2805 // If the node had chain/glue results, update our notion of the current 2806 // chain and glue. 2807 if (EmitNodeInfo & OPFL_GlueOutput) { 2808 InputGlue = SDValue(Res, VTs.size()-1); 2809 if (EmitNodeInfo & OPFL_Chain) 2810 InputChain = SDValue(Res, VTs.size()-2); 2811 } else if (EmitNodeInfo & OPFL_Chain) 2812 InputChain = SDValue(Res, VTs.size()-1); 2813 2814 // If the OPFL_MemRefs glue is set on this node, slap all of the 2815 // accumulated memrefs onto it. 2816 // 2817 // FIXME: This is vastly incorrect for patterns with multiple outputs 2818 // instructions that access memory and for ComplexPatterns that match 2819 // loads. 2820 if (EmitNodeInfo & OPFL_MemRefs) { 2821 // Only attach load or store memory operands if the generated 2822 // instruction may load or store. 2823 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2824 bool mayLoad = MCID.mayLoad(); 2825 bool mayStore = MCID.mayStore(); 2826 2827 unsigned NumMemRefs = 0; 2828 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2829 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2830 if ((*I)->isLoad()) { 2831 if (mayLoad) 2832 ++NumMemRefs; 2833 } else if ((*I)->isStore()) { 2834 if (mayStore) 2835 ++NumMemRefs; 2836 } else { 2837 ++NumMemRefs; 2838 } 2839 } 2840 2841 MachineSDNode::mmo_iterator MemRefs = 2842 MF->allocateMemRefsArray(NumMemRefs); 2843 2844 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2845 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2846 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2847 if ((*I)->isLoad()) { 2848 if (mayLoad) 2849 *MemRefsPos++ = *I; 2850 } else if ((*I)->isStore()) { 2851 if (mayStore) 2852 *MemRefsPos++ = *I; 2853 } else { 2854 *MemRefsPos++ = *I; 2855 } 2856 } 2857 2858 cast<MachineSDNode>(Res) 2859 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2860 } 2861 2862 DEBUG(errs() << " " 2863 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2864 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2865 2866 // If this was a MorphNodeTo then we're completely done! 2867 if (Opcode == OPC_MorphNodeTo) { 2868 // Update chain and glue uses. 2869 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2870 InputGlue, GlueResultNodesMatched, true); 2871 return Res; 2872 } 2873 2874 continue; 2875 } 2876 2877 case OPC_MarkGlueResults: { 2878 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2879 2880 // Read and remember all the glue-result nodes. 2881 for (unsigned i = 0; i != NumNodes; ++i) { 2882 unsigned RecNo = MatcherTable[MatcherIndex++]; 2883 if (RecNo & 128) 2884 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2885 2886 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2887 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2888 } 2889 continue; 2890 } 2891 2892 case OPC_CompleteMatch: { 2893 // The match has been completed, and any new nodes (if any) have been 2894 // created. Patch up references to the matched dag to use the newly 2895 // created nodes. 2896 unsigned NumResults = MatcherTable[MatcherIndex++]; 2897 2898 for (unsigned i = 0; i != NumResults; ++i) { 2899 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2900 if (ResSlot & 128) 2901 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2902 2903 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2904 SDValue Res = RecordedNodes[ResSlot].first; 2905 2906 assert(i < NodeToMatch->getNumValues() && 2907 NodeToMatch->getValueType(i) != MVT::Other && 2908 NodeToMatch->getValueType(i) != MVT::Glue && 2909 "Invalid number of results to complete!"); 2910 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2911 NodeToMatch->getValueType(i) == MVT::iPTR || 2912 Res.getValueType() == MVT::iPTR || 2913 NodeToMatch->getValueType(i).getSizeInBits() == 2914 Res.getValueType().getSizeInBits()) && 2915 "invalid replacement"); 2916 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2917 } 2918 2919 // If the root node defines glue, add it to the glue nodes to update list. 2920 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2921 GlueResultNodesMatched.push_back(NodeToMatch); 2922 2923 // Update chain and glue uses. 2924 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2925 InputGlue, GlueResultNodesMatched, false); 2926 2927 assert(NodeToMatch->use_empty() && 2928 "Didn't replace all uses of the node?"); 2929 2930 // FIXME: We just return here, which interacts correctly with SelectRoot 2931 // above. We should fix this to not return an SDNode* anymore. 2932 return 0; 2933 } 2934 } 2935 2936 // If the code reached this point, then the match failed. See if there is 2937 // another child to try in the current 'Scope', otherwise pop it until we 2938 // find a case to check. 2939 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2940 ++NumDAGIselRetries; 2941 while (1) { 2942 if (MatchScopes.empty()) { 2943 CannotYetSelect(NodeToMatch); 2944 return 0; 2945 } 2946 2947 // Restore the interpreter state back to the point where the scope was 2948 // formed. 2949 MatchScope &LastScope = MatchScopes.back(); 2950 RecordedNodes.resize(LastScope.NumRecordedNodes); 2951 NodeStack.clear(); 2952 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2953 N = NodeStack.back(); 2954 2955 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2956 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2957 MatcherIndex = LastScope.FailIndex; 2958 2959 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2960 2961 InputChain = LastScope.InputChain; 2962 InputGlue = LastScope.InputGlue; 2963 if (!LastScope.HasChainNodesMatched) 2964 ChainNodesMatched.clear(); 2965 if (!LastScope.HasGlueResultNodesMatched) 2966 GlueResultNodesMatched.clear(); 2967 2968 // Check to see what the offset is at the new MatcherIndex. If it is zero 2969 // we have reached the end of this scope, otherwise we have another child 2970 // in the current scope to try. 2971 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2972 if (NumToSkip & 128) 2973 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2974 2975 // If we have another child in this scope to match, update FailIndex and 2976 // try it. 2977 if (NumToSkip != 0) { 2978 LastScope.FailIndex = MatcherIndex+NumToSkip; 2979 break; 2980 } 2981 2982 // End of this scope, pop it and try the next child in the containing 2983 // scope. 2984 MatchScopes.pop_back(); 2985 } 2986 } 2987 } 2988 2989 2990 2991 void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2992 std::string msg; 2993 raw_string_ostream Msg(msg); 2994 Msg << "Cannot select: "; 2995 2996 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2997 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2998 N->getOpcode() != ISD::INTRINSIC_VOID) { 2999 N->printrFull(Msg, CurDAG); 3000 Msg << "\nIn function: " << MF->getName(); 3001 } else { 3002 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3003 unsigned iid = 3004 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3005 if (iid < Intrinsic::num_intrinsics) 3006 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3007 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3008 Msg << "target intrinsic %" << TII->getName(iid); 3009 else 3010 Msg << "unknown intrinsic #" << iid; 3011 } 3012 report_fatal_error(Msg.str()); 3013 } 3014 3015 char SelectionDAGISel::ID = 0; 3016