1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the X86 specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef X86SUBTARGET_H 15 #define X86SUBTARGET_H 16 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/IR/CallingConv.h" 19 #include "llvm/Target/TargetSubtargetInfo.h" 20 #include <string> 21 22 #define GET_SUBTARGETINFO_HEADER 23 #include "X86GenSubtargetInfo.inc" 24 25 namespace llvm { 26 class GlobalValue; 27 class StringRef; 28 class TargetMachine; 29 30 /// PICStyles - The X86 backend supports a number of different styles of PIC. 31 /// 32 namespace PICStyles { 33 enum Style { 34 StubPIC, // Used on i386-darwin in -fPIC mode. 35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode. 36 GOT, // Used on many 32-bit unices in -fPIC mode. 37 RIPRel, // Used on X86-64 when not in -static mode. 38 None // Set when in -static mode (not PIC or DynamicNoPIC mode). 39 }; 40 } 41 42 class X86Subtarget : public X86GenSubtargetInfo { 43 protected: 44 enum X86SSEEnum { 45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 46 }; 47 48 enum X863DNowEnum { 49 NoThreeDNow, ThreeDNow, ThreeDNowA 50 }; 51 52 enum X86ProcFamilyEnum { 53 Others, IntelAtom 54 }; 55 56 /// X86ProcFamily - X86 processor family: Intel Atom, and others 57 X86ProcFamilyEnum X86ProcFamily; 58 59 /// PICStyle - Which PIC style to use 60 /// 61 PICStyles::Style PICStyle; 62 63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or 64 /// none supported. 65 X86SSEEnum X86SSELevel; 66 67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported. 68 /// 69 X863DNowEnum X863DNowLevel; 70 71 /// HasCMov - True if this processor has conditional move instructions 72 /// (generally pentium pro+). 73 bool HasCMov; 74 75 /// HasX86_64 - True if the processor supports X86-64 instructions. 76 /// 77 bool HasX86_64; 78 79 /// HasPOPCNT - True if the processor supports POPCNT. 80 bool HasPOPCNT; 81 82 /// HasSSE4A - True if the processor supports SSE4A instructions. 83 bool HasSSE4A; 84 85 /// HasAES - Target has AES instructions 86 bool HasAES; 87 88 /// HasPCLMUL - Target has carry-less multiplication 89 bool HasPCLMUL; 90 91 /// HasFMA - Target has 3-operand fused multiply-add 92 bool HasFMA; 93 94 /// HasFMA4 - Target has 4-operand fused multiply-add 95 bool HasFMA4; 96 97 /// HasXOP - Target has XOP instructions 98 bool HasXOP; 99 100 /// HasMOVBE - True if the processor has the MOVBE instruction. 101 bool HasMOVBE; 102 103 /// HasRDRAND - True if the processor has the RDRAND instruction. 104 bool HasRDRAND; 105 106 /// HasF16C - Processor has 16-bit floating point conversion instructions. 107 bool HasF16C; 108 109 /// HasFSGSBase - Processor has FS/GS base insturctions. 110 bool HasFSGSBase; 111 112 /// HasLZCNT - Processor has LZCNT instruction. 113 bool HasLZCNT; 114 115 /// HasBMI - Processor has BMI1 instructions. 116 bool HasBMI; 117 118 /// HasBMI2 - Processor has BMI2 instructions. 119 bool HasBMI2; 120 121 /// HasRTM - Processor has RTM instructions. 122 bool HasRTM; 123 124 /// HasADX - Processor has ADX instructions. 125 bool HasADX; 126 127 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. 128 bool IsBTMemSlow; 129 130 /// IsUAMemFast - True if unaligned memory access is fast. 131 bool IsUAMemFast; 132 133 /// HasVectorUAMem - True if SIMD operations can have unaligned memory 134 /// operands. This may require setting a feature bit in the processor. 135 bool HasVectorUAMem; 136 137 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction; 138 /// this is true for most x86-64 chips, but not the first AMD chips. 139 bool HasCmpxchg16b; 140 141 /// UseLeaForSP - True if the LEA instruction should be used for adjusting 142 /// the stack pointer. This is an optimization for Intel Atom processors. 143 bool UseLeaForSP; 144 145 /// HasSlowDivide - True if smaller divides are significantly faster than 146 /// full divides and should be used when possible. 147 bool HasSlowDivide; 148 149 /// PostRAScheduler - True if using post-register-allocation scheduler. 150 bool PostRAScheduler; 151 152 /// PadShortFunctions - True if the short functions should be padded to prevent 153 /// a stall when returning too early. 154 bool PadShortFunctions; 155 156 /// stackAlignment - The minimum alignment known to hold of the stack frame on 157 /// entry to the function and which must be maintained by every function. 158 unsigned stackAlignment; 159 160 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. 161 /// 162 unsigned MaxInlineSizeThreshold; 163 164 /// TargetTriple - What processor and OS we're targeting. 165 Triple TargetTriple; 166 167 /// Instruction itineraries for scheduling 168 InstrItineraryData InstrItins; 169 170 private: 171 /// StackAlignOverride - Override the stack alignment. 172 unsigned StackAlignOverride; 173 174 /// In64BitMode - True if compiling for 64-bit, false for 32-bit. 175 bool In64BitMode; 176 177 public: 178 /// This constructor initializes the data members to match that 179 /// of the specified triple. 180 /// 181 X86Subtarget(const std::string &TT, const std::string &CPU, 182 const std::string &FS, 183 unsigned StackAlignOverride, bool is64Bit); 184 185 /// getStackAlignment - Returns the minimum alignment known to hold of the 186 /// stack frame on entry to the function and which must be maintained by every 187 /// function for this subtarget. 188 unsigned getStackAlignment() const { return stackAlignment; } 189 190 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 191 /// that still makes it profitable to inline the call. 192 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } 193 194 /// ParseSubtargetFeatures - Parses features string setting specified 195 /// subtarget options. Definition of function is auto generated by tblgen. 196 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 197 198 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID 199 /// instruction. 200 void AutoDetectSubtargetFeatures(); 201 202 /// \brief Reset the features for the X86 target. 203 virtual void resetSubtargetFeatures(const MachineFunction *MF); 204 private: 205 void initializeEnvironment(); 206 void resetSubtargetFeatures(StringRef CPU, StringRef FS); 207 public: 208 /// Is this x86_64? (disregarding specific ABI / programming model) 209 bool is64Bit() const { 210 return In64BitMode; 211 } 212 213 /// Is this x86_64 with the ILP32 programming model (x32 ABI)? 214 bool isTarget64BitILP32() const { 215 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32); 216 } 217 218 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? 219 bool isTarget64BitLP64() const { 220 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32); 221 } 222 223 PICStyles::Style getPICStyle() const { return PICStyle; } 224 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } 225 226 bool hasCMov() const { return HasCMov; } 227 bool hasMMX() const { return X86SSELevel >= MMX; } 228 bool hasSSE1() const { return X86SSELevel >= SSE1; } 229 bool hasSSE2() const { return X86SSELevel >= SSE2; } 230 bool hasSSE3() const { return X86SSELevel >= SSE3; } 231 bool hasSSSE3() const { return X86SSELevel >= SSSE3; } 232 bool hasSSE41() const { return X86SSELevel >= SSE41; } 233 bool hasSSE42() const { return X86SSELevel >= SSE42; } 234 bool hasAVX() const { return X86SSELevel >= AVX; } 235 bool hasAVX2() const { return X86SSELevel >= AVX2; } 236 bool hasFp256() const { return hasAVX(); } 237 bool hasInt256() const { return hasAVX2(); } 238 bool hasSSE4A() const { return HasSSE4A; } 239 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } 240 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } 241 bool hasPOPCNT() const { return HasPOPCNT; } 242 bool hasAES() const { return HasAES; } 243 bool hasPCLMUL() const { return HasPCLMUL; } 244 bool hasFMA() const { return HasFMA; } 245 // FIXME: Favor FMA when both are enabled. Is this the right thing to do? 246 bool hasFMA4() const { return HasFMA4 && !HasFMA; } 247 bool hasXOP() const { return HasXOP; } 248 bool hasMOVBE() const { return HasMOVBE; } 249 bool hasRDRAND() const { return HasRDRAND; } 250 bool hasF16C() const { return HasF16C; } 251 bool hasFSGSBase() const { return HasFSGSBase; } 252 bool hasLZCNT() const { return HasLZCNT; } 253 bool hasBMI() const { return HasBMI; } 254 bool hasBMI2() const { return HasBMI2; } 255 bool hasRTM() const { return HasRTM; } 256 bool hasADX() const { return HasADX; } 257 bool isBTMemSlow() const { return IsBTMemSlow; } 258 bool isUnalignedMemAccessFast() const { return IsUAMemFast; } 259 bool hasVectorUAMem() const { return HasVectorUAMem; } 260 bool hasCmpxchg16b() const { return HasCmpxchg16b; } 261 bool useLeaForSP() const { return UseLeaForSP; } 262 bool hasSlowDivide() const { return HasSlowDivide; } 263 bool padShortFunctions() const { return PadShortFunctions; } 264 265 bool isAtom() const { return X86ProcFamily == IntelAtom; } 266 267 const Triple &getTargetTriple() const { return TargetTriple; } 268 269 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 270 bool isTargetFreeBSD() const { 271 return TargetTriple.getOS() == Triple::FreeBSD; 272 } 273 bool isTargetSolaris() const { 274 return TargetTriple.getOS() == Triple::Solaris; 275 } 276 bool isTargetELF() const { 277 return (TargetTriple.getEnvironment() == Triple::ELF || 278 TargetTriple.isOSBinFormatELF()); 279 } 280 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; } 281 bool isTargetNaCl() const { 282 return TargetTriple.getOS() == Triple::NaCl; 283 } 284 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } 285 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } 286 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; } 287 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; } 288 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; } 289 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } 290 bool isTargetCOFF() const { 291 return (TargetTriple.getEnvironment() != Triple::ELF && 292 TargetTriple.isOSBinFormatCOFF()); 293 } 294 bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); } 295 296 bool isTargetWin64() const { 297 // FIXME: x86_64-cygwin has not been released yet. 298 return In64BitMode && TargetTriple.isOSWindows(); 299 } 300 301 bool isTargetWin32() const { 302 // FIXME: Cygwin is included for isTargetWin64 -- should it be included 303 // here too? 304 return !In64BitMode && (isTargetMingw() || isTargetWindows()); 305 } 306 307 bool isPICStyleSet() const { return PICStyle != PICStyles::None; } 308 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; } 309 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; } 310 311 bool isPICStyleStubPIC() const { 312 return PICStyle == PICStyles::StubPIC; 313 } 314 315 bool isPICStyleStubNoDynamic() const { 316 return PICStyle == PICStyles::StubDynamicNoPIC; 317 } 318 bool isPICStyleStubAny() const { 319 return PICStyle == PICStyles::StubDynamicNoPIC || 320 PICStyle == PICStyles::StubPIC; } 321 322 /// ClassifyGlobalReference - Classify a global variable reference for the 323 /// current subtarget according to how we should reference it in a non-pcrel 324 /// context. 325 unsigned char ClassifyGlobalReference(const GlobalValue *GV, 326 const TargetMachine &TM)const; 327 328 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the 329 /// current subtarget according to how we should reference it in a non-pcrel 330 /// context. 331 unsigned char ClassifyBlockAddressReference() const; 332 333 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls 334 /// to immediate address. 335 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const; 336 337 /// This function returns the name of a function which has an interface 338 /// like the non-standard bzero function, if such a function exists on 339 /// the current subtarget and it is considered prefereable over 340 /// memset with zero passed as the second argument. Otherwise it 341 /// returns null. 342 const char *getBZeroEntry() const; 343 344 /// This function returns true if the target has sincos() routine in its 345 /// compiler runtime or math libraries. 346 bool hasSinCos() const; 347 348 /// enablePostRAScheduler - run for Atom optimization. 349 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 350 TargetSubtargetInfo::AntiDepBreakMode& Mode, 351 RegClassVector& CriticalPathRCs) const; 352 353 bool postRAScheduler() const { return PostRAScheduler; } 354 355 /// getInstrItins = Return the instruction itineraries based on the 356 /// subtarget selection. 357 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 358 }; 359 360 } // End llvm namespace 361 362 #endif 363
