1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstrInfo.h" 15 #include "X86.h" 16 #include "X86InstrBuilder.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/CodeGen/LiveVariables.h" 22 #include "llvm/CodeGen/MachineConstantPool.h" 23 #include "llvm/CodeGen/MachineDominators.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/IR/DerivedTypes.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/MC/MCAsmInfo.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetOptions.h" 36 #include <limits> 37 38 #define GET_INSTRINFO_CTOR 39 #include "X86GenInstrInfo.inc" 40 41 using namespace llvm; 42 43 static cl::opt<bool> 44 NoFusing("disable-spill-fusing", 45 cl::desc("Disable fusing of spill code into instructions")); 46 static cl::opt<bool> 47 PrintFailedFusing("print-failed-fuse-candidates", 48 cl::desc("Print instructions that the allocator wants to" 49 " fuse, but the X86 backend currently can't"), 50 cl::Hidden); 51 static cl::opt<bool> 52 ReMatPICStubLoad("remat-pic-stub-load", 53 cl::desc("Re-materialize load from stub in PIC mode"), 54 cl::init(false), cl::Hidden); 55 56 enum { 57 // Select which memory operand is being unfolded. 58 // (stored in bits 0 - 3) 59 TB_INDEX_0 = 0, 60 TB_INDEX_1 = 1, 61 TB_INDEX_2 = 2, 62 TB_INDEX_3 = 3, 63 TB_INDEX_MASK = 0xf, 64 65 // Do not insert the reverse map (MemOp -> RegOp) into the table. 66 // This may be needed because there is a many -> one mapping. 67 TB_NO_REVERSE = 1 << 4, 68 69 // Do not insert the forward map (RegOp -> MemOp) into the table. 70 // This is needed for Native Client, which prohibits branch 71 // instructions from using a memory operand. 72 TB_NO_FORWARD = 1 << 5, 73 74 TB_FOLDED_LOAD = 1 << 6, 75 TB_FOLDED_STORE = 1 << 7, 76 77 // Minimum alignment required for load/store. 78 // Used for RegOp->MemOp conversion. 79 // (stored in bits 8 - 15) 80 TB_ALIGN_SHIFT = 8, 81 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 82 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 83 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 84 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 85 }; 86 87 struct X86OpTblEntry { 88 uint16_t RegOp; 89 uint16_t MemOp; 90 uint16_t Flags; 91 }; 92 93 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 94 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() 95 ? X86::ADJCALLSTACKDOWN64 96 : X86::ADJCALLSTACKDOWN32), 97 (tm.getSubtarget<X86Subtarget>().is64Bit() 98 ? X86::ADJCALLSTACKUP64 99 : X86::ADJCALLSTACKUP32)), 100 TM(tm), RI(tm, *this) { 101 102 static const X86OpTblEntry OpTbl2Addr[] = { 103 { X86::ADC32ri, X86::ADC32mi, 0 }, 104 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 105 { X86::ADC32rr, X86::ADC32mr, 0 }, 106 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 107 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 108 { X86::ADC64rr, X86::ADC64mr, 0 }, 109 { X86::ADD16ri, X86::ADD16mi, 0 }, 110 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 111 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 112 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 113 { X86::ADD16rr, X86::ADD16mr, 0 }, 114 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 115 { X86::ADD32ri, X86::ADD32mi, 0 }, 116 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 117 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 118 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 119 { X86::ADD32rr, X86::ADD32mr, 0 }, 120 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 121 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 122 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 123 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 124 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 125 { X86::ADD64rr, X86::ADD64mr, 0 }, 126 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 127 { X86::ADD8ri, X86::ADD8mi, 0 }, 128 { X86::ADD8rr, X86::ADD8mr, 0 }, 129 { X86::AND16ri, X86::AND16mi, 0 }, 130 { X86::AND16ri8, X86::AND16mi8, 0 }, 131 { X86::AND16rr, X86::AND16mr, 0 }, 132 { X86::AND32ri, X86::AND32mi, 0 }, 133 { X86::AND32ri8, X86::AND32mi8, 0 }, 134 { X86::AND32rr, X86::AND32mr, 0 }, 135 { X86::AND64ri32, X86::AND64mi32, 0 }, 136 { X86::AND64ri8, X86::AND64mi8, 0 }, 137 { X86::AND64rr, X86::AND64mr, 0 }, 138 { X86::AND8ri, X86::AND8mi, 0 }, 139 { X86::AND8rr, X86::AND8mr, 0 }, 140 { X86::DEC16r, X86::DEC16m, 0 }, 141 { X86::DEC32r, X86::DEC32m, 0 }, 142 { X86::DEC64_16r, X86::DEC64_16m, 0 }, 143 { X86::DEC64_32r, X86::DEC64_32m, 0 }, 144 { X86::DEC64r, X86::DEC64m, 0 }, 145 { X86::DEC8r, X86::DEC8m, 0 }, 146 { X86::INC16r, X86::INC16m, 0 }, 147 { X86::INC32r, X86::INC32m, 0 }, 148 { X86::INC64_16r, X86::INC64_16m, 0 }, 149 { X86::INC64_32r, X86::INC64_32m, 0 }, 150 { X86::INC64r, X86::INC64m, 0 }, 151 { X86::INC8r, X86::INC8m, 0 }, 152 { X86::NEG16r, X86::NEG16m, 0 }, 153 { X86::NEG32r, X86::NEG32m, 0 }, 154 { X86::NEG64r, X86::NEG64m, 0 }, 155 { X86::NEG8r, X86::NEG8m, 0 }, 156 { X86::NOT16r, X86::NOT16m, 0 }, 157 { X86::NOT32r, X86::NOT32m, 0 }, 158 { X86::NOT64r, X86::NOT64m, 0 }, 159 { X86::NOT8r, X86::NOT8m, 0 }, 160 { X86::OR16ri, X86::OR16mi, 0 }, 161 { X86::OR16ri8, X86::OR16mi8, 0 }, 162 { X86::OR16rr, X86::OR16mr, 0 }, 163 { X86::OR32ri, X86::OR32mi, 0 }, 164 { X86::OR32ri8, X86::OR32mi8, 0 }, 165 { X86::OR32rr, X86::OR32mr, 0 }, 166 { X86::OR64ri32, X86::OR64mi32, 0 }, 167 { X86::OR64ri8, X86::OR64mi8, 0 }, 168 { X86::OR64rr, X86::OR64mr, 0 }, 169 { X86::OR8ri, X86::OR8mi, 0 }, 170 { X86::OR8rr, X86::OR8mr, 0 }, 171 { X86::ROL16r1, X86::ROL16m1, 0 }, 172 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 173 { X86::ROL16ri, X86::ROL16mi, 0 }, 174 { X86::ROL32r1, X86::ROL32m1, 0 }, 175 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 176 { X86::ROL32ri, X86::ROL32mi, 0 }, 177 { X86::ROL64r1, X86::ROL64m1, 0 }, 178 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 179 { X86::ROL64ri, X86::ROL64mi, 0 }, 180 { X86::ROL8r1, X86::ROL8m1, 0 }, 181 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 182 { X86::ROL8ri, X86::ROL8mi, 0 }, 183 { X86::ROR16r1, X86::ROR16m1, 0 }, 184 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 185 { X86::ROR16ri, X86::ROR16mi, 0 }, 186 { X86::ROR32r1, X86::ROR32m1, 0 }, 187 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 188 { X86::ROR32ri, X86::ROR32mi, 0 }, 189 { X86::ROR64r1, X86::ROR64m1, 0 }, 190 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 191 { X86::ROR64ri, X86::ROR64mi, 0 }, 192 { X86::ROR8r1, X86::ROR8m1, 0 }, 193 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 194 { X86::ROR8ri, X86::ROR8mi, 0 }, 195 { X86::SAR16r1, X86::SAR16m1, 0 }, 196 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 197 { X86::SAR16ri, X86::SAR16mi, 0 }, 198 { X86::SAR32r1, X86::SAR32m1, 0 }, 199 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 200 { X86::SAR32ri, X86::SAR32mi, 0 }, 201 { X86::SAR64r1, X86::SAR64m1, 0 }, 202 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 203 { X86::SAR64ri, X86::SAR64mi, 0 }, 204 { X86::SAR8r1, X86::SAR8m1, 0 }, 205 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 206 { X86::SAR8ri, X86::SAR8mi, 0 }, 207 { X86::SBB32ri, X86::SBB32mi, 0 }, 208 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 209 { X86::SBB32rr, X86::SBB32mr, 0 }, 210 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 211 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 212 { X86::SBB64rr, X86::SBB64mr, 0 }, 213 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 214 { X86::SHL16ri, X86::SHL16mi, 0 }, 215 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 216 { X86::SHL32ri, X86::SHL32mi, 0 }, 217 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 218 { X86::SHL64ri, X86::SHL64mi, 0 }, 219 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 220 { X86::SHL8ri, X86::SHL8mi, 0 }, 221 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 222 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 223 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 224 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 225 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 226 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 227 { X86::SHR16r1, X86::SHR16m1, 0 }, 228 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 229 { X86::SHR16ri, X86::SHR16mi, 0 }, 230 { X86::SHR32r1, X86::SHR32m1, 0 }, 231 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 232 { X86::SHR32ri, X86::SHR32mi, 0 }, 233 { X86::SHR64r1, X86::SHR64m1, 0 }, 234 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 235 { X86::SHR64ri, X86::SHR64mi, 0 }, 236 { X86::SHR8r1, X86::SHR8m1, 0 }, 237 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 238 { X86::SHR8ri, X86::SHR8mi, 0 }, 239 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 240 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 241 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 242 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 243 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 244 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 245 { X86::SUB16ri, X86::SUB16mi, 0 }, 246 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 247 { X86::SUB16rr, X86::SUB16mr, 0 }, 248 { X86::SUB32ri, X86::SUB32mi, 0 }, 249 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 250 { X86::SUB32rr, X86::SUB32mr, 0 }, 251 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 252 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 253 { X86::SUB64rr, X86::SUB64mr, 0 }, 254 { X86::SUB8ri, X86::SUB8mi, 0 }, 255 { X86::SUB8rr, X86::SUB8mr, 0 }, 256 { X86::XOR16ri, X86::XOR16mi, 0 }, 257 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 258 { X86::XOR16rr, X86::XOR16mr, 0 }, 259 { X86::XOR32ri, X86::XOR32mi, 0 }, 260 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 261 { X86::XOR32rr, X86::XOR32mr, 0 }, 262 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 263 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 264 { X86::XOR64rr, X86::XOR64mr, 0 }, 265 { X86::XOR8ri, X86::XOR8mi, 0 }, 266 { X86::XOR8rr, X86::XOR8mr, 0 } 267 }; 268 269 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 270 unsigned RegOp = OpTbl2Addr[i].RegOp; 271 unsigned MemOp = OpTbl2Addr[i].MemOp; 272 unsigned Flags = OpTbl2Addr[i].Flags; 273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 274 RegOp, MemOp, 275 // Index 0, folded load and store, no alignment requirement. 276 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 277 } 278 279 static const X86OpTblEntry OpTbl0[] = { 280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE }, 301 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 302 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 335 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 336 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 337 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 338 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 339 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 340 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 341 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 342 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 343 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 344 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 345 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 346 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 347 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 348 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 349 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 350 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 351 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 352 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 353 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 354 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 355 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 356 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 357 // AVX 128-bit versions of foldable instructions 358 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, 359 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 360 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 361 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 362 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 365 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 366 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 367 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 368 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 369 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 370 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 371 // AVX 256-bit foldable instructions 372 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 373 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 374 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 376 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 377 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE } 378 }; 379 380 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 381 unsigned RegOp = OpTbl0[i].RegOp; 382 unsigned MemOp = OpTbl0[i].MemOp; 383 unsigned Flags = OpTbl0[i].Flags; 384 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 385 RegOp, MemOp, TB_INDEX_0 | Flags); 386 } 387 388 static const X86OpTblEntry OpTbl1[] = { 389 { X86::CMP16rr, X86::CMP16rm, 0 }, 390 { X86::CMP32rr, X86::CMP32rm, 0 }, 391 { X86::CMP64rr, X86::CMP64rm, 0 }, 392 { X86::CMP8rr, X86::CMP8rm, 0 }, 393 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 394 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 395 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 396 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 397 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 398 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 399 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 400 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 401 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 402 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 403 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE }, 404 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE }, 405 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 406 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 407 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 408 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 409 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 410 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 411 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 412 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 413 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 414 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 415 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 416 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 417 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 418 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 419 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 420 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 421 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 422 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 423 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 424 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 425 { X86::MOV16rr, X86::MOV16rm, 0 }, 426 { X86::MOV32rr, X86::MOV32rm, 0 }, 427 { X86::MOV64rr, X86::MOV64rm, 0 }, 428 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 429 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 430 { X86::MOV8rr, X86::MOV8rm, 0 }, 431 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 432 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 433 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 434 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 435 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 436 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 437 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 438 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 439 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 440 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 441 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 442 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 443 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 444 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 445 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 446 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 447 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 448 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 449 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 450 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 451 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 452 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 453 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 454 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 455 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 456 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 457 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 458 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 459 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 460 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 461 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 462 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 463 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 464 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 465 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 466 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 467 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 468 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 469 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 470 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 471 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 472 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 473 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 474 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 475 { X86::TEST16rr, X86::TEST16rm, 0 }, 476 { X86::TEST32rr, X86::TEST32rm, 0 }, 477 { X86::TEST64rr, X86::TEST64rm, 0 }, 478 { X86::TEST8rr, X86::TEST8rm, 0 }, 479 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 480 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 481 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 482 // AVX 128-bit versions of foldable instructions 483 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 484 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 485 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 486 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 487 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 488 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 489 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 490 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 491 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 492 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 493 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 494 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 495 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 496 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 497 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 498 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 499 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE }, 500 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE }, 501 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 502 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 503 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 504 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 505 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 506 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 507 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 508 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 509 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 510 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 511 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 }, 512 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 513 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 }, 514 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 515 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 516 { X86::VPABSBrr128, X86::VPABSBrm128, 0 }, 517 { X86::VPABSDrr128, X86::VPABSDrm128, 0 }, 518 { X86::VPABSWrr128, X86::VPABSWrm128, 0 }, 519 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 }, 520 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 }, 521 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 }, 522 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 }, 523 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 }, 524 { X86::VRCPPSr, X86::VRCPPSm, 0 }, 525 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 }, 526 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, 527 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 }, 528 { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, 529 { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, 530 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 531 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 532 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 533 534 // AVX 256-bit foldable instructions 535 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 536 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 537 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 538 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 539 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 540 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 }, 541 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 }, 542 543 // AVX2 foldable instructions 544 { X86::VPABSBrr256, X86::VPABSBrm256, 0 }, 545 { X86::VPABSDrr256, X86::VPABSDrm256, 0 }, 546 { X86::VPABSWrr256, X86::VPABSWrm256, 0 }, 547 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 }, 548 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 }, 549 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 }, 550 { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, 551 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 }, 552 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, 553 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, 554 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, 555 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 556 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 557 558 // BMI/BMI2/LZCNT/POPCNT foldable instructions 559 { X86::BEXTR32rr, X86::BEXTR32rm, 0 }, 560 { X86::BEXTR64rr, X86::BEXTR64rm, 0 }, 561 { X86::BLSI32rr, X86::BLSI32rm, 0 }, 562 { X86::BLSI64rr, X86::BLSI64rm, 0 }, 563 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 }, 564 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 }, 565 { X86::BLSR32rr, X86::BLSR32rm, 0 }, 566 { X86::BLSR64rr, X86::BLSR64rm, 0 }, 567 { X86::BZHI32rr, X86::BZHI32rm, 0 }, 568 { X86::BZHI64rr, X86::BZHI64rm, 0 }, 569 { X86::LZCNT16rr, X86::LZCNT16rm, 0 }, 570 { X86::LZCNT32rr, X86::LZCNT32rm, 0 }, 571 { X86::LZCNT64rr, X86::LZCNT64rm, 0 }, 572 { X86::POPCNT16rr, X86::POPCNT16rm, 0 }, 573 { X86::POPCNT32rr, X86::POPCNT32rm, 0 }, 574 { X86::POPCNT64rr, X86::POPCNT64rm, 0 }, 575 { X86::RORX32ri, X86::RORX32mi, 0 }, 576 { X86::RORX64ri, X86::RORX64mi, 0 }, 577 { X86::SARX32rr, X86::SARX32rm, 0 }, 578 { X86::SARX64rr, X86::SARX64rm, 0 }, 579 { X86::SHRX32rr, X86::SHRX32rm, 0 }, 580 { X86::SHRX64rr, X86::SHRX64rm, 0 }, 581 { X86::SHLX32rr, X86::SHLX32rm, 0 }, 582 { X86::SHLX64rr, X86::SHLX64rm, 0 }, 583 { X86::TZCNT16rr, X86::TZCNT16rm, 0 }, 584 { X86::TZCNT32rr, X86::TZCNT32rm, 0 }, 585 { X86::TZCNT64rr, X86::TZCNT64rm, 0 }, 586 }; 587 588 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 589 unsigned RegOp = OpTbl1[i].RegOp; 590 unsigned MemOp = OpTbl1[i].MemOp; 591 unsigned Flags = OpTbl1[i].Flags; 592 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 593 RegOp, MemOp, 594 // Index 1, folded load 595 Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 596 } 597 598 static const X86OpTblEntry OpTbl2[] = { 599 { X86::ADC32rr, X86::ADC32rm, 0 }, 600 { X86::ADC64rr, X86::ADC64rm, 0 }, 601 { X86::ADD16rr, X86::ADD16rm, 0 }, 602 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 603 { X86::ADD32rr, X86::ADD32rm, 0 }, 604 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 605 { X86::ADD64rr, X86::ADD64rm, 0 }, 606 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 607 { X86::ADD8rr, X86::ADD8rm, 0 }, 608 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 609 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 610 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 611 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 612 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 613 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 614 { X86::AND16rr, X86::AND16rm, 0 }, 615 { X86::AND32rr, X86::AND32rm, 0 }, 616 { X86::AND64rr, X86::AND64rm, 0 }, 617 { X86::AND8rr, X86::AND8rm, 0 }, 618 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 619 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 620 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 621 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 622 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 623 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 624 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 625 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 626 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 627 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 628 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 629 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 630 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 631 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 632 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 633 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 634 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 635 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 636 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 637 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 638 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 639 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 640 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 641 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 642 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 643 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 644 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 645 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 646 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 647 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 648 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 649 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 650 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 651 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 652 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 653 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 654 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 655 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 656 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 657 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 658 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 659 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 660 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 661 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 662 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 663 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 664 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 665 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 666 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 667 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 668 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 669 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 670 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 671 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 672 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 673 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 674 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 675 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 676 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 677 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 678 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 679 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 680 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 681 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 682 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 683 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 684 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 685 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 686 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 687 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 688 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 689 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 690 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 691 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 692 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 693 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 694 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 695 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 696 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 697 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 698 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 699 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 700 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 701 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 702 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 703 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 704 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 705 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 706 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 707 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 708 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 709 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 710 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 711 { X86::MINSDrr, X86::MINSDrm, 0 }, 712 { X86::MINSSrr, X86::MINSSrm, 0 }, 713 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 714 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 715 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 716 { X86::MULSDrr, X86::MULSDrm, 0 }, 717 { X86::MULSSrr, X86::MULSSrm, 0 }, 718 { X86::OR16rr, X86::OR16rm, 0 }, 719 { X86::OR32rr, X86::OR32rm, 0 }, 720 { X86::OR64rr, X86::OR64rm, 0 }, 721 { X86::OR8rr, X86::OR8rm, 0 }, 722 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 723 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 724 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 725 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 726 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 727 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 728 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 729 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 730 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 731 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 732 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 733 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 734 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 735 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 736 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 737 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 738 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 739 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 740 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 741 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 742 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 743 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 744 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 745 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 746 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 747 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 748 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 749 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 750 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 751 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 752 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 753 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 754 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 755 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 756 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 757 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 758 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 759 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 760 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 761 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 762 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 763 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 }, 764 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 }, 765 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 }, 766 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 }, 767 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, 768 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 }, 769 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 }, 770 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 }, 771 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 772 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 773 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 774 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 775 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 776 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 777 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 778 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 779 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 780 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 781 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 782 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 783 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 784 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 785 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 786 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 787 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 788 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 789 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 790 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 791 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 792 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 793 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 794 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 795 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 796 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 797 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 798 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 799 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 800 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 801 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 802 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 803 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 804 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 805 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 806 { X86::SBB32rr, X86::SBB32rm, 0 }, 807 { X86::SBB64rr, X86::SBB64rm, 0 }, 808 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 809 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 810 { X86::SUB16rr, X86::SUB16rm, 0 }, 811 { X86::SUB32rr, X86::SUB32rm, 0 }, 812 { X86::SUB64rr, X86::SUB64rm, 0 }, 813 { X86::SUB8rr, X86::SUB8rm, 0 }, 814 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 815 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 816 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 817 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 818 // FIXME: TEST*rr -> swapped operand of TEST*mr. 819 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 820 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 821 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 822 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 823 { X86::XOR16rr, X86::XOR16rm, 0 }, 824 { X86::XOR32rr, X86::XOR32rm, 0 }, 825 { X86::XOR64rr, X86::XOR64rm, 0 }, 826 { X86::XOR8rr, X86::XOR8rm, 0 }, 827 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 828 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 829 // AVX 128-bit versions of foldable instructions 830 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 831 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 832 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 833 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 834 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 835 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 836 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 837 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 838 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 839 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 840 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 841 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 842 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 }, 843 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, 844 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 845 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 846 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 847 { X86::VADDPDrr, X86::VADDPDrm, 0 }, 848 { X86::VADDPSrr, X86::VADDPSrm, 0 }, 849 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 850 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 851 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 }, 852 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 }, 853 { X86::VANDNPDrr, X86::VANDNPDrm, 0 }, 854 { X86::VANDNPSrr, X86::VANDNPSrm, 0 }, 855 { X86::VANDPDrr, X86::VANDPDrm, 0 }, 856 { X86::VANDPSrr, X86::VANDPSrm, 0 }, 857 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 }, 858 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 }, 859 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 }, 860 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 }, 861 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 }, 862 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 }, 863 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 864 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 865 { X86::VDIVPDrr, X86::VDIVPDrm, 0 }, 866 { X86::VDIVPSrr, X86::VDIVPSrm, 0 }, 867 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 868 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 869 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 870 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 871 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 872 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 873 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 874 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 875 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 876 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 877 { X86::VHADDPDrr, X86::VHADDPDrm, 0 }, 878 { X86::VHADDPSrr, X86::VHADDPSrm, 0 }, 879 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 }, 880 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 }, 881 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 882 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 883 { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, 884 { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, 885 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 886 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 887 { X86::VMINPDrr, X86::VMINPDrm, 0 }, 888 { X86::VMINPSrr, X86::VMINPSrm, 0 }, 889 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 890 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 891 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, 892 { X86::VMULPDrr, X86::VMULPDrm, 0 }, 893 { X86::VMULPSrr, X86::VMULPSrm, 0 }, 894 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 895 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 896 { X86::VORPDrr, X86::VORPDrm, 0 }, 897 { X86::VORPSrr, X86::VORPSrm, 0 }, 898 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 }, 899 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 }, 900 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 }, 901 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 }, 902 { X86::VPADDBrr, X86::VPADDBrm, 0 }, 903 { X86::VPADDDrr, X86::VPADDDrm, 0 }, 904 { X86::VPADDQrr, X86::VPADDQrm, 0 }, 905 { X86::VPADDSBrr, X86::VPADDSBrm, 0 }, 906 { X86::VPADDSWrr, X86::VPADDSWrm, 0 }, 907 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 }, 908 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 }, 909 { X86::VPADDWrr, X86::VPADDWrm, 0 }, 910 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 }, 911 { X86::VPANDNrr, X86::VPANDNrm, 0 }, 912 { X86::VPANDrr, X86::VPANDrm, 0 }, 913 { X86::VPAVGBrr, X86::VPAVGBrm, 0 }, 914 { X86::VPAVGWrr, X86::VPAVGWrm, 0 }, 915 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 }, 916 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 }, 917 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 }, 918 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 }, 919 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 }, 920 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 }, 921 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 }, 922 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 }, 923 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 }, 924 { X86::VPHADDDrr, X86::VPHADDDrm, 0 }, 925 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 }, 926 { X86::VPHADDWrr, X86::VPHADDWrm, 0 }, 927 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 }, 928 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 }, 929 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, 930 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, 931 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, 932 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 }, 933 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 }, 934 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, 935 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 }, 936 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 }, 937 { X86::VPMINSWrr, X86::VPMINSWrm, 0 }, 938 { X86::VPMINUBrr, X86::VPMINUBrm, 0 }, 939 { X86::VPMINSBrr, X86::VPMINSBrm, 0 }, 940 { X86::VPMINSDrr, X86::VPMINSDrm, 0 }, 941 { X86::VPMINUDrr, X86::VPMINUDrm, 0 }, 942 { X86::VPMINUWrr, X86::VPMINUWrm, 0 }, 943 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, 944 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 }, 945 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 }, 946 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 }, 947 { X86::VPMULDQrr, X86::VPMULDQrm, 0 }, 948 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 }, 949 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 }, 950 { X86::VPMULHWrr, X86::VPMULHWrm, 0 }, 951 { X86::VPMULLDrr, X86::VPMULLDrm, 0 }, 952 { X86::VPMULLWrr, X86::VPMULLWrm, 0 }, 953 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 }, 954 { X86::VPORrr, X86::VPORrm, 0 }, 955 { X86::VPSADBWrr, X86::VPSADBWrm, 0 }, 956 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 }, 957 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 }, 958 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 }, 959 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 }, 960 { X86::VPSLLDrr, X86::VPSLLDrm, 0 }, 961 { X86::VPSLLQrr, X86::VPSLLQrm, 0 }, 962 { X86::VPSLLWrr, X86::VPSLLWrm, 0 }, 963 { X86::VPSRADrr, X86::VPSRADrm, 0 }, 964 { X86::VPSRAWrr, X86::VPSRAWrm, 0 }, 965 { X86::VPSRLDrr, X86::VPSRLDrm, 0 }, 966 { X86::VPSRLQrr, X86::VPSRLQrm, 0 }, 967 { X86::VPSRLWrr, X86::VPSRLWrm, 0 }, 968 { X86::VPSUBBrr, X86::VPSUBBrm, 0 }, 969 { X86::VPSUBDrr, X86::VPSUBDrm, 0 }, 970 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 }, 971 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 }, 972 { X86::VPSUBWrr, X86::VPSUBWrm, 0 }, 973 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 }, 974 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 }, 975 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 }, 976 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 }, 977 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 }, 978 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 }, 979 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 }, 980 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 }, 981 { X86::VPXORrr, X86::VPXORrm, 0 }, 982 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 }, 983 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 }, 984 { X86::VSUBPDrr, X86::VSUBPDrm, 0 }, 985 { X86::VSUBPSrr, X86::VSUBPSrm, 0 }, 986 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 987 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 988 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 }, 989 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 }, 990 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 }, 991 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 }, 992 { X86::VXORPDrr, X86::VXORPDrm, 0 }, 993 { X86::VXORPSrr, X86::VXORPSrm, 0 }, 994 // AVX 256-bit foldable instructions 995 { X86::VADDPDYrr, X86::VADDPDYrm, 0 }, 996 { X86::VADDPSYrr, X86::VADDPSYrm, 0 }, 997 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 }, 998 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 }, 999 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 }, 1000 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 }, 1001 { X86::VANDPDYrr, X86::VANDPDYrm, 0 }, 1002 { X86::VANDPSYrr, X86::VANDPSYrm, 0 }, 1003 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 }, 1004 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 }, 1005 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 }, 1006 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 }, 1007 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 }, 1008 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 }, 1009 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 }, 1010 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 }, 1011 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 }, 1012 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 }, 1013 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 }, 1014 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, 1015 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, 1016 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, 1017 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, 1018 { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, 1019 { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, 1020 { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, 1021 { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, 1022 { X86::VORPDYrr, X86::VORPDYrm, 0 }, 1023 { X86::VORPSYrr, X86::VORPSYrm, 0 }, 1024 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 }, 1025 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 }, 1026 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 }, 1027 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 }, 1028 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 }, 1029 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 }, 1030 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 }, 1031 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 }, 1032 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 }, 1033 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 }, 1034 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 }, 1035 { X86::VXORPDYrr, X86::VXORPDYrm, 0 }, 1036 { X86::VXORPSYrr, X86::VXORPSYrm, 0 }, 1037 // AVX2 foldable instructions 1038 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 }, 1039 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 }, 1040 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 }, 1041 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 }, 1042 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 }, 1043 { X86::VPADDBYrr, X86::VPADDBYrm, 0 }, 1044 { X86::VPADDDYrr, X86::VPADDDYrm, 0 }, 1045 { X86::VPADDQYrr, X86::VPADDQYrm, 0 }, 1046 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 }, 1047 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 }, 1048 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 }, 1049 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 }, 1050 { X86::VPADDWYrr, X86::VPADDWYrm, 0 }, 1051 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 }, 1052 { X86::VPANDNYrr, X86::VPANDNYrm, 0 }, 1053 { X86::VPANDYrr, X86::VPANDYrm, 0 }, 1054 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 }, 1055 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 }, 1056 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 }, 1057 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 }, 1058 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 }, 1059 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 }, 1060 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 }, 1061 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 }, 1062 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 }, 1063 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 }, 1064 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 }, 1065 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 }, 1066 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 }, 1067 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 }, 1068 { X86::VPERMDYrr, X86::VPERMDYrm, 0 }, 1069 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 }, 1070 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 }, 1071 { X86::VPERMQYri, X86::VPERMQYmi, 0 }, 1072 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 }, 1073 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 }, 1074 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 }, 1075 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 }, 1076 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 }, 1077 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 }, 1078 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 }, 1079 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 }, 1080 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 }, 1081 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 }, 1082 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 }, 1083 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 }, 1084 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 }, 1085 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 }, 1086 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 }, 1087 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 }, 1088 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 }, 1089 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 }, 1090 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 }, 1091 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 }, 1092 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 }, 1093 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 }, 1094 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 }, 1095 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 }, 1096 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 }, 1097 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 }, 1098 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 }, 1099 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 }, 1100 { X86::VPORYrr, X86::VPORYrm, 0 }, 1101 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 }, 1102 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 }, 1103 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 }, 1104 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 }, 1105 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 }, 1106 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 }, 1107 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 }, 1108 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 }, 1109 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 }, 1110 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 }, 1111 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 }, 1112 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 }, 1113 { X86::VPSRADYrr, X86::VPSRADYrm, 0 }, 1114 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 }, 1115 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 }, 1116 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 }, 1117 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 }, 1118 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 }, 1119 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 }, 1120 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 }, 1121 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 }, 1122 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 }, 1123 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 }, 1124 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 }, 1125 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 }, 1126 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 }, 1127 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 }, 1128 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 }, 1129 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 }, 1130 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 }, 1131 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 }, 1132 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 }, 1133 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 }, 1134 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 }, 1135 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 }, 1136 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 }, 1137 { X86::VPXORYrr, X86::VPXORYrm, 0 }, 1138 // FIXME: add AVX 256-bit foldable instructions 1139 1140 // FMA4 foldable patterns 1141 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 }, 1142 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 }, 1143 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 }, 1144 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 }, 1145 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 }, 1146 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 }, 1147 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 }, 1148 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 }, 1149 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 }, 1150 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 }, 1151 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 }, 1152 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 }, 1153 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 }, 1154 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 }, 1155 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 }, 1156 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 }, 1157 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 }, 1158 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 }, 1159 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 }, 1160 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 }, 1161 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 }, 1162 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 }, 1163 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 }, 1164 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 }, 1165 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 }, 1166 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 }, 1167 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 }, 1168 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 }, 1169 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 }, 1170 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 }, 1171 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 }, 1172 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 }, 1173 1174 // BMI/BMI2 foldable instructions 1175 { X86::ANDN32rr, X86::ANDN32rm, 0 }, 1176 { X86::ANDN64rr, X86::ANDN64rm, 0 }, 1177 { X86::MULX32rr, X86::MULX32rm, 0 }, 1178 { X86::MULX64rr, X86::MULX64rm, 0 }, 1179 { X86::PDEP32rr, X86::PDEP32rm, 0 }, 1180 { X86::PDEP64rr, X86::PDEP64rm, 0 }, 1181 { X86::PEXT32rr, X86::PEXT32rm, 0 }, 1182 { X86::PEXT64rr, X86::PEXT64rm, 0 }, 1183 }; 1184 1185 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1186 unsigned RegOp = OpTbl2[i].RegOp; 1187 unsigned MemOp = OpTbl2[i].MemOp; 1188 unsigned Flags = OpTbl2[i].Flags; 1189 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1190 RegOp, MemOp, 1191 // Index 2, folded load 1192 Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1193 } 1194 1195 static const X86OpTblEntry OpTbl3[] = { 1196 // FMA foldable instructions 1197 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 }, 1198 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 }, 1199 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 }, 1200 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 }, 1201 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 }, 1202 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 }, 1203 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 }, 1204 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 }, 1205 1206 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 }, 1207 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 }, 1208 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 }, 1209 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 }, 1210 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 }, 1211 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 }, 1212 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 }, 1213 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 }, 1214 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 }, 1215 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 }, 1216 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 }, 1217 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 }, 1218 1219 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 }, 1220 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 }, 1221 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 }, 1222 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 }, 1223 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 }, 1224 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 }, 1225 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 }, 1226 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 }, 1227 1228 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 }, 1229 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 }, 1230 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 }, 1231 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 }, 1232 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 }, 1233 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 }, 1234 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 }, 1235 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 }, 1236 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 }, 1237 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 }, 1238 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 }, 1239 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 }, 1240 1241 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 }, 1242 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 }, 1243 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 }, 1244 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 }, 1245 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 }, 1246 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 }, 1247 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 }, 1248 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 }, 1249 1250 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 }, 1251 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 }, 1252 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 }, 1253 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 }, 1254 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 }, 1255 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 }, 1256 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 }, 1257 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 }, 1258 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 }, 1259 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 }, 1260 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 }, 1261 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 }, 1262 1263 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 }, 1264 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 }, 1265 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 }, 1266 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 }, 1267 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 }, 1268 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 }, 1269 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 }, 1270 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 }, 1271 1272 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 }, 1273 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 }, 1274 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 }, 1275 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 }, 1276 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 }, 1277 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 }, 1278 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 }, 1279 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 }, 1280 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 }, 1281 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 }, 1282 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 }, 1283 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 }, 1284 1285 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 }, 1286 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 }, 1287 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 }, 1288 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 }, 1289 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 }, 1290 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 }, 1291 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 }, 1292 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 }, 1293 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 }, 1294 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 }, 1295 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 }, 1296 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 }, 1297 1298 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 }, 1299 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 }, 1300 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 }, 1301 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 }, 1302 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 }, 1303 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 }, 1304 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 }, 1305 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 }, 1306 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 }, 1307 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 }, 1308 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 }, 1309 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 }, 1310 1311 // FMA4 foldable patterns 1312 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 }, 1313 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 }, 1314 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 }, 1315 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 }, 1316 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 }, 1317 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 }, 1318 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 }, 1319 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 }, 1320 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 }, 1321 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 }, 1322 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 }, 1323 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 }, 1324 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 }, 1325 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 }, 1326 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 }, 1327 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 }, 1328 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 }, 1329 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 }, 1330 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 }, 1331 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 }, 1332 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 }, 1333 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 }, 1334 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 }, 1335 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 }, 1336 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 }, 1337 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 }, 1338 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 }, 1339 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 }, 1340 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 }, 1341 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 }, 1342 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 }, 1343 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 }, 1344 }; 1345 1346 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1347 unsigned RegOp = OpTbl3[i].RegOp; 1348 unsigned MemOp = OpTbl3[i].MemOp; 1349 unsigned Flags = OpTbl3[i].Flags; 1350 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1351 RegOp, MemOp, 1352 // Index 3, folded load 1353 Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1354 } 1355 1356 } 1357 1358 void 1359 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1360 MemOp2RegOpTableType &M2RTable, 1361 unsigned RegOp, unsigned MemOp, unsigned Flags) { 1362 if ((Flags & TB_NO_FORWARD) == 0) { 1363 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1364 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1365 } 1366 if ((Flags & TB_NO_REVERSE) == 0) { 1367 assert(!M2RTable.count(MemOp) && 1368 "Duplicated entries in unfolding maps?"); 1369 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1370 } 1371 } 1372 1373 bool 1374 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1375 unsigned &SrcReg, unsigned &DstReg, 1376 unsigned &SubIdx) const { 1377 switch (MI.getOpcode()) { 1378 default: break; 1379 case X86::MOVSX16rr8: 1380 case X86::MOVZX16rr8: 1381 case X86::MOVSX32rr8: 1382 case X86::MOVZX32rr8: 1383 case X86::MOVSX64rr8: 1384 case X86::MOVZX64rr8: 1385 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 1386 // It's not always legal to reference the low 8-bit of the larger 1387 // register in 32-bit mode. 1388 return false; 1389 case X86::MOVSX32rr16: 1390 case X86::MOVZX32rr16: 1391 case X86::MOVSX64rr16: 1392 case X86::MOVZX64rr16: 1393 case X86::MOVSX64rr32: 1394 case X86::MOVZX64rr32: { 1395 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1396 // Be conservative. 1397 return false; 1398 SrcReg = MI.getOperand(1).getReg(); 1399 DstReg = MI.getOperand(0).getReg(); 1400 switch (MI.getOpcode()) { 1401 default: llvm_unreachable("Unreachable!"); 1402 case X86::MOVSX16rr8: 1403 case X86::MOVZX16rr8: 1404 case X86::MOVSX32rr8: 1405 case X86::MOVZX32rr8: 1406 case X86::MOVSX64rr8: 1407 case X86::MOVZX64rr8: 1408 SubIdx = X86::sub_8bit; 1409 break; 1410 case X86::MOVSX32rr16: 1411 case X86::MOVZX32rr16: 1412 case X86::MOVSX64rr16: 1413 case X86::MOVZX64rr16: 1414 SubIdx = X86::sub_16bit; 1415 break; 1416 case X86::MOVSX64rr32: 1417 case X86::MOVZX64rr32: 1418 SubIdx = X86::sub_32bit; 1419 break; 1420 } 1421 return true; 1422 } 1423 } 1424 return false; 1425 } 1426 1427 /// isFrameOperand - Return true and the FrameIndex if the specified 1428 /// operand and follow operands form a reference to the stack frame. 1429 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1430 int &FrameIndex) const { 1431 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 1432 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 1433 MI->getOperand(Op+1).getImm() == 1 && 1434 MI->getOperand(Op+2).getReg() == 0 && 1435 MI->getOperand(Op+3).getImm() == 0) { 1436 FrameIndex = MI->getOperand(Op).getIndex(); 1437 return true; 1438 } 1439 return false; 1440 } 1441 1442 static bool isFrameLoadOpcode(int Opcode) { 1443 switch (Opcode) { 1444 default: 1445 return false; 1446 case X86::MOV8rm: 1447 case X86::MOV16rm: 1448 case X86::MOV32rm: 1449 case X86::MOV64rm: 1450 case X86::LD_Fp64m: 1451 case X86::MOVSSrm: 1452 case X86::MOVSDrm: 1453 case X86::MOVAPSrm: 1454 case X86::MOVAPDrm: 1455 case X86::MOVDQArm: 1456 case X86::VMOVSSrm: 1457 case X86::VMOVSDrm: 1458 case X86::VMOVAPSrm: 1459 case X86::VMOVAPDrm: 1460 case X86::VMOVDQArm: 1461 case X86::VMOVAPSYrm: 1462 case X86::VMOVAPDYrm: 1463 case X86::VMOVDQAYrm: 1464 case X86::MMX_MOVD64rm: 1465 case X86::MMX_MOVQ64rm: 1466 return true; 1467 } 1468 } 1469 1470 static bool isFrameStoreOpcode(int Opcode) { 1471 switch (Opcode) { 1472 default: break; 1473 case X86::MOV8mr: 1474 case X86::MOV16mr: 1475 case X86::MOV32mr: 1476 case X86::MOV64mr: 1477 case X86::ST_FpP64m: 1478 case X86::MOVSSmr: 1479 case X86::MOVSDmr: 1480 case X86::MOVAPSmr: 1481 case X86::MOVAPDmr: 1482 case X86::MOVDQAmr: 1483 case X86::VMOVSSmr: 1484 case X86::VMOVSDmr: 1485 case X86::VMOVAPSmr: 1486 case X86::VMOVAPDmr: 1487 case X86::VMOVDQAmr: 1488 case X86::VMOVAPSYmr: 1489 case X86::VMOVAPDYmr: 1490 case X86::VMOVDQAYmr: 1491 case X86::MMX_MOVD64mr: 1492 case X86::MMX_MOVQ64mr: 1493 case X86::MMX_MOVNTQmr: 1494 return true; 1495 } 1496 return false; 1497 } 1498 1499 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1500 int &FrameIndex) const { 1501 if (isFrameLoadOpcode(MI->getOpcode())) 1502 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1503 return MI->getOperand(0).getReg(); 1504 return 0; 1505 } 1506 1507 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1508 int &FrameIndex) const { 1509 if (isFrameLoadOpcode(MI->getOpcode())) { 1510 unsigned Reg; 1511 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1512 return Reg; 1513 // Check for post-frame index elimination operations 1514 const MachineMemOperand *Dummy; 1515 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1516 } 1517 return 0; 1518 } 1519 1520 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1521 int &FrameIndex) const { 1522 if (isFrameStoreOpcode(MI->getOpcode())) 1523 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1524 isFrameOperand(MI, 0, FrameIndex)) 1525 return MI->getOperand(X86::AddrNumOperands).getReg(); 1526 return 0; 1527 } 1528 1529 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1530 int &FrameIndex) const { 1531 if (isFrameStoreOpcode(MI->getOpcode())) { 1532 unsigned Reg; 1533 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1534 return Reg; 1535 // Check for post-frame index elimination operations 1536 const MachineMemOperand *Dummy; 1537 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1538 } 1539 return 0; 1540 } 1541 1542 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1543 /// X86::MOVPC32r. 1544 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1545 // Don't waste compile time scanning use-def chains of physregs. 1546 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1547 return false; 1548 bool isPICBase = false; 1549 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1550 E = MRI.def_end(); I != E; ++I) { 1551 MachineInstr *DefMI = I.getOperand().getParent(); 1552 if (DefMI->getOpcode() != X86::MOVPC32r) 1553 return false; 1554 assert(!isPICBase && "More than one PIC base?"); 1555 isPICBase = true; 1556 } 1557 return isPICBase; 1558 } 1559 1560 bool 1561 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1562 AliasAnalysis *AA) const { 1563 switch (MI->getOpcode()) { 1564 default: break; 1565 case X86::MOV8rm: 1566 case X86::MOV16rm: 1567 case X86::MOV32rm: 1568 case X86::MOV64rm: 1569 case X86::LD_Fp64m: 1570 case X86::MOVSSrm: 1571 case X86::MOVSDrm: 1572 case X86::MOVAPSrm: 1573 case X86::MOVUPSrm: 1574 case X86::MOVAPDrm: 1575 case X86::MOVDQArm: 1576 case X86::MOVDQUrm: 1577 case X86::VMOVSSrm: 1578 case X86::VMOVSDrm: 1579 case X86::VMOVAPSrm: 1580 case X86::VMOVUPSrm: 1581 case X86::VMOVAPDrm: 1582 case X86::VMOVDQArm: 1583 case X86::VMOVDQUrm: 1584 case X86::VMOVAPSYrm: 1585 case X86::VMOVUPSYrm: 1586 case X86::VMOVAPDYrm: 1587 case X86::VMOVDQAYrm: 1588 case X86::VMOVDQUYrm: 1589 case X86::MMX_MOVD64rm: 1590 case X86::MMX_MOVQ64rm: 1591 case X86::FsVMOVAPSrm: 1592 case X86::FsVMOVAPDrm: 1593 case X86::FsMOVAPSrm: 1594 case X86::FsMOVAPDrm: { 1595 // Loads from constant pools are trivially rematerializable. 1596 if (MI->getOperand(1).isReg() && 1597 MI->getOperand(2).isImm() && 1598 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1599 MI->isInvariantLoad(AA)) { 1600 unsigned BaseReg = MI->getOperand(1).getReg(); 1601 if (BaseReg == 0 || BaseReg == X86::RIP) 1602 return true; 1603 // Allow re-materialization of PIC load. 1604 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 1605 return false; 1606 const MachineFunction &MF = *MI->getParent()->getParent(); 1607 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1608 return regIsPICBase(BaseReg, MRI); 1609 } 1610 return false; 1611 } 1612 1613 case X86::LEA32r: 1614 case X86::LEA64r: { 1615 if (MI->getOperand(2).isImm() && 1616 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1617 !MI->getOperand(4).isReg()) { 1618 // lea fi#, lea GV, etc. are all rematerializable. 1619 if (!MI->getOperand(1).isReg()) 1620 return true; 1621 unsigned BaseReg = MI->getOperand(1).getReg(); 1622 if (BaseReg == 0) 1623 return true; 1624 // Allow re-materialization of lea PICBase + x. 1625 const MachineFunction &MF = *MI->getParent()->getParent(); 1626 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1627 return regIsPICBase(BaseReg, MRI); 1628 } 1629 return false; 1630 } 1631 } 1632 1633 // All other instructions marked M_REMATERIALIZABLE are always trivially 1634 // rematerializable. 1635 return true; 1636 } 1637 1638 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 1639 /// would clobber the EFLAGS condition register. Note the result may be 1640 /// conservative. If it cannot definitely determine the safety after visiting 1641 /// a few instructions in each direction it assumes it's not safe. 1642 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1643 MachineBasicBlock::iterator I) { 1644 MachineBasicBlock::iterator E = MBB.end(); 1645 1646 // For compile time consideration, if we are not able to determine the 1647 // safety after visiting 4 instructions in each direction, we will assume 1648 // it's not safe. 1649 MachineBasicBlock::iterator Iter = I; 1650 for (unsigned i = 0; Iter != E && i < 4; ++i) { 1651 bool SeenDef = false; 1652 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1653 MachineOperand &MO = Iter->getOperand(j); 1654 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1655 SeenDef = true; 1656 if (!MO.isReg()) 1657 continue; 1658 if (MO.getReg() == X86::EFLAGS) { 1659 if (MO.isUse()) 1660 return false; 1661 SeenDef = true; 1662 } 1663 } 1664 1665 if (SeenDef) 1666 // This instruction defines EFLAGS, no need to look any further. 1667 return true; 1668 ++Iter; 1669 // Skip over DBG_VALUE. 1670 while (Iter != E && Iter->isDebugValue()) 1671 ++Iter; 1672 } 1673 1674 // It is safe to clobber EFLAGS at the end of a block of no successor has it 1675 // live in. 1676 if (Iter == E) { 1677 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1678 SE = MBB.succ_end(); SI != SE; ++SI) 1679 if ((*SI)->isLiveIn(X86::EFLAGS)) 1680 return false; 1681 return true; 1682 } 1683 1684 MachineBasicBlock::iterator B = MBB.begin(); 1685 Iter = I; 1686 for (unsigned i = 0; i < 4; ++i) { 1687 // If we make it to the beginning of the block, it's safe to clobber 1688 // EFLAGS iff EFLAGS is not live-in. 1689 if (Iter == B) 1690 return !MBB.isLiveIn(X86::EFLAGS); 1691 1692 --Iter; 1693 // Skip over DBG_VALUE. 1694 while (Iter != B && Iter->isDebugValue()) 1695 --Iter; 1696 1697 bool SawKill = false; 1698 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1699 MachineOperand &MO = Iter->getOperand(j); 1700 // A register mask may clobber EFLAGS, but we should still look for a 1701 // live EFLAGS def. 1702 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1703 SawKill = true; 1704 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1705 if (MO.isDef()) return MO.isDead(); 1706 if (MO.isKill()) SawKill = true; 1707 } 1708 } 1709 1710 if (SawKill) 1711 // This instruction kills EFLAGS and doesn't redefine it, so 1712 // there's no need to look further. 1713 return true; 1714 } 1715 1716 // Conservative answer. 1717 return false; 1718 } 1719 1720 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1721 MachineBasicBlock::iterator I, 1722 unsigned DestReg, unsigned SubIdx, 1723 const MachineInstr *Orig, 1724 const TargetRegisterInfo &TRI) const { 1725 DebugLoc DL = Orig->getDebugLoc(); 1726 1727 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1728 // Re-materialize them as movri instructions to avoid side effects. 1729 bool Clone = true; 1730 unsigned Opc = Orig->getOpcode(); 1731 switch (Opc) { 1732 default: break; 1733 case X86::MOV8r0: 1734 case X86::MOV16r0: 1735 case X86::MOV32r0: 1736 case X86::MOV64r0: { 1737 if (!isSafeToClobberEFLAGS(MBB, I)) { 1738 switch (Opc) { 1739 default: llvm_unreachable("Unreachable!"); 1740 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1741 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1742 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1743 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1744 } 1745 Clone = false; 1746 } 1747 break; 1748 } 1749 } 1750 1751 if (Clone) { 1752 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1753 MBB.insert(I, MI); 1754 } else { 1755 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1756 } 1757 1758 MachineInstr *NewMI = prior(I); 1759 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1760 } 1761 1762 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1763 /// is not marked dead. 1764 static bool hasLiveCondCodeDef(MachineInstr *MI) { 1765 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1766 MachineOperand &MO = MI->getOperand(i); 1767 if (MO.isReg() && MO.isDef() && 1768 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1769 return true; 1770 } 1771 } 1772 return false; 1773 } 1774 1775 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1776 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1777 /// to a 32-bit superregister and then truncating back down to a 16-bit 1778 /// subregister. 1779 MachineInstr * 1780 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1781 MachineFunction::iterator &MFI, 1782 MachineBasicBlock::iterator &MBBI, 1783 LiveVariables *LV) const { 1784 MachineInstr *MI = MBBI; 1785 unsigned Dest = MI->getOperand(0).getReg(); 1786 unsigned Src = MI->getOperand(1).getReg(); 1787 bool isDead = MI->getOperand(0).isDead(); 1788 bool isKill = MI->getOperand(1).isKill(); 1789 1790 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1791 ? X86::LEA64_32r : X86::LEA32r; 1792 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1793 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1794 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1795 1796 // Build and insert into an implicit UNDEF value. This is OK because 1797 // well be shifting and then extracting the lower 16-bits. 1798 // This has the potential to cause partial register stall. e.g. 1799 // movw (%rbp,%rcx,2), %dx 1800 // leal -65(%rdx), %esi 1801 // But testing has shown this *does* help performance in 64-bit mode (at 1802 // least on modern x86 machines). 1803 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1804 MachineInstr *InsMI = 1805 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1806 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1807 .addReg(Src, getKillRegState(isKill)); 1808 1809 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1810 get(Opc), leaOutReg); 1811 switch (MIOpc) { 1812 default: llvm_unreachable("Unreachable!"); 1813 case X86::SHL16ri: { 1814 unsigned ShAmt = MI->getOperand(2).getImm(); 1815 MIB.addReg(0).addImm(1 << ShAmt) 1816 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1817 break; 1818 } 1819 case X86::INC16r: 1820 case X86::INC64_16r: 1821 addRegOffset(MIB, leaInReg, true, 1); 1822 break; 1823 case X86::DEC16r: 1824 case X86::DEC64_16r: 1825 addRegOffset(MIB, leaInReg, true, -1); 1826 break; 1827 case X86::ADD16ri: 1828 case X86::ADD16ri8: 1829 case X86::ADD16ri_DB: 1830 case X86::ADD16ri8_DB: 1831 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1832 break; 1833 case X86::ADD16rr: 1834 case X86::ADD16rr_DB: { 1835 unsigned Src2 = MI->getOperand(2).getReg(); 1836 bool isKill2 = MI->getOperand(2).isKill(); 1837 unsigned leaInReg2 = 0; 1838 MachineInstr *InsMI2 = 0; 1839 if (Src == Src2) { 1840 // ADD16rr %reg1028<kill>, %reg1028 1841 // just a single insert_subreg. 1842 addRegReg(MIB, leaInReg, true, leaInReg, false); 1843 } else { 1844 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1845 // Build and insert into an implicit UNDEF value. This is OK because 1846 // well be shifting and then extracting the lower 16-bits. 1847 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1848 InsMI2 = 1849 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1850 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1851 .addReg(Src2, getKillRegState(isKill2)); 1852 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1853 } 1854 if (LV && isKill2 && InsMI2) 1855 LV->replaceKillInstruction(Src2, MI, InsMI2); 1856 break; 1857 } 1858 } 1859 1860 MachineInstr *NewMI = MIB; 1861 MachineInstr *ExtMI = 1862 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1863 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1864 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1865 1866 if (LV) { 1867 // Update live variables 1868 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1869 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1870 if (isKill) 1871 LV->replaceKillInstruction(Src, MI, InsMI); 1872 if (isDead) 1873 LV->replaceKillInstruction(Dest, MI, ExtMI); 1874 } 1875 1876 return ExtMI; 1877 } 1878 1879 /// convertToThreeAddress - This method must be implemented by targets that 1880 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1881 /// may be able to convert a two-address instruction into a true 1882 /// three-address instruction on demand. This allows the X86 target (for 1883 /// example) to convert ADD and SHL instructions into LEA instructions if they 1884 /// would require register copies due to two-addressness. 1885 /// 1886 /// This method returns a null pointer if the transformation cannot be 1887 /// performed, otherwise it returns the new instruction. 1888 /// 1889 MachineInstr * 1890 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1891 MachineBasicBlock::iterator &MBBI, 1892 LiveVariables *LV) const { 1893 MachineInstr *MI = MBBI; 1894 MachineFunction &MF = *MI->getParent()->getParent(); 1895 // All instructions input are two-addr instructions. Get the known operands. 1896 const MachineOperand &Dest = MI->getOperand(0); 1897 const MachineOperand &Src = MI->getOperand(1); 1898 1899 MachineInstr *NewMI = NULL; 1900 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1901 // we have better subtarget support, enable the 16-bit LEA generation here. 1902 // 16-bit LEA is also slow on Core2. 1903 bool DisableLEA16 = true; 1904 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1905 1906 unsigned MIOpc = MI->getOpcode(); 1907 switch (MIOpc) { 1908 case X86::SHUFPSrri: { 1909 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1910 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1911 1912 unsigned B = MI->getOperand(1).getReg(); 1913 unsigned C = MI->getOperand(2).getReg(); 1914 if (B != C) return 0; 1915 unsigned M = MI->getOperand(3).getImm(); 1916 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1917 .addOperand(Dest).addOperand(Src).addImm(M); 1918 break; 1919 } 1920 case X86::SHUFPDrri: { 1921 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!"); 1922 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1923 1924 unsigned B = MI->getOperand(1).getReg(); 1925 unsigned C = MI->getOperand(2).getReg(); 1926 if (B != C) return 0; 1927 unsigned M = MI->getOperand(3).getImm(); 1928 1929 // Convert to PSHUFD mask. 1930 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44; 1931 1932 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1933 .addOperand(Dest).addOperand(Src).addImm(M); 1934 break; 1935 } 1936 case X86::SHL64ri: { 1937 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1938 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1939 // the flags produced by a shift yet, so this is safe. 1940 unsigned ShAmt = MI->getOperand(2).getImm(); 1941 if (ShAmt == 0 || ShAmt >= 4) return 0; 1942 1943 // LEA can't handle RSP. 1944 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1945 !MF.getRegInfo().constrainRegClass(Src.getReg(), 1946 &X86::GR64_NOSPRegClass)) 1947 return 0; 1948 1949 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1950 .addOperand(Dest) 1951 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1952 break; 1953 } 1954 case X86::SHL32ri: { 1955 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1956 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1957 // the flags produced by a shift yet, so this is safe. 1958 unsigned ShAmt = MI->getOperand(2).getImm(); 1959 if (ShAmt == 0 || ShAmt >= 4) return 0; 1960 1961 // LEA can't handle ESP. 1962 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1963 !MF.getRegInfo().constrainRegClass(Src.getReg(), 1964 &X86::GR32_NOSPRegClass)) 1965 return 0; 1966 1967 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1968 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1969 .addOperand(Dest) 1970 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1971 break; 1972 } 1973 case X86::SHL16ri: { 1974 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1975 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1976 // the flags produced by a shift yet, so this is safe. 1977 unsigned ShAmt = MI->getOperand(2).getImm(); 1978 if (ShAmt == 0 || ShAmt >= 4) return 0; 1979 1980 if (DisableLEA16) 1981 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1982 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1983 .addOperand(Dest) 1984 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1985 break; 1986 } 1987 default: { 1988 // The following opcodes also sets the condition code register(s). Only 1989 // convert them to equivalent lea if the condition code register def's 1990 // are dead! 1991 if (hasLiveCondCodeDef(MI)) 1992 return 0; 1993 1994 switch (MIOpc) { 1995 default: return 0; 1996 case X86::INC64r: 1997 case X86::INC32r: 1998 case X86::INC64_32r: { 1999 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2000 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 2001 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2002 const TargetRegisterClass *RC = MIOpc == X86::INC64r ? 2003 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 2004 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 2005 2006 // LEA can't handle RSP. 2007 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2008 !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 2009 return 0; 2010 2011 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2012 .addOperand(Dest).addOperand(Src), 1); 2013 break; 2014 } 2015 case X86::INC16r: 2016 case X86::INC64_16r: 2017 if (DisableLEA16) 2018 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2019 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2020 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2021 .addOperand(Dest).addOperand(Src), 1); 2022 break; 2023 case X86::DEC64r: 2024 case X86::DEC32r: 2025 case X86::DEC64_32r: { 2026 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2027 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 2028 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2029 const TargetRegisterClass *RC = MIOpc == X86::DEC64r ? 2030 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 2031 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 2032 // LEA can't handle RSP. 2033 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2034 !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 2035 return 0; 2036 2037 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2038 .addOperand(Dest).addOperand(Src), -1); 2039 break; 2040 } 2041 case X86::DEC16r: 2042 case X86::DEC64_16r: 2043 if (DisableLEA16) 2044 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2045 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2046 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2047 .addOperand(Dest).addOperand(Src), -1); 2048 break; 2049 case X86::ADD64rr: 2050 case X86::ADD64rr_DB: 2051 case X86::ADD32rr: 2052 case X86::ADD32rr_DB: { 2053 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2054 unsigned Opc; 2055 const TargetRegisterClass *RC; 2056 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) { 2057 Opc = X86::LEA64r; 2058 RC = &X86::GR64_NOSPRegClass; 2059 } else { 2060 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2061 RC = &X86::GR32_NOSPRegClass; 2062 } 2063 2064 2065 unsigned Src2 = MI->getOperand(2).getReg(); 2066 bool isKill2 = MI->getOperand(2).isKill(); 2067 2068 // LEA can't handle RSP. 2069 if (TargetRegisterInfo::isVirtualRegister(Src2) && 2070 !MF.getRegInfo().constrainRegClass(Src2, RC)) 2071 return 0; 2072 2073 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2074 .addOperand(Dest), 2075 Src.getReg(), Src.isKill(), Src2, isKill2); 2076 2077 // Preserve undefness of the operands. 2078 bool isUndef = MI->getOperand(1).isUndef(); 2079 bool isUndef2 = MI->getOperand(2).isUndef(); 2080 NewMI->getOperand(1).setIsUndef(isUndef); 2081 NewMI->getOperand(3).setIsUndef(isUndef2); 2082 2083 if (LV && isKill2) 2084 LV->replaceKillInstruction(Src2, MI, NewMI); 2085 break; 2086 } 2087 case X86::ADD16rr: 2088 case X86::ADD16rr_DB: { 2089 if (DisableLEA16) 2090 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2091 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2092 unsigned Src2 = MI->getOperand(2).getReg(); 2093 bool isKill2 = MI->getOperand(2).isKill(); 2094 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2095 .addOperand(Dest), 2096 Src.getReg(), Src.isKill(), Src2, isKill2); 2097 2098 // Preserve undefness of the operands. 2099 bool isUndef = MI->getOperand(1).isUndef(); 2100 bool isUndef2 = MI->getOperand(2).isUndef(); 2101 NewMI->getOperand(1).setIsUndef(isUndef); 2102 NewMI->getOperand(3).setIsUndef(isUndef2); 2103 2104 if (LV && isKill2) 2105 LV->replaceKillInstruction(Src2, MI, NewMI); 2106 break; 2107 } 2108 case X86::ADD64ri32: 2109 case X86::ADD64ri8: 2110 case X86::ADD64ri32_DB: 2111 case X86::ADD64ri8_DB: 2112 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2113 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2114 .addOperand(Dest).addOperand(Src), 2115 MI->getOperand(2).getImm()); 2116 break; 2117 case X86::ADD32ri: 2118 case X86::ADD32ri8: 2119 case X86::ADD32ri_DB: 2120 case X86::ADD32ri8_DB: { 2121 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2122 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2123 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2124 .addOperand(Dest).addOperand(Src), 2125 MI->getOperand(2).getImm()); 2126 break; 2127 } 2128 case X86::ADD16ri: 2129 case X86::ADD16ri8: 2130 case X86::ADD16ri_DB: 2131 case X86::ADD16ri8_DB: 2132 if (DisableLEA16) 2133 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2134 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2135 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2136 .addOperand(Dest).addOperand(Src), 2137 MI->getOperand(2).getImm()); 2138 break; 2139 } 2140 } 2141 } 2142 2143 if (!NewMI) return 0; 2144 2145 if (LV) { // Update live variables 2146 if (Src.isKill()) 2147 LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2148 if (Dest.isDead()) 2149 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2150 } 2151 2152 MFI->insert(MBBI, NewMI); // Insert the new inst 2153 return NewMI; 2154 } 2155 2156 /// commuteInstruction - We have a few instructions that must be hacked on to 2157 /// commute them. 2158 /// 2159 MachineInstr * 2160 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2161 switch (MI->getOpcode()) { 2162 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2163 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2164 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2165 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2166 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2167 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2168 unsigned Opc; 2169 unsigned Size; 2170 switch (MI->getOpcode()) { 2171 default: llvm_unreachable("Unreachable!"); 2172 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2173 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2174 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2175 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2176 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2177 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2178 } 2179 unsigned Amt = MI->getOperand(3).getImm(); 2180 if (NewMI) { 2181 MachineFunction &MF = *MI->getParent()->getParent(); 2182 MI = MF.CloneMachineInstr(MI); 2183 NewMI = false; 2184 } 2185 MI->setDesc(get(Opc)); 2186 MI->getOperand(3).setImm(Size-Amt); 2187 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2188 } 2189 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2190 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2191 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2192 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2193 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2194 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2195 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2196 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2197 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2198 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2199 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2200 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2201 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2202 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2203 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2204 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2205 unsigned Opc; 2206 switch (MI->getOpcode()) { 2207 default: llvm_unreachable("Unreachable!"); 2208 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2209 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2210 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2211 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2212 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2213 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2214 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2215 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2216 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2217 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2218 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2219 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2220 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2221 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2222 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2223 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2224 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2225 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2226 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2227 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2228 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2229 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2230 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2231 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2232 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2233 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2234 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2235 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2236 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2237 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2238 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2239 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2240 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2241 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2242 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2243 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2244 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2245 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2246 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2247 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2248 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2249 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2250 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2251 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2252 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2253 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2254 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2255 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2256 } 2257 if (NewMI) { 2258 MachineFunction &MF = *MI->getParent()->getParent(); 2259 MI = MF.CloneMachineInstr(MI); 2260 NewMI = false; 2261 } 2262 MI->setDesc(get(Opc)); 2263 // Fallthrough intended. 2264 } 2265 default: 2266 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2267 } 2268 } 2269 2270 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2271 switch (BrOpc) { 2272 default: return X86::COND_INVALID; 2273 case X86::JE_4: return X86::COND_E; 2274 case X86::JNE_4: return X86::COND_NE; 2275 case X86::JL_4: return X86::COND_L; 2276 case X86::JLE_4: return X86::COND_LE; 2277 case X86::JG_4: return X86::COND_G; 2278 case X86::JGE_4: return X86::COND_GE; 2279 case X86::JB_4: return X86::COND_B; 2280 case X86::JBE_4: return X86::COND_BE; 2281 case X86::JA_4: return X86::COND_A; 2282 case X86::JAE_4: return X86::COND_AE; 2283 case X86::JS_4: return X86::COND_S; 2284 case X86::JNS_4: return X86::COND_NS; 2285 case X86::JP_4: return X86::COND_P; 2286 case X86::JNP_4: return X86::COND_NP; 2287 case X86::JO_4: return X86::COND_O; 2288 case X86::JNO_4: return X86::COND_NO; 2289 } 2290 } 2291 2292 /// getCondFromSETOpc - return condition code of a SET opcode. 2293 static X86::CondCode getCondFromSETOpc(unsigned Opc) { 2294 switch (Opc) { 2295 default: return X86::COND_INVALID; 2296 case X86::SETAr: case X86::SETAm: return X86::COND_A; 2297 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2298 case X86::SETBr: case X86::SETBm: return X86::COND_B; 2299 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2300 case X86::SETEr: case X86::SETEm: return X86::COND_E; 2301 case X86::SETGr: case X86::SETGm: return X86::COND_G; 2302 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2303 case X86::SETLr: case X86::SETLm: return X86::COND_L; 2304 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2305 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2306 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2307 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2308 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2309 case X86::SETOr: case X86::SETOm: return X86::COND_O; 2310 case X86::SETPr: case X86::SETPm: return X86::COND_P; 2311 case X86::SETSr: case X86::SETSm: return X86::COND_S; 2312 } 2313 } 2314 2315 /// getCondFromCmovOpc - return condition code of a CMov opcode. 2316 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 2317 switch (Opc) { 2318 default: return X86::COND_INVALID; 2319 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2320 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2321 return X86::COND_A; 2322 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2323 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2324 return X86::COND_AE; 2325 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2326 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2327 return X86::COND_B; 2328 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2329 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2330 return X86::COND_BE; 2331 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2332 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2333 return X86::COND_E; 2334 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2335 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2336 return X86::COND_G; 2337 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2338 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2339 return X86::COND_GE; 2340 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2341 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2342 return X86::COND_L; 2343 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2344 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2345 return X86::COND_LE; 2346 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2347 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2348 return X86::COND_NE; 2349 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2350 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2351 return X86::COND_NO; 2352 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2353 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2354 return X86::COND_NP; 2355 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2356 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2357 return X86::COND_NS; 2358 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2359 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2360 return X86::COND_O; 2361 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2362 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2363 return X86::COND_P; 2364 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2365 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2366 return X86::COND_S; 2367 } 2368 } 2369 2370 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2371 switch (CC) { 2372 default: llvm_unreachable("Illegal condition code!"); 2373 case X86::COND_E: return X86::JE_4; 2374 case X86::COND_NE: return X86::JNE_4; 2375 case X86::COND_L: return X86::JL_4; 2376 case X86::COND_LE: return X86::JLE_4; 2377 case X86::COND_G: return X86::JG_4; 2378 case X86::COND_GE: return X86::JGE_4; 2379 case X86::COND_B: return X86::JB_4; 2380 case X86::COND_BE: return X86::JBE_4; 2381 case X86::COND_A: return X86::JA_4; 2382 case X86::COND_AE: return X86::JAE_4; 2383 case X86::COND_S: return X86::JS_4; 2384 case X86::COND_NS: return X86::JNS_4; 2385 case X86::COND_P: return X86::JP_4; 2386 case X86::COND_NP: return X86::JNP_4; 2387 case X86::COND_O: return X86::JO_4; 2388 case X86::COND_NO: return X86::JNO_4; 2389 } 2390 } 2391 2392 /// GetOppositeBranchCondition - Return the inverse of the specified condition, 2393 /// e.g. turning COND_E to COND_NE. 2394 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2395 switch (CC) { 2396 default: llvm_unreachable("Illegal condition code!"); 2397 case X86::COND_E: return X86::COND_NE; 2398 case X86::COND_NE: return X86::COND_E; 2399 case X86::COND_L: return X86::COND_GE; 2400 case X86::COND_LE: return X86::COND_G; 2401 case X86::COND_G: return X86::COND_LE; 2402 case X86::COND_GE: return X86::COND_L; 2403 case X86::COND_B: return X86::COND_AE; 2404 case X86::COND_BE: return X86::COND_A; 2405 case X86::COND_A: return X86::COND_BE; 2406 case X86::COND_AE: return X86::COND_B; 2407 case X86::COND_S: return X86::COND_NS; 2408 case X86::COND_NS: return X86::COND_S; 2409 case X86::COND_P: return X86::COND_NP; 2410 case X86::COND_NP: return X86::COND_P; 2411 case X86::COND_O: return X86::COND_NO; 2412 case X86::COND_NO: return X86::COND_O; 2413 } 2414 } 2415 2416 /// getSwappedCondition - assume the flags are set by MI(a,b), return 2417 /// the condition code if we modify the instructions such that flags are 2418 /// set by MI(b,a). 2419 static X86::CondCode getSwappedCondition(X86::CondCode CC) { 2420 switch (CC) { 2421 default: return X86::COND_INVALID; 2422 case X86::COND_E: return X86::COND_E; 2423 case X86::COND_NE: return X86::COND_NE; 2424 case X86::COND_L: return X86::COND_G; 2425 case X86::COND_LE: return X86::COND_GE; 2426 case X86::COND_G: return X86::COND_L; 2427 case X86::COND_GE: return X86::COND_LE; 2428 case X86::COND_B: return X86::COND_A; 2429 case X86::COND_BE: return X86::COND_AE; 2430 case X86::COND_A: return X86::COND_B; 2431 case X86::COND_AE: return X86::COND_BE; 2432 } 2433 } 2434 2435 /// getSETFromCond - Return a set opcode for the given condition and 2436 /// whether it has memory operand. 2437 static unsigned getSETFromCond(X86::CondCode CC, 2438 bool HasMemoryOperand) { 2439 static const uint16_t Opc[16][2] = { 2440 { X86::SETAr, X86::SETAm }, 2441 { X86::SETAEr, X86::SETAEm }, 2442 { X86::SETBr, X86::SETBm }, 2443 { X86::SETBEr, X86::SETBEm }, 2444 { X86::SETEr, X86::SETEm }, 2445 { X86::SETGr, X86::SETGm }, 2446 { X86::SETGEr, X86::SETGEm }, 2447 { X86::SETLr, X86::SETLm }, 2448 { X86::SETLEr, X86::SETLEm }, 2449 { X86::SETNEr, X86::SETNEm }, 2450 { X86::SETNOr, X86::SETNOm }, 2451 { X86::SETNPr, X86::SETNPm }, 2452 { X86::SETNSr, X86::SETNSm }, 2453 { X86::SETOr, X86::SETOm }, 2454 { X86::SETPr, X86::SETPm }, 2455 { X86::SETSr, X86::SETSm } 2456 }; 2457 2458 assert(CC < 16 && "Can only handle standard cond codes"); 2459 return Opc[CC][HasMemoryOperand ? 1 : 0]; 2460 } 2461 2462 /// getCMovFromCond - Return a cmov opcode for the given condition, 2463 /// register size in bytes, and operand type. 2464 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, 2465 bool HasMemoryOperand) { 2466 static const uint16_t Opc[32][3] = { 2467 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2468 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2469 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2470 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2471 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2472 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2473 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2474 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2475 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2476 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2477 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2478 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2479 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2480 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2481 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2482 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2483 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2484 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2485 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2486 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2487 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2488 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2489 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2490 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2491 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2492 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2493 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2494 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2495 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2496 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2497 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2498 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2499 }; 2500 2501 assert(CC < 16 && "Can only handle standard cond codes"); 2502 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2503 switch(RegBytes) { 2504 default: llvm_unreachable("Illegal register size!"); 2505 case 2: return Opc[Idx][0]; 2506 case 4: return Opc[Idx][1]; 2507 case 8: return Opc[Idx][2]; 2508 } 2509 } 2510 2511 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2512 if (!MI->isTerminator()) return false; 2513 2514 // Conditional branch is a special case. 2515 if (MI->isBranch() && !MI->isBarrier()) 2516 return true; 2517 if (!MI->isPredicable()) 2518 return true; 2519 return !isPredicated(MI); 2520 } 2521 2522 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2523 MachineBasicBlock *&TBB, 2524 MachineBasicBlock *&FBB, 2525 SmallVectorImpl<MachineOperand> &Cond, 2526 bool AllowModify) const { 2527 // Start from the bottom of the block and work up, examining the 2528 // terminator instructions. 2529 MachineBasicBlock::iterator I = MBB.end(); 2530 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2531 while (I != MBB.begin()) { 2532 --I; 2533 if (I->isDebugValue()) 2534 continue; 2535 2536 // Working from the bottom, when we see a non-terminator instruction, we're 2537 // done. 2538 if (!isUnpredicatedTerminator(I)) 2539 break; 2540 2541 // A terminator that isn't a branch can't easily be handled by this 2542 // analysis. 2543 if (!I->isBranch()) 2544 return true; 2545 2546 // Handle unconditional branches. 2547 if (I->getOpcode() == X86::JMP_4) { 2548 UnCondBrIter = I; 2549 2550 if (!AllowModify) { 2551 TBB = I->getOperand(0).getMBB(); 2552 continue; 2553 } 2554 2555 // If the block has any instructions after a JMP, delete them. 2556 while (llvm::next(I) != MBB.end()) 2557 llvm::next(I)->eraseFromParent(); 2558 2559 Cond.clear(); 2560 FBB = 0; 2561 2562 // Delete the JMP if it's equivalent to a fall-through. 2563 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 2564 TBB = 0; 2565 I->eraseFromParent(); 2566 I = MBB.end(); 2567 UnCondBrIter = MBB.end(); 2568 continue; 2569 } 2570 2571 // TBB is used to indicate the unconditional destination. 2572 TBB = I->getOperand(0).getMBB(); 2573 continue; 2574 } 2575 2576 // Handle conditional branches. 2577 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 2578 if (BranchCode == X86::COND_INVALID) 2579 return true; // Can't handle indirect branch. 2580 2581 // Working from the bottom, handle the first conditional branch. 2582 if (Cond.empty()) { 2583 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 2584 if (AllowModify && UnCondBrIter != MBB.end() && 2585 MBB.isLayoutSuccessor(TargetBB)) { 2586 // If we can modify the code and it ends in something like: 2587 // 2588 // jCC L1 2589 // jmp L2 2590 // L1: 2591 // ... 2592 // L2: 2593 // 2594 // Then we can change this to: 2595 // 2596 // jnCC L2 2597 // L1: 2598 // ... 2599 // L2: 2600 // 2601 // Which is a bit more efficient. 2602 // We conditionally jump to the fall-through block. 2603 BranchCode = GetOppositeBranchCondition(BranchCode); 2604 unsigned JNCC = GetCondBranchFromCond(BranchCode); 2605 MachineBasicBlock::iterator OldInst = I; 2606 2607 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 2608 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 2609 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 2610 .addMBB(TargetBB); 2611 2612 OldInst->eraseFromParent(); 2613 UnCondBrIter->eraseFromParent(); 2614 2615 // Restart the analysis. 2616 UnCondBrIter = MBB.end(); 2617 I = MBB.end(); 2618 continue; 2619 } 2620 2621 FBB = TBB; 2622 TBB = I->getOperand(0).getMBB(); 2623 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 2624 continue; 2625 } 2626 2627 // Handle subsequent conditional branches. Only handle the case where all 2628 // conditional branches branch to the same destination and their condition 2629 // opcodes fit one of the special multi-branch idioms. 2630 assert(Cond.size() == 1); 2631 assert(TBB); 2632 2633 // Only handle the case where all conditional branches branch to the same 2634 // destination. 2635 if (TBB != I->getOperand(0).getMBB()) 2636 return true; 2637 2638 // If the conditions are the same, we can leave them alone. 2639 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 2640 if (OldBranchCode == BranchCode) 2641 continue; 2642 2643 // If they differ, see if they fit one of the known patterns. Theoretically, 2644 // we could handle more patterns here, but we shouldn't expect to see them 2645 // if instruction selection has done a reasonable job. 2646 if ((OldBranchCode == X86::COND_NP && 2647 BranchCode == X86::COND_E) || 2648 (OldBranchCode == X86::COND_E && 2649 BranchCode == X86::COND_NP)) 2650 BranchCode = X86::COND_NP_OR_E; 2651 else if ((OldBranchCode == X86::COND_P && 2652 BranchCode == X86::COND_NE) || 2653 (OldBranchCode == X86::COND_NE && 2654 BranchCode == X86::COND_P)) 2655 BranchCode = X86::COND_NE_OR_P; 2656 else 2657 return true; 2658 2659 // Update the MachineOperand. 2660 Cond[0].setImm(BranchCode); 2661 } 2662 2663 return false; 2664 } 2665 2666 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 2667 MachineBasicBlock::iterator I = MBB.end(); 2668 unsigned Count = 0; 2669 2670 while (I != MBB.begin()) { 2671 --I; 2672 if (I->isDebugValue()) 2673 continue; 2674 if (I->getOpcode() != X86::JMP_4 && 2675 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 2676 break; 2677 // Remove the branch. 2678 I->eraseFromParent(); 2679 I = MBB.end(); 2680 ++Count; 2681 } 2682 2683 return Count; 2684 } 2685 2686 unsigned 2687 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2688 MachineBasicBlock *FBB, 2689 const SmallVectorImpl<MachineOperand> &Cond, 2690 DebugLoc DL) const { 2691 // Shouldn't be a fall through. 2692 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 2693 assert((Cond.size() == 1 || Cond.size() == 0) && 2694 "X86 branch conditions have one component!"); 2695 2696 if (Cond.empty()) { 2697 // Unconditional branch? 2698 assert(!FBB && "Unconditional branch with multiple successors!"); 2699 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 2700 return 1; 2701 } 2702 2703 // Conditional branch. 2704 unsigned Count = 0; 2705 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 2706 switch (CC) { 2707 case X86::COND_NP_OR_E: 2708 // Synthesize NP_OR_E with two branches. 2709 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 2710 ++Count; 2711 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 2712 ++Count; 2713 break; 2714 case X86::COND_NE_OR_P: 2715 // Synthesize NE_OR_P with two branches. 2716 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 2717 ++Count; 2718 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 2719 ++Count; 2720 break; 2721 default: { 2722 unsigned Opc = GetCondBranchFromCond(CC); 2723 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 2724 ++Count; 2725 } 2726 } 2727 if (FBB) { 2728 // Two-way Conditional branch. Insert the second branch. 2729 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 2730 ++Count; 2731 } 2732 return Count; 2733 } 2734 2735 bool X86InstrInfo:: 2736 canInsertSelect(const MachineBasicBlock &MBB, 2737 const SmallVectorImpl<MachineOperand> &Cond, 2738 unsigned TrueReg, unsigned FalseReg, 2739 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 2740 // Not all subtargets have cmov instructions. 2741 if (!TM.getSubtarget<X86Subtarget>().hasCMov()) 2742 return false; 2743 if (Cond.size() != 1) 2744 return false; 2745 // We cannot do the composite conditions, at least not in SSA form. 2746 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 2747 return false; 2748 2749 // Check register classes. 2750 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2751 const TargetRegisterClass *RC = 2752 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2753 if (!RC) 2754 return false; 2755 2756 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 2757 if (X86::GR16RegClass.hasSubClassEq(RC) || 2758 X86::GR32RegClass.hasSubClassEq(RC) || 2759 X86::GR64RegClass.hasSubClassEq(RC)) { 2760 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 2761 // Bridge. Probably Ivy Bridge as well. 2762 CondCycles = 2; 2763 TrueCycles = 2; 2764 FalseCycles = 2; 2765 return true; 2766 } 2767 2768 // Can't do vectors. 2769 return false; 2770 } 2771 2772 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 2773 MachineBasicBlock::iterator I, DebugLoc DL, 2774 unsigned DstReg, 2775 const SmallVectorImpl<MachineOperand> &Cond, 2776 unsigned TrueReg, unsigned FalseReg) const { 2777 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2778 assert(Cond.size() == 1 && "Invalid Cond array"); 2779 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 2780 MRI.getRegClass(DstReg)->getSize(), 2781 false/*HasMemoryOperand*/); 2782 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 2783 } 2784 2785 /// isHReg - Test if the given register is a physical h register. 2786 static bool isHReg(unsigned Reg) { 2787 return X86::GR8_ABCD_HRegClass.contains(Reg); 2788 } 2789 2790 // Try and copy between VR128/VR64 and GR64 registers. 2791 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 2792 bool HasAVX) { 2793 // SrcReg(VR128) -> DestReg(GR64) 2794 // SrcReg(VR64) -> DestReg(GR64) 2795 // SrcReg(GR64) -> DestReg(VR128) 2796 // SrcReg(GR64) -> DestReg(VR64) 2797 2798 if (X86::GR64RegClass.contains(DestReg)) { 2799 if (X86::VR128RegClass.contains(SrcReg)) 2800 // Copy from a VR128 register to a GR64 register. 2801 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr; 2802 if (X86::VR64RegClass.contains(SrcReg)) 2803 // Copy from a VR64 register to a GR64 register. 2804 return X86::MOVSDto64rr; 2805 } else if (X86::GR64RegClass.contains(SrcReg)) { 2806 // Copy from a GR64 register to a VR128 register. 2807 if (X86::VR128RegClass.contains(DestReg)) 2808 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr; 2809 // Copy from a GR64 register to a VR64 register. 2810 if (X86::VR64RegClass.contains(DestReg)) 2811 return X86::MOV64toSDrr; 2812 } 2813 2814 // SrcReg(FR32) -> DestReg(GR32) 2815 // SrcReg(GR32) -> DestReg(FR32) 2816 2817 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg)) 2818 // Copy from a FR32 register to a GR32 register. 2819 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr; 2820 2821 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 2822 // Copy from a GR32 register to a FR32 register. 2823 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr; 2824 2825 return 0; 2826 } 2827 2828 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 2829 MachineBasicBlock::iterator MI, DebugLoc DL, 2830 unsigned DestReg, unsigned SrcReg, 2831 bool KillSrc) const { 2832 // First deal with the normal symmetric copies. 2833 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2834 unsigned Opc; 2835 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 2836 Opc = X86::MOV64rr; 2837 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 2838 Opc = X86::MOV32rr; 2839 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 2840 Opc = X86::MOV16rr; 2841 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 2842 // Copying to or from a physical H register on x86-64 requires a NOREX 2843 // move. Otherwise use a normal move. 2844 if ((isHReg(DestReg) || isHReg(SrcReg)) && 2845 TM.getSubtarget<X86Subtarget>().is64Bit()) { 2846 Opc = X86::MOV8rr_NOREX; 2847 // Both operands must be encodable without an REX prefix. 2848 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 2849 "8-bit H register can not be copied outside GR8_NOREX"); 2850 } else 2851 Opc = X86::MOV8rr; 2852 } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 2853 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 2854 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 2855 Opc = X86::VMOVAPSYrr; 2856 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 2857 Opc = X86::MMX_MOVQ64rr; 2858 else 2859 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX); 2860 2861 if (Opc) { 2862 BuildMI(MBB, MI, DL, get(Opc), DestReg) 2863 .addReg(SrcReg, getKillRegState(KillSrc)); 2864 return; 2865 } 2866 2867 // Moving EFLAGS to / from another register requires a push and a pop. 2868 // Notice that we have to adjust the stack if we don't want to clobber the 2869 // first frame index. See X86FrameLowering.cpp - colobbersTheStack. 2870 if (SrcReg == X86::EFLAGS) { 2871 if (X86::GR64RegClass.contains(DestReg)) { 2872 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 2873 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 2874 return; 2875 } 2876 if (X86::GR32RegClass.contains(DestReg)) { 2877 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 2878 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 2879 return; 2880 } 2881 } 2882 if (DestReg == X86::EFLAGS) { 2883 if (X86::GR64RegClass.contains(SrcReg)) { 2884 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 2885 .addReg(SrcReg, getKillRegState(KillSrc)); 2886 BuildMI(MBB, MI, DL, get(X86::POPF64)); 2887 return; 2888 } 2889 if (X86::GR32RegClass.contains(SrcReg)) { 2890 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 2891 .addReg(SrcReg, getKillRegState(KillSrc)); 2892 BuildMI(MBB, MI, DL, get(X86::POPF32)); 2893 return; 2894 } 2895 } 2896 2897 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 2898 << " to " << RI.getName(DestReg) << '\n'); 2899 llvm_unreachable("Cannot emit physreg copy instruction"); 2900 } 2901 2902 static unsigned getLoadStoreRegOpcode(unsigned Reg, 2903 const TargetRegisterClass *RC, 2904 bool isStackAligned, 2905 const TargetMachine &TM, 2906 bool load) { 2907 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2908 switch (RC->getSize()) { 2909 default: 2910 llvm_unreachable("Unknown spill size"); 2911 case 1: 2912 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 2913 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2914 // Copying to or from a physical H register on x86-64 requires a NOREX 2915 // move. Otherwise use a normal move. 2916 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 2917 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2918 return load ? X86::MOV8rm : X86::MOV8mr; 2919 case 2: 2920 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 2921 return load ? X86::MOV16rm : X86::MOV16mr; 2922 case 4: 2923 if (X86::GR32RegClass.hasSubClassEq(RC)) 2924 return load ? X86::MOV32rm : X86::MOV32mr; 2925 if (X86::FR32RegClass.hasSubClassEq(RC)) 2926 return load ? 2927 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 2928 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 2929 if (X86::RFP32RegClass.hasSubClassEq(RC)) 2930 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 2931 llvm_unreachable("Unknown 4-byte regclass"); 2932 case 8: 2933 if (X86::GR64RegClass.hasSubClassEq(RC)) 2934 return load ? X86::MOV64rm : X86::MOV64mr; 2935 if (X86::FR64RegClass.hasSubClassEq(RC)) 2936 return load ? 2937 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 2938 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 2939 if (X86::VR64RegClass.hasSubClassEq(RC)) 2940 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 2941 if (X86::RFP64RegClass.hasSubClassEq(RC)) 2942 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 2943 llvm_unreachable("Unknown 8-byte regclass"); 2944 case 10: 2945 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 2946 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 2947 case 16: { 2948 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); 2949 // If stack is realigned we can use aligned stores. 2950 if (isStackAligned) 2951 return load ? 2952 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 2953 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 2954 else 2955 return load ? 2956 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 2957 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 2958 } 2959 case 32: 2960 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); 2961 // If stack is realigned we can use aligned stores. 2962 if (isStackAligned) 2963 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 2964 else 2965 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 2966 } 2967 } 2968 2969 static unsigned getStoreRegOpcode(unsigned SrcReg, 2970 const TargetRegisterClass *RC, 2971 bool isStackAligned, 2972 TargetMachine &TM) { 2973 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 2974 } 2975 2976 2977 static unsigned getLoadRegOpcode(unsigned DestReg, 2978 const TargetRegisterClass *RC, 2979 bool isStackAligned, 2980 const TargetMachine &TM) { 2981 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 2982 } 2983 2984 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2985 MachineBasicBlock::iterator MI, 2986 unsigned SrcReg, bool isKill, int FrameIdx, 2987 const TargetRegisterClass *RC, 2988 const TargetRegisterInfo *TRI) const { 2989 const MachineFunction &MF = *MBB.getParent(); 2990 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 2991 "Stack slot too small for store"); 2992 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2993 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 2994 RI.canRealignStack(MF); 2995 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2996 DebugLoc DL = MBB.findDebugLoc(MI); 2997 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2998 .addReg(SrcReg, getKillRegState(isKill)); 2999 } 3000 3001 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 3002 bool isKill, 3003 SmallVectorImpl<MachineOperand> &Addr, 3004 const TargetRegisterClass *RC, 3005 MachineInstr::mmo_iterator MMOBegin, 3006 MachineInstr::mmo_iterator MMOEnd, 3007 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3008 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3009 bool isAligned = MMOBegin != MMOEnd && 3010 (*MMOBegin)->getAlignment() >= Alignment; 3011 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 3012 DebugLoc DL; 3013 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 3014 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3015 MIB.addOperand(Addr[i]); 3016 MIB.addReg(SrcReg, getKillRegState(isKill)); 3017 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3018 NewMIs.push_back(MIB); 3019 } 3020 3021 3022 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 3023 MachineBasicBlock::iterator MI, 3024 unsigned DestReg, int FrameIdx, 3025 const TargetRegisterClass *RC, 3026 const TargetRegisterInfo *TRI) const { 3027 const MachineFunction &MF = *MBB.getParent(); 3028 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3029 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 3030 RI.canRealignStack(MF); 3031 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3032 DebugLoc DL = MBB.findDebugLoc(MI); 3033 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 3034 } 3035 3036 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 3037 SmallVectorImpl<MachineOperand> &Addr, 3038 const TargetRegisterClass *RC, 3039 MachineInstr::mmo_iterator MMOBegin, 3040 MachineInstr::mmo_iterator MMOEnd, 3041 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3042 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3043 bool isAligned = MMOBegin != MMOEnd && 3044 (*MMOBegin)->getAlignment() >= Alignment; 3045 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3046 DebugLoc DL; 3047 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 3048 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3049 MIB.addOperand(Addr[i]); 3050 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3051 NewMIs.push_back(MIB); 3052 } 3053 3054 bool X86InstrInfo:: 3055 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 3056 int &CmpMask, int &CmpValue) const { 3057 switch (MI->getOpcode()) { 3058 default: break; 3059 case X86::CMP64ri32: 3060 case X86::CMP64ri8: 3061 case X86::CMP32ri: 3062 case X86::CMP32ri8: 3063 case X86::CMP16ri: 3064 case X86::CMP16ri8: 3065 case X86::CMP8ri: 3066 SrcReg = MI->getOperand(0).getReg(); 3067 SrcReg2 = 0; 3068 CmpMask = ~0; 3069 CmpValue = MI->getOperand(1).getImm(); 3070 return true; 3071 // A SUB can be used to perform comparison. 3072 case X86::SUB64rm: 3073 case X86::SUB32rm: 3074 case X86::SUB16rm: 3075 case X86::SUB8rm: 3076 SrcReg = MI->getOperand(1).getReg(); 3077 SrcReg2 = 0; 3078 CmpMask = ~0; 3079 CmpValue = 0; 3080 return true; 3081 case X86::SUB64rr: 3082 case X86::SUB32rr: 3083 case X86::SUB16rr: 3084 case X86::SUB8rr: 3085 SrcReg = MI->getOperand(1).getReg(); 3086 SrcReg2 = MI->getOperand(2).getReg(); 3087 CmpMask = ~0; 3088 CmpValue = 0; 3089 return true; 3090 case X86::SUB64ri32: 3091 case X86::SUB64ri8: 3092 case X86::SUB32ri: 3093 case X86::SUB32ri8: 3094 case X86::SUB16ri: 3095 case X86::SUB16ri8: 3096 case X86::SUB8ri: 3097 SrcReg = MI->getOperand(1).getReg(); 3098 SrcReg2 = 0; 3099 CmpMask = ~0; 3100 CmpValue = MI->getOperand(2).getImm(); 3101 return true; 3102 case X86::CMP64rr: 3103 case X86::CMP32rr: 3104 case X86::CMP16rr: 3105 case X86::CMP8rr: 3106 SrcReg = MI->getOperand(0).getReg(); 3107 SrcReg2 = MI->getOperand(1).getReg(); 3108 CmpMask = ~0; 3109 CmpValue = 0; 3110 return true; 3111 case X86::TEST8rr: 3112 case X86::TEST16rr: 3113 case X86::TEST32rr: 3114 case X86::TEST64rr: 3115 SrcReg = MI->getOperand(0).getReg(); 3116 if (MI->getOperand(1).getReg() != SrcReg) return false; 3117 // Compare against zero. 3118 SrcReg2 = 0; 3119 CmpMask = ~0; 3120 CmpValue = 0; 3121 return true; 3122 } 3123 return false; 3124 } 3125 3126 /// isRedundantFlagInstr - check whether the first instruction, whose only 3127 /// purpose is to update flags, can be made redundant. 3128 /// CMPrr can be made redundant by SUBrr if the operands are the same. 3129 /// This function can be extended later on. 3130 /// SrcReg, SrcRegs: register operands for FlagI. 3131 /// ImmValue: immediate for FlagI if it takes an immediate. 3132 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3133 unsigned SrcReg2, int ImmValue, 3134 MachineInstr *OI) { 3135 if (((FlagI->getOpcode() == X86::CMP64rr && 3136 OI->getOpcode() == X86::SUB64rr) || 3137 (FlagI->getOpcode() == X86::CMP32rr && 3138 OI->getOpcode() == X86::SUB32rr)|| 3139 (FlagI->getOpcode() == X86::CMP16rr && 3140 OI->getOpcode() == X86::SUB16rr)|| 3141 (FlagI->getOpcode() == X86::CMP8rr && 3142 OI->getOpcode() == X86::SUB8rr)) && 3143 ((OI->getOperand(1).getReg() == SrcReg && 3144 OI->getOperand(2).getReg() == SrcReg2) || 3145 (OI->getOperand(1).getReg() == SrcReg2 && 3146 OI->getOperand(2).getReg() == SrcReg))) 3147 return true; 3148 3149 if (((FlagI->getOpcode() == X86::CMP64ri32 && 3150 OI->getOpcode() == X86::SUB64ri32) || 3151 (FlagI->getOpcode() == X86::CMP64ri8 && 3152 OI->getOpcode() == X86::SUB64ri8) || 3153 (FlagI->getOpcode() == X86::CMP32ri && 3154 OI->getOpcode() == X86::SUB32ri) || 3155 (FlagI->getOpcode() == X86::CMP32ri8 && 3156 OI->getOpcode() == X86::SUB32ri8) || 3157 (FlagI->getOpcode() == X86::CMP16ri && 3158 OI->getOpcode() == X86::SUB16ri) || 3159 (FlagI->getOpcode() == X86::CMP16ri8 && 3160 OI->getOpcode() == X86::SUB16ri8) || 3161 (FlagI->getOpcode() == X86::CMP8ri && 3162 OI->getOpcode() == X86::SUB8ri)) && 3163 OI->getOperand(1).getReg() == SrcReg && 3164 OI->getOperand(2).getImm() == ImmValue) 3165 return true; 3166 return false; 3167 } 3168 3169 /// isDefConvertible - check whether the definition can be converted 3170 /// to remove a comparison against zero. 3171 inline static bool isDefConvertible(MachineInstr *MI) { 3172 switch (MI->getOpcode()) { 3173 default: return false; 3174 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3175 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3176 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3177 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3178 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3179 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 3180 case X86::DEC64_32r: case X86::DEC64_16r: 3181 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3182 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3183 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3184 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3185 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3186 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 3187 case X86::INC64_32r: case X86::INC64_16r: 3188 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3189 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3190 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3191 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3192 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3193 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3194 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3195 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3196 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3197 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3198 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3199 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3200 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3201 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3202 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3203 case X86::ANDN32rr: case X86::ANDN32rm: 3204 case X86::ANDN64rr: case X86::ANDN64rm: 3205 return true; 3206 } 3207 } 3208 3209 /// optimizeCompareInstr - Check if there exists an earlier instruction that 3210 /// operates on the same source operands and sets flags in the same way as 3211 /// Compare; remove Compare if possible. 3212 bool X86InstrInfo:: 3213 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3214 int CmpMask, int CmpValue, 3215 const MachineRegisterInfo *MRI) const { 3216 // Check whether we can replace SUB with CMP. 3217 unsigned NewOpcode = 0; 3218 switch (CmpInstr->getOpcode()) { 3219 default: break; 3220 case X86::SUB64ri32: 3221 case X86::SUB64ri8: 3222 case X86::SUB32ri: 3223 case X86::SUB32ri8: 3224 case X86::SUB16ri: 3225 case X86::SUB16ri8: 3226 case X86::SUB8ri: 3227 case X86::SUB64rm: 3228 case X86::SUB32rm: 3229 case X86::SUB16rm: 3230 case X86::SUB8rm: 3231 case X86::SUB64rr: 3232 case X86::SUB32rr: 3233 case X86::SUB16rr: 3234 case X86::SUB8rr: { 3235 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3236 return false; 3237 // There is no use of the destination register, we can replace SUB with CMP. 3238 switch (CmpInstr->getOpcode()) { 3239 default: llvm_unreachable("Unreachable!"); 3240 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3241 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3242 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3243 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3244 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3245 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3246 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3247 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3248 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3249 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3250 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3251 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3252 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3253 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3254 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3255 } 3256 CmpInstr->setDesc(get(NewOpcode)); 3257 CmpInstr->RemoveOperand(0); 3258 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3259 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3260 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3261 return false; 3262 } 3263 } 3264 3265 // Get the unique definition of SrcReg. 3266 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3267 if (!MI) return false; 3268 3269 // CmpInstr is the first instruction of the BB. 3270 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3271 3272 // If we are comparing against zero, check whether we can use MI to update 3273 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3274 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3275 if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() || 3276 !isDefConvertible(MI))) 3277 return false; 3278 3279 // We are searching for an earlier instruction that can make CmpInstr 3280 // redundant and that instruction will be saved in Sub. 3281 MachineInstr *Sub = NULL; 3282 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3283 3284 // We iterate backward, starting from the instruction before CmpInstr and 3285 // stop when reaching the definition of a source register or done with the BB. 3286 // RI points to the instruction before CmpInstr. 3287 // If the definition is in this basic block, RE points to the definition; 3288 // otherwise, RE is the rend of the basic block. 3289 MachineBasicBlock::reverse_iterator 3290 RI = MachineBasicBlock::reverse_iterator(I), 3291 RE = CmpInstr->getParent() == MI->getParent() ? 3292 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3293 CmpInstr->getParent()->rend(); 3294 MachineInstr *Movr0Inst = 0; 3295 for (; RI != RE; ++RI) { 3296 MachineInstr *Instr = &*RI; 3297 // Check whether CmpInstr can be made redundant by the current instruction. 3298 if (!IsCmpZero && 3299 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3300 Sub = Instr; 3301 break; 3302 } 3303 3304 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3305 Instr->readsRegister(X86::EFLAGS, TRI)) { 3306 // This instruction modifies or uses EFLAGS. 3307 3308 // MOV32r0 etc. are implemented with xor which clobbers condition code. 3309 // They are safe to move up, if the definition to EFLAGS is dead and 3310 // earlier instructions do not read or write EFLAGS. 3311 if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 || 3312 Instr->getOpcode() == X86::MOV16r0 || 3313 Instr->getOpcode() == X86::MOV32r0 || 3314 Instr->getOpcode() == X86::MOV64r0) && 3315 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3316 Movr0Inst = Instr; 3317 continue; 3318 } 3319 3320 // We can't remove CmpInstr. 3321 return false; 3322 } 3323 } 3324 3325 // Return false if no candidates exist. 3326 if (!IsCmpZero && !Sub) 3327 return false; 3328 3329 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3330 Sub->getOperand(2).getReg() == SrcReg); 3331 3332 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3333 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3334 // If we are done with the basic block, we need to check whether EFLAGS is 3335 // live-out. 3336 bool IsSafe = false; 3337 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3338 MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3339 for (++I; I != E; ++I) { 3340 const MachineInstr &Instr = *I; 3341 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3342 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3343 // We should check the usage if this instruction uses and updates EFLAGS. 3344 if (!UseEFLAGS && ModifyEFLAGS) { 3345 // It is safe to remove CmpInstr if EFLAGS is updated again. 3346 IsSafe = true; 3347 break; 3348 } 3349 if (!UseEFLAGS && !ModifyEFLAGS) 3350 continue; 3351 3352 // EFLAGS is used by this instruction. 3353 X86::CondCode OldCC; 3354 bool OpcIsSET = false; 3355 if (IsCmpZero || IsSwapped) { 3356 // We decode the condition code from opcode. 3357 if (Instr.isBranch()) 3358 OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3359 else { 3360 OldCC = getCondFromSETOpc(Instr.getOpcode()); 3361 if (OldCC != X86::COND_INVALID) 3362 OpcIsSET = true; 3363 else 3364 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 3365 } 3366 if (OldCC == X86::COND_INVALID) return false; 3367 } 3368 if (IsCmpZero) { 3369 switch (OldCC) { 3370 default: break; 3371 case X86::COND_A: case X86::COND_AE: 3372 case X86::COND_B: case X86::COND_BE: 3373 case X86::COND_G: case X86::COND_GE: 3374 case X86::COND_L: case X86::COND_LE: 3375 case X86::COND_O: case X86::COND_NO: 3376 // CF and OF are used, we can't perform this optimization. 3377 return false; 3378 } 3379 } else if (IsSwapped) { 3380 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3381 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3382 // We swap the condition code and synthesize the new opcode. 3383 X86::CondCode NewCC = getSwappedCondition(OldCC); 3384 if (NewCC == X86::COND_INVALID) return false; 3385 3386 // Synthesize the new opcode. 3387 bool HasMemoryOperand = Instr.hasOneMemOperand(); 3388 unsigned NewOpc; 3389 if (Instr.isBranch()) 3390 NewOpc = GetCondBranchFromCond(NewCC); 3391 else if(OpcIsSET) 3392 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3393 else { 3394 unsigned DstReg = Instr.getOperand(0).getReg(); 3395 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3396 HasMemoryOperand); 3397 } 3398 3399 // Push the MachineInstr to OpsToUpdate. 3400 // If it is safe to remove CmpInstr, the condition code of these 3401 // instructions will be modified. 3402 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3403 } 3404 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 3405 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 3406 IsSafe = true; 3407 break; 3408 } 3409 } 3410 3411 // If EFLAGS is not killed nor re-defined, we should check whether it is 3412 // live-out. If it is live-out, do not optimize. 3413 if ((IsCmpZero || IsSwapped) && !IsSafe) { 3414 MachineBasicBlock *MBB = CmpInstr->getParent(); 3415 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 3416 SE = MBB->succ_end(); SI != SE; ++SI) 3417 if ((*SI)->isLiveIn(X86::EFLAGS)) 3418 return false; 3419 } 3420 3421 // The instruction to be updated is either Sub or MI. 3422 Sub = IsCmpZero ? MI : Sub; 3423 // Move Movr0Inst to the place right before Sub. 3424 if (Movr0Inst) { 3425 Sub->getParent()->remove(Movr0Inst); 3426 Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst); 3427 } 3428 3429 // Make sure Sub instruction defines EFLAGS and mark the def live. 3430 unsigned LastOperand = Sub->getNumOperands() - 1; 3431 assert(Sub->getNumOperands() >= 2 && 3432 Sub->getOperand(LastOperand).isReg() && 3433 Sub->getOperand(LastOperand).getReg() == X86::EFLAGS && 3434 "EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND"); 3435 Sub->getOperand(LastOperand).setIsDef(true); 3436 Sub->getOperand(LastOperand).setIsDead(false); 3437 CmpInstr->eraseFromParent(); 3438 3439 // Modify the condition code of instructions in OpsToUpdate. 3440 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 3441 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 3442 return true; 3443 } 3444 3445 /// optimizeLoadInstr - Try to remove the load by folding it to a register 3446 /// operand at the use. We fold the load instructions if load defines a virtual 3447 /// register, the virtual register is used once in the same BB, and the 3448 /// instructions in-between do not load or store, and have no side effects. 3449 MachineInstr* X86InstrInfo:: 3450 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, 3451 unsigned &FoldAsLoadDefReg, 3452 MachineInstr *&DefMI) const { 3453 if (FoldAsLoadDefReg == 0) 3454 return 0; 3455 // To be conservative, if there exists another load, clear the load candidate. 3456 if (MI->mayLoad()) { 3457 FoldAsLoadDefReg = 0; 3458 return 0; 3459 } 3460 3461 // Check whether we can move DefMI here. 3462 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3463 assert(DefMI); 3464 bool SawStore = false; 3465 if (!DefMI->isSafeToMove(this, 0, SawStore)) 3466 return 0; 3467 3468 // We try to commute MI if possible. 3469 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1; 3470 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) { 3471 // Collect information about virtual register operands of MI. 3472 unsigned SrcOperandId = 0; 3473 bool FoundSrcOperand = false; 3474 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 3475 MachineOperand &MO = MI->getOperand(i); 3476 if (!MO.isReg()) 3477 continue; 3478 unsigned Reg = MO.getReg(); 3479 if (Reg != FoldAsLoadDefReg) 3480 continue; 3481 // Do not fold if we have a subreg use or a def or multiple uses. 3482 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 3483 return 0; 3484 3485 SrcOperandId = i; 3486 FoundSrcOperand = true; 3487 } 3488 if (!FoundSrcOperand) return 0; 3489 3490 // Check whether we can fold the def into SrcOperandId. 3491 SmallVector<unsigned, 8> Ops; 3492 Ops.push_back(SrcOperandId); 3493 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 3494 if (FoldMI) { 3495 FoldAsLoadDefReg = 0; 3496 return FoldMI; 3497 } 3498 3499 if (Idx == 1) { 3500 // MI was changed but it didn't help, commute it back! 3501 commuteInstruction(MI, false); 3502 return 0; 3503 } 3504 3505 // Check whether we can commute MI and enable folding. 3506 if (MI->isCommutable()) { 3507 MachineInstr *NewMI = commuteInstruction(MI, false); 3508 // Unable to commute. 3509 if (!NewMI) return 0; 3510 if (NewMI != MI) { 3511 // New instruction. It doesn't need to be kept. 3512 NewMI->eraseFromParent(); 3513 return 0; 3514 } 3515 } 3516 } 3517 return 0; 3518 } 3519 3520 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 3521 /// instruction with two undef reads of the register being defined. This is 3522 /// used for mapping: 3523 /// %xmm4 = V_SET0 3524 /// to: 3525 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 3526 /// 3527 static bool Expand2AddrUndef(MachineInstrBuilder &MIB, 3528 const MCInstrDesc &Desc) { 3529 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 3530 unsigned Reg = MIB->getOperand(0).getReg(); 3531 MIB->setDesc(Desc); 3532 3533 // MachineInstr::addOperand() will insert explicit operands before any 3534 // implicit operands. 3535 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3536 // But we don't trust that. 3537 assert(MIB->getOperand(1).getReg() == Reg && 3538 MIB->getOperand(2).getReg() == Reg && "Misplaced operand"); 3539 return true; 3540 } 3541 3542 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 3543 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3544 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 3545 switch (MI->getOpcode()) { 3546 case X86::SETB_C8r: 3547 return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 3548 case X86::SETB_C16r: 3549 return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 3550 case X86::SETB_C32r: 3551 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 3552 case X86::SETB_C64r: 3553 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 3554 case X86::V_SET0: 3555 case X86::FsFLD0SS: 3556 case X86::FsFLD0SD: 3557 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 3558 case X86::AVX_SET0: 3559 assert(HasAVX && "AVX not supported"); 3560 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr)); 3561 case X86::V_SETALLONES: 3562 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 3563 case X86::AVX2_SETALLONES: 3564 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 3565 case X86::TEST8ri_NOREX: 3566 MI->setDesc(get(X86::TEST8ri)); 3567 return true; 3568 } 3569 return false; 3570 } 3571 3572 MachineInstr* 3573 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 3574 int FrameIx, uint64_t Offset, 3575 const MDNode *MDPtr, 3576 DebugLoc DL) const { 3577 X86AddressMode AM; 3578 AM.BaseType = X86AddressMode::FrameIndexBase; 3579 AM.Base.FrameIndex = FrameIx; 3580 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 3581 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 3582 return &*MIB; 3583 } 3584 3585 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 3586 const SmallVectorImpl<MachineOperand> &MOs, 3587 MachineInstr *MI, 3588 const TargetInstrInfo &TII) { 3589 // Create the base instruction with the memory operand as the first part. 3590 // Omit the implicit operands, something BuildMI can't do. 3591 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3592 MI->getDebugLoc(), true); 3593 MachineInstrBuilder MIB(MF, NewMI); 3594 unsigned NumAddrOps = MOs.size(); 3595 for (unsigned i = 0; i != NumAddrOps; ++i) 3596 MIB.addOperand(MOs[i]); 3597 if (NumAddrOps < 4) // FrameIndex only 3598 addOffset(MIB, 0); 3599 3600 // Loop over the rest of the ri operands, converting them over. 3601 unsigned NumOps = MI->getDesc().getNumOperands()-2; 3602 for (unsigned i = 0; i != NumOps; ++i) { 3603 MachineOperand &MO = MI->getOperand(i+2); 3604 MIB.addOperand(MO); 3605 } 3606 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 3607 MachineOperand &MO = MI->getOperand(i); 3608 MIB.addOperand(MO); 3609 } 3610 return MIB; 3611 } 3612 3613 static MachineInstr *FuseInst(MachineFunction &MF, 3614 unsigned Opcode, unsigned OpNo, 3615 const SmallVectorImpl<MachineOperand> &MOs, 3616 MachineInstr *MI, const TargetInstrInfo &TII) { 3617 // Omit the implicit operands, something BuildMI can't do. 3618 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3619 MI->getDebugLoc(), true); 3620 MachineInstrBuilder MIB(MF, NewMI); 3621 3622 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3623 MachineOperand &MO = MI->getOperand(i); 3624 if (i == OpNo) { 3625 assert(MO.isReg() && "Expected to fold into reg operand!"); 3626 unsigned NumAddrOps = MOs.size(); 3627 for (unsigned i = 0; i != NumAddrOps; ++i) 3628 MIB.addOperand(MOs[i]); 3629 if (NumAddrOps < 4) // FrameIndex only 3630 addOffset(MIB, 0); 3631 } else { 3632 MIB.addOperand(MO); 3633 } 3634 } 3635 return MIB; 3636 } 3637 3638 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 3639 const SmallVectorImpl<MachineOperand> &MOs, 3640 MachineInstr *MI) { 3641 MachineFunction &MF = *MI->getParent()->getParent(); 3642 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 3643 3644 unsigned NumAddrOps = MOs.size(); 3645 for (unsigned i = 0; i != NumAddrOps; ++i) 3646 MIB.addOperand(MOs[i]); 3647 if (NumAddrOps < 4) // FrameIndex only 3648 addOffset(MIB, 0); 3649 return MIB.addImm(0); 3650 } 3651 3652 MachineInstr* 3653 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3654 MachineInstr *MI, unsigned i, 3655 const SmallVectorImpl<MachineOperand> &MOs, 3656 unsigned Size, unsigned Align) const { 3657 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 3658 bool isTwoAddrFold = false; 3659 unsigned NumOps = MI->getDesc().getNumOperands(); 3660 bool isTwoAddr = NumOps > 1 && 3661 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 3662 3663 // FIXME: AsmPrinter doesn't know how to handle 3664 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 3665 if (MI->getOpcode() == X86::ADD32ri && 3666 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 3667 return NULL; 3668 3669 MachineInstr *NewMI = NULL; 3670 // Folding a memory location into the two-address part of a two-address 3671 // instruction is different than folding it other places. It requires 3672 // replacing the *two* registers with the memory location. 3673 if (isTwoAddr && NumOps >= 2 && i < 2 && 3674 MI->getOperand(0).isReg() && 3675 MI->getOperand(1).isReg() && 3676 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 3677 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 3678 isTwoAddrFold = true; 3679 } else if (i == 0) { // If operand 0 3680 unsigned Opc = 0; 3681 switch (MI->getOpcode()) { 3682 default: break; 3683 case X86::MOV64r0: Opc = X86::MOV64mi32; break; 3684 case X86::MOV32r0: Opc = X86::MOV32mi; break; 3685 case X86::MOV16r0: Opc = X86::MOV16mi; break; 3686 case X86::MOV8r0: Opc = X86::MOV8mi; break; 3687 } 3688 if (Opc) 3689 NewMI = MakeM0Inst(*this, Opc, MOs, MI); 3690 if (NewMI) 3691 return NewMI; 3692 3693 OpcodeTablePtr = &RegOp2MemOpTable0; 3694 } else if (i == 1) { 3695 OpcodeTablePtr = &RegOp2MemOpTable1; 3696 } else if (i == 2) { 3697 OpcodeTablePtr = &RegOp2MemOpTable2; 3698 } else if (i == 3) { 3699 OpcodeTablePtr = &RegOp2MemOpTable3; 3700 } 3701 3702 // If table selected... 3703 if (OpcodeTablePtr) { 3704 // Find the Opcode to fuse 3705 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 3706 OpcodeTablePtr->find(MI->getOpcode()); 3707 if (I != OpcodeTablePtr->end()) { 3708 unsigned Opcode = I->second.first; 3709 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 3710 if (Align < MinAlign) 3711 return NULL; 3712 bool NarrowToMOV32rm = false; 3713 if (Size) { 3714 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 3715 if (Size < RCSize) { 3716 // Check if it's safe to fold the load. If the size of the object is 3717 // narrower than the load width, then it's not. 3718 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 3719 return NULL; 3720 // If this is a 64-bit load, but the spill slot is 32, then we can do 3721 // a 32-bit load which is implicitly zero-extended. This likely is due 3722 // to liveintervalanalysis remat'ing a load from stack slot. 3723 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 3724 return NULL; 3725 Opcode = X86::MOV32rm; 3726 NarrowToMOV32rm = true; 3727 } 3728 } 3729 3730 if (isTwoAddrFold) 3731 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 3732 else 3733 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 3734 3735 if (NarrowToMOV32rm) { 3736 // If this is the special case where we use a MOV32rm to load a 32-bit 3737 // value and zero-extend the top bits. Change the destination register 3738 // to a 32-bit one. 3739 unsigned DstReg = NewMI->getOperand(0).getReg(); 3740 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 3741 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 3742 X86::sub_32bit)); 3743 else 3744 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 3745 } 3746 return NewMI; 3747 } 3748 } 3749 3750 // No fusion 3751 if (PrintFailedFusing && !MI->isCopy()) 3752 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 3753 return NULL; 3754 } 3755 3756 /// hasPartialRegUpdate - Return true for all instructions that only update 3757 /// the first 32 or 64-bits of the destination register and leave the rest 3758 /// unmodified. This can be used to avoid folding loads if the instructions 3759 /// only update part of the destination register, and the non-updated part is 3760 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 3761 /// instructions breaks the partial register dependency and it can improve 3762 /// performance. e.g.: 3763 /// 3764 /// movss (%rdi), %xmm0 3765 /// cvtss2sd %xmm0, %xmm0 3766 /// 3767 /// Instead of 3768 /// cvtss2sd (%rdi), %xmm0 3769 /// 3770 /// FIXME: This should be turned into a TSFlags. 3771 /// 3772 static bool hasPartialRegUpdate(unsigned Opcode) { 3773 switch (Opcode) { 3774 case X86::CVTSI2SSrr: 3775 case X86::CVTSI2SS64rr: 3776 case X86::CVTSI2SDrr: 3777 case X86::CVTSI2SD64rr: 3778 case X86::CVTSD2SSrr: 3779 case X86::Int_CVTSD2SSrr: 3780 case X86::CVTSS2SDrr: 3781 case X86::Int_CVTSS2SDrr: 3782 case X86::RCPSSr: 3783 case X86::RCPSSr_Int: 3784 case X86::ROUNDSDr: 3785 case X86::ROUNDSDr_Int: 3786 case X86::ROUNDSSr: 3787 case X86::ROUNDSSr_Int: 3788 case X86::RSQRTSSr: 3789 case X86::RSQRTSSr_Int: 3790 case X86::SQRTSSr: 3791 case X86::SQRTSSr_Int: 3792 // AVX encoded versions 3793 case X86::VCVTSD2SSrr: 3794 case X86::Int_VCVTSD2SSrr: 3795 case X86::VCVTSS2SDrr: 3796 case X86::Int_VCVTSS2SDrr: 3797 case X86::VRCPSSr: 3798 case X86::VROUNDSDr: 3799 case X86::VROUNDSDr_Int: 3800 case X86::VROUNDSSr: 3801 case X86::VROUNDSSr_Int: 3802 case X86::VRSQRTSSr: 3803 case X86::VSQRTSSr: 3804 return true; 3805 } 3806 3807 return false; 3808 } 3809 3810 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 3811 /// instructions we would like before a partial register update. 3812 unsigned X86InstrInfo:: 3813 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 3814 const TargetRegisterInfo *TRI) const { 3815 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 3816 return 0; 3817 3818 // If MI is marked as reading Reg, the partial register update is wanted. 3819 const MachineOperand &MO = MI->getOperand(0); 3820 unsigned Reg = MO.getReg(); 3821 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 3822 if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 3823 return 0; 3824 } else { 3825 if (MI->readsRegister(Reg, TRI)) 3826 return 0; 3827 } 3828 3829 // If any of the preceding 16 instructions are reading Reg, insert a 3830 // dependency breaking instruction. The magic number is based on a few 3831 // Nehalem experiments. 3832 return 16; 3833 } 3834 3835 void X86InstrInfo:: 3836 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 3837 const TargetRegisterInfo *TRI) const { 3838 unsigned Reg = MI->getOperand(OpNum).getReg(); 3839 if (X86::VR128RegClass.contains(Reg)) { 3840 // These instructions are all floating point domain, so xorps is the best 3841 // choice. 3842 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3843 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 3844 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 3845 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3846 } else if (X86::VR256RegClass.contains(Reg)) { 3847 // Use vxorps to clear the full ymm register. 3848 // It wants to read and write the xmm sub-register. 3849 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 3850 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 3851 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 3852 .addReg(Reg, RegState::ImplicitDefine); 3853 } else 3854 return; 3855 MI->addRegisterKilled(Reg, TRI, true); 3856 } 3857 3858 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3859 MachineInstr *MI, 3860 const SmallVectorImpl<unsigned> &Ops, 3861 int FrameIndex) const { 3862 // Check switch flag 3863 if (NoFusing) return NULL; 3864 3865 // Unless optimizing for size, don't fold to avoid partial 3866 // register update stalls 3867 if (!MF.getFunction()->getAttributes(). 3868 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 3869 hasPartialRegUpdate(MI->getOpcode())) 3870 return 0; 3871 3872 const MachineFrameInfo *MFI = MF.getFrameInfo(); 3873 unsigned Size = MFI->getObjectSize(FrameIndex); 3874 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 3875 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3876 unsigned NewOpc = 0; 3877 unsigned RCSize = 0; 3878 switch (MI->getOpcode()) { 3879 default: return NULL; 3880 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 3881 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 3882 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 3883 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 3884 } 3885 // Check if it's safe to fold the load. If the size of the object is 3886 // narrower than the load width, then it's not. 3887 if (Size < RCSize) 3888 return NULL; 3889 // Change to CMPXXri r, 0 first. 3890 MI->setDesc(get(NewOpc)); 3891 MI->getOperand(1).ChangeToImmediate(0); 3892 } else if (Ops.size() != 1) 3893 return NULL; 3894 3895 SmallVector<MachineOperand,4> MOs; 3896 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 3897 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 3898 } 3899 3900 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3901 MachineInstr *MI, 3902 const SmallVectorImpl<unsigned> &Ops, 3903 MachineInstr *LoadMI) const { 3904 // Check switch flag 3905 if (NoFusing) return NULL; 3906 3907 // Unless optimizing for size, don't fold to avoid partial 3908 // register update stalls 3909 if (!MF.getFunction()->getAttributes(). 3910 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 3911 hasPartialRegUpdate(MI->getOpcode())) 3912 return 0; 3913 3914 // Determine the alignment of the load. 3915 unsigned Alignment = 0; 3916 if (LoadMI->hasOneMemOperand()) 3917 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 3918 else 3919 switch (LoadMI->getOpcode()) { 3920 case X86::AVX2_SETALLONES: 3921 case X86::AVX_SET0: 3922 Alignment = 32; 3923 break; 3924 case X86::V_SET0: 3925 case X86::V_SETALLONES: 3926 Alignment = 16; 3927 break; 3928 case X86::FsFLD0SD: 3929 Alignment = 8; 3930 break; 3931 case X86::FsFLD0SS: 3932 Alignment = 4; 3933 break; 3934 default: 3935 return 0; 3936 } 3937 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3938 unsigned NewOpc = 0; 3939 switch (MI->getOpcode()) { 3940 default: return NULL; 3941 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 3942 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 3943 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 3944 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 3945 } 3946 // Change to CMPXXri r, 0 first. 3947 MI->setDesc(get(NewOpc)); 3948 MI->getOperand(1).ChangeToImmediate(0); 3949 } else if (Ops.size() != 1) 3950 return NULL; 3951 3952 // Make sure the subregisters match. 3953 // Otherwise we risk changing the size of the load. 3954 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 3955 return NULL; 3956 3957 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 3958 switch (LoadMI->getOpcode()) { 3959 case X86::V_SET0: 3960 case X86::V_SETALLONES: 3961 case X86::AVX2_SETALLONES: 3962 case X86::AVX_SET0: 3963 case X86::FsFLD0SD: 3964 case X86::FsFLD0SS: { 3965 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 3966 // Create a constant-pool entry and operands to load from it. 3967 3968 // Medium and large mode can't fold loads this way. 3969 if (TM.getCodeModel() != CodeModel::Small && 3970 TM.getCodeModel() != CodeModel::Kernel) 3971 return NULL; 3972 3973 // x86-32 PIC requires a PIC base register for constant pools. 3974 unsigned PICBase = 0; 3975 if (TM.getRelocationModel() == Reloc::PIC_) { 3976 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 3977 PICBase = X86::RIP; 3978 else 3979 // FIXME: PICBase = getGlobalBaseReg(&MF); 3980 // This doesn't work for several reasons. 3981 // 1. GlobalBaseReg may have been spilled. 3982 // 2. It may not be live at MI. 3983 return NULL; 3984 } 3985 3986 // Create a constant-pool entry. 3987 MachineConstantPool &MCP = *MF.getConstantPool(); 3988 Type *Ty; 3989 unsigned Opc = LoadMI->getOpcode(); 3990 if (Opc == X86::FsFLD0SS) 3991 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 3992 else if (Opc == X86::FsFLD0SD) 3993 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 3994 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 3995 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 3996 else 3997 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 3998 3999 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 4000 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 4001 Constant::getNullValue(Ty); 4002 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 4003 4004 // Create operands to load from the constant pool entry. 4005 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 4006 MOs.push_back(MachineOperand::CreateImm(1)); 4007 MOs.push_back(MachineOperand::CreateReg(0, false)); 4008 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 4009 MOs.push_back(MachineOperand::CreateReg(0, false)); 4010 break; 4011 } 4012 default: { 4013 if ((LoadMI->getOpcode() == X86::MOVSSrm || 4014 LoadMI->getOpcode() == X86::VMOVSSrm) && 4015 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4016 > 4) 4017 // These instructions only load 32 bits, we can't fold them if the 4018 // destination register is wider than 32 bits (4 bytes). 4019 return NULL; 4020 if ((LoadMI->getOpcode() == X86::MOVSDrm || 4021 LoadMI->getOpcode() == X86::VMOVSDrm) && 4022 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4023 > 8) 4024 // These instructions only load 64 bits, we can't fold them if the 4025 // destination register is wider than 64 bits (8 bytes). 4026 return NULL; 4027 4028 // Folding a normal load. Just copy the load's address operands. 4029 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 4030 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 4031 MOs.push_back(LoadMI->getOperand(i)); 4032 break; 4033 } 4034 } 4035 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 4036 } 4037 4038 4039 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 4040 const SmallVectorImpl<unsigned> &Ops) const { 4041 // Check switch flag 4042 if (NoFusing) return 0; 4043 4044 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4045 switch (MI->getOpcode()) { 4046 default: return false; 4047 case X86::TEST8rr: 4048 case X86::TEST16rr: 4049 case X86::TEST32rr: 4050 case X86::TEST64rr: 4051 return true; 4052 case X86::ADD32ri: 4053 // FIXME: AsmPrinter doesn't know how to handle 4054 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4055 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4056 return false; 4057 break; 4058 } 4059 } 4060 4061 if (Ops.size() != 1) 4062 return false; 4063 4064 unsigned OpNum = Ops[0]; 4065 unsigned Opc = MI->getOpcode(); 4066 unsigned NumOps = MI->getDesc().getNumOperands(); 4067 bool isTwoAddr = NumOps > 1 && 4068 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4069 4070 // Folding a memory location into the two-address part of a two-address 4071 // instruction is different than folding it other places. It requires 4072 // replacing the *two* registers with the memory location. 4073 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 4074 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 4075 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4076 } else if (OpNum == 0) { // If operand 0 4077 switch (Opc) { 4078 case X86::MOV8r0: 4079 case X86::MOV16r0: 4080 case X86::MOV32r0: 4081 case X86::MOV64r0: return true; 4082 default: break; 4083 } 4084 OpcodeTablePtr = &RegOp2MemOpTable0; 4085 } else if (OpNum == 1) { 4086 OpcodeTablePtr = &RegOp2MemOpTable1; 4087 } else if (OpNum == 2) { 4088 OpcodeTablePtr = &RegOp2MemOpTable2; 4089 } else if (OpNum == 3) { 4090 OpcodeTablePtr = &RegOp2MemOpTable3; 4091 } 4092 4093 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 4094 return true; 4095 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops); 4096 } 4097 4098 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 4099 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 4100 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4101 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4102 MemOp2RegOpTable.find(MI->getOpcode()); 4103 if (I == MemOp2RegOpTable.end()) 4104 return false; 4105 unsigned Opc = I->second.first; 4106 unsigned Index = I->second.second & TB_INDEX_MASK; 4107 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4108 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4109 if (UnfoldLoad && !FoldedLoad) 4110 return false; 4111 UnfoldLoad &= FoldedLoad; 4112 if (UnfoldStore && !FoldedStore) 4113 return false; 4114 UnfoldStore &= FoldedStore; 4115 4116 const MCInstrDesc &MCID = get(Opc); 4117 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4118 if (!MI->hasOneMemOperand() && 4119 RC == &X86::VR128RegClass && 4120 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4121 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 4122 // conservatively assume the address is unaligned. That's bad for 4123 // performance. 4124 return false; 4125 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 4126 SmallVector<MachineOperand,2> BeforeOps; 4127 SmallVector<MachineOperand,2> AfterOps; 4128 SmallVector<MachineOperand,4> ImpOps; 4129 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4130 MachineOperand &Op = MI->getOperand(i); 4131 if (i >= Index && i < Index + X86::AddrNumOperands) 4132 AddrOps.push_back(Op); 4133 else if (Op.isReg() && Op.isImplicit()) 4134 ImpOps.push_back(Op); 4135 else if (i < Index) 4136 BeforeOps.push_back(Op); 4137 else if (i > Index) 4138 AfterOps.push_back(Op); 4139 } 4140 4141 // Emit the load instruction. 4142 if (UnfoldLoad) { 4143 std::pair<MachineInstr::mmo_iterator, 4144 MachineInstr::mmo_iterator> MMOs = 4145 MF.extractLoadMemRefs(MI->memoperands_begin(), 4146 MI->memoperands_end()); 4147 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4148 if (UnfoldStore) { 4149 // Address operands cannot be marked isKill. 4150 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4151 MachineOperand &MO = NewMIs[0]->getOperand(i); 4152 if (MO.isReg()) 4153 MO.setIsKill(false); 4154 } 4155 } 4156 } 4157 4158 // Emit the data processing instruction. 4159 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4160 MachineInstrBuilder MIB(MF, DataMI); 4161 4162 if (FoldedStore) 4163 MIB.addReg(Reg, RegState::Define); 4164 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4165 MIB.addOperand(BeforeOps[i]); 4166 if (FoldedLoad) 4167 MIB.addReg(Reg); 4168 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4169 MIB.addOperand(AfterOps[i]); 4170 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4171 MachineOperand &MO = ImpOps[i]; 4172 MIB.addReg(MO.getReg(), 4173 getDefRegState(MO.isDef()) | 4174 RegState::Implicit | 4175 getKillRegState(MO.isKill()) | 4176 getDeadRegState(MO.isDead()) | 4177 getUndefRegState(MO.isUndef())); 4178 } 4179 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4180 switch (DataMI->getOpcode()) { 4181 default: break; 4182 case X86::CMP64ri32: 4183 case X86::CMP64ri8: 4184 case X86::CMP32ri: 4185 case X86::CMP32ri8: 4186 case X86::CMP16ri: 4187 case X86::CMP16ri8: 4188 case X86::CMP8ri: { 4189 MachineOperand &MO0 = DataMI->getOperand(0); 4190 MachineOperand &MO1 = DataMI->getOperand(1); 4191 if (MO1.getImm() == 0) { 4192 unsigned NewOpc; 4193 switch (DataMI->getOpcode()) { 4194 default: llvm_unreachable("Unreachable!"); 4195 case X86::CMP64ri8: 4196 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 4197 case X86::CMP32ri8: 4198 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 4199 case X86::CMP16ri8: 4200 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 4201 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 4202 } 4203 DataMI->setDesc(get(NewOpc)); 4204 MO1.ChangeToRegister(MO0.getReg(), false); 4205 } 4206 } 4207 } 4208 NewMIs.push_back(DataMI); 4209 4210 // Emit the store instruction. 4211 if (UnfoldStore) { 4212 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 4213 std::pair<MachineInstr::mmo_iterator, 4214 MachineInstr::mmo_iterator> MMOs = 4215 MF.extractStoreMemRefs(MI->memoperands_begin(), 4216 MI->memoperands_end()); 4217 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4218 } 4219 4220 return true; 4221 } 4222 4223 bool 4224 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4225 SmallVectorImpl<SDNode*> &NewNodes) const { 4226 if (!N->isMachineOpcode()) 4227 return false; 4228 4229 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4230 MemOp2RegOpTable.find(N->getMachineOpcode()); 4231 if (I == MemOp2RegOpTable.end()) 4232 return false; 4233 unsigned Opc = I->second.first; 4234 unsigned Index = I->second.second & TB_INDEX_MASK; 4235 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4236 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4237 const MCInstrDesc &MCID = get(Opc); 4238 MachineFunction &MF = DAG.getMachineFunction(); 4239 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4240 unsigned NumDefs = MCID.NumDefs; 4241 std::vector<SDValue> AddrOps; 4242 std::vector<SDValue> BeforeOps; 4243 std::vector<SDValue> AfterOps; 4244 DebugLoc dl = N->getDebugLoc(); 4245 unsigned NumOps = N->getNumOperands(); 4246 for (unsigned i = 0; i != NumOps-1; ++i) { 4247 SDValue Op = N->getOperand(i); 4248 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 4249 AddrOps.push_back(Op); 4250 else if (i < Index-NumDefs) 4251 BeforeOps.push_back(Op); 4252 else if (i > Index-NumDefs) 4253 AfterOps.push_back(Op); 4254 } 4255 SDValue Chain = N->getOperand(NumOps-1); 4256 AddrOps.push_back(Chain); 4257 4258 // Emit the load instruction. 4259 SDNode *Load = 0; 4260 if (FoldedLoad) { 4261 EVT VT = *RC->vt_begin(); 4262 std::pair<MachineInstr::mmo_iterator, 4263 MachineInstr::mmo_iterator> MMOs = 4264 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4265 cast<MachineSDNode>(N)->memoperands_end()); 4266 if (!(*MMOs.first) && 4267 RC == &X86::VR128RegClass && 4268 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4269 // Do not introduce a slow unaligned load. 4270 return false; 4271 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4272 bool isAligned = (*MMOs.first) && 4273 (*MMOs.first)->getAlignment() >= Alignment; 4274 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 4275 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 4276 NewNodes.push_back(Load); 4277 4278 // Preserve memory reference information. 4279 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4280 } 4281 4282 // Emit the data processing instruction. 4283 std::vector<EVT> VTs; 4284 const TargetRegisterClass *DstRC = 0; 4285 if (MCID.getNumDefs() > 0) { 4286 DstRC = getRegClass(MCID, 0, &RI, MF); 4287 VTs.push_back(*DstRC->vt_begin()); 4288 } 4289 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 4290 EVT VT = N->getValueType(i); 4291 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 4292 VTs.push_back(VT); 4293 } 4294 if (Load) 4295 BeforeOps.push_back(SDValue(Load, 0)); 4296 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 4297 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 4298 BeforeOps.size()); 4299 NewNodes.push_back(NewNode); 4300 4301 // Emit the store instruction. 4302 if (FoldedStore) { 4303 AddrOps.pop_back(); 4304 AddrOps.push_back(SDValue(NewNode, 0)); 4305 AddrOps.push_back(Chain); 4306 std::pair<MachineInstr::mmo_iterator, 4307 MachineInstr::mmo_iterator> MMOs = 4308 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4309 cast<MachineSDNode>(N)->memoperands_end()); 4310 if (!(*MMOs.first) && 4311 RC == &X86::VR128RegClass && 4312 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4313 // Do not introduce a slow unaligned store. 4314 return false; 4315 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4316 bool isAligned = (*MMOs.first) && 4317 (*MMOs.first)->getAlignment() >= Alignment; 4318 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 4319 isAligned, TM), 4320 dl, MVT::Other, 4321 &AddrOps[0], AddrOps.size()); 4322 NewNodes.push_back(Store); 4323 4324 // Preserve memory reference information. 4325 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4326 } 4327 4328 return true; 4329 } 4330 4331 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 4332 bool UnfoldLoad, bool UnfoldStore, 4333 unsigned *LoadRegIndex) const { 4334 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4335 MemOp2RegOpTable.find(Opc); 4336 if (I == MemOp2RegOpTable.end()) 4337 return 0; 4338 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4339 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4340 if (UnfoldLoad && !FoldedLoad) 4341 return 0; 4342 if (UnfoldStore && !FoldedStore) 4343 return 0; 4344 if (LoadRegIndex) 4345 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 4346 return I->second.first; 4347 } 4348 4349 bool 4350 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4351 int64_t &Offset1, int64_t &Offset2) const { 4352 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 4353 return false; 4354 unsigned Opc1 = Load1->getMachineOpcode(); 4355 unsigned Opc2 = Load2->getMachineOpcode(); 4356 switch (Opc1) { 4357 default: return false; 4358 case X86::MOV8rm: 4359 case X86::MOV16rm: 4360 case X86::MOV32rm: 4361 case X86::MOV64rm: 4362 case X86::LD_Fp32m: 4363 case X86::LD_Fp64m: 4364 case X86::LD_Fp80m: 4365 case X86::MOVSSrm: 4366 case X86::MOVSDrm: 4367 case X86::MMX_MOVD64rm: 4368 case X86::MMX_MOVQ64rm: 4369 case X86::FsMOVAPSrm: 4370 case X86::FsMOVAPDrm: 4371 case X86::MOVAPSrm: 4372 case X86::MOVUPSrm: 4373 case X86::MOVAPDrm: 4374 case X86::MOVDQArm: 4375 case X86::MOVDQUrm: 4376 // AVX load instructions 4377 case X86::VMOVSSrm: 4378 case X86::VMOVSDrm: 4379 case X86::FsVMOVAPSrm: 4380 case X86::FsVMOVAPDrm: 4381 case X86::VMOVAPSrm: 4382 case X86::VMOVUPSrm: 4383 case X86::VMOVAPDrm: 4384 case X86::VMOVDQArm: 4385 case X86::VMOVDQUrm: 4386 case X86::VMOVAPSYrm: 4387 case X86::VMOVUPSYrm: 4388 case X86::VMOVAPDYrm: 4389 case X86::VMOVDQAYrm: 4390 case X86::VMOVDQUYrm: 4391 break; 4392 } 4393 switch (Opc2) { 4394 default: return false; 4395 case X86::MOV8rm: 4396 case X86::MOV16rm: 4397 case X86::MOV32rm: 4398 case X86::MOV64rm: 4399 case X86::LD_Fp32m: 4400 case X86::LD_Fp64m: 4401 case X86::LD_Fp80m: 4402 case X86::MOVSSrm: 4403 case X86::MOVSDrm: 4404 case X86::MMX_MOVD64rm: 4405 case X86::MMX_MOVQ64rm: 4406 case X86::FsMOVAPSrm: 4407 case X86::FsMOVAPDrm: 4408 case X86::MOVAPSrm: 4409 case X86::MOVUPSrm: 4410 case X86::MOVAPDrm: 4411 case X86::MOVDQArm: 4412 case X86::MOVDQUrm: 4413 // AVX load instructions 4414 case X86::VMOVSSrm: 4415 case X86::VMOVSDrm: 4416 case X86::FsVMOVAPSrm: 4417 case X86::FsVMOVAPDrm: 4418 case X86::VMOVAPSrm: 4419 case X86::VMOVUPSrm: 4420 case X86::VMOVAPDrm: 4421 case X86::VMOVDQArm: 4422 case X86::VMOVDQUrm: 4423 case X86::VMOVAPSYrm: 4424 case X86::VMOVUPSYrm: 4425 case X86::VMOVAPDYrm: 4426 case X86::VMOVDQAYrm: 4427 case X86::VMOVDQUYrm: 4428 break; 4429 } 4430 4431 // Check if chain operands and base addresses match. 4432 if (Load1->getOperand(0) != Load2->getOperand(0) || 4433 Load1->getOperand(5) != Load2->getOperand(5)) 4434 return false; 4435 // Segment operands should match as well. 4436 if (Load1->getOperand(4) != Load2->getOperand(4)) 4437 return false; 4438 // Scale should be 1, Index should be Reg0. 4439 if (Load1->getOperand(1) == Load2->getOperand(1) && 4440 Load1->getOperand(2) == Load2->getOperand(2)) { 4441 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 4442 return false; 4443 4444 // Now let's examine the displacements. 4445 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 4446 isa<ConstantSDNode>(Load2->getOperand(3))) { 4447 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4448 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 4449 return true; 4450 } 4451 } 4452 return false; 4453 } 4454 4455 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 4456 int64_t Offset1, int64_t Offset2, 4457 unsigned NumLoads) const { 4458 assert(Offset2 > Offset1); 4459 if ((Offset2 - Offset1) / 8 > 64) 4460 return false; 4461 4462 unsigned Opc1 = Load1->getMachineOpcode(); 4463 unsigned Opc2 = Load2->getMachineOpcode(); 4464 if (Opc1 != Opc2) 4465 return false; // FIXME: overly conservative? 4466 4467 switch (Opc1) { 4468 default: break; 4469 case X86::LD_Fp32m: 4470 case X86::LD_Fp64m: 4471 case X86::LD_Fp80m: 4472 case X86::MMX_MOVD64rm: 4473 case X86::MMX_MOVQ64rm: 4474 return false; 4475 } 4476 4477 EVT VT = Load1->getValueType(0); 4478 switch (VT.getSimpleVT().SimpleTy) { 4479 default: 4480 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 4481 // have 16 of them to play with. 4482 if (TM.getSubtargetImpl()->is64Bit()) { 4483 if (NumLoads >= 3) 4484 return false; 4485 } else if (NumLoads) { 4486 return false; 4487 } 4488 break; 4489 case MVT::i8: 4490 case MVT::i16: 4491 case MVT::i32: 4492 case MVT::i64: 4493 case MVT::f32: 4494 case MVT::f64: 4495 if (NumLoads) 4496 return false; 4497 break; 4498 } 4499 4500 return true; 4501 } 4502 4503 4504 bool X86InstrInfo:: 4505 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4506 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 4507 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 4508 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 4509 return true; 4510 Cond[0].setImm(GetOppositeBranchCondition(CC)); 4511 return false; 4512 } 4513 4514 bool X86InstrInfo:: 4515 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 4516 // FIXME: Return false for x87 stack register classes for now. We can't 4517 // allow any loads of these registers before FpGet_ST0_80. 4518 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 4519 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 4520 } 4521 4522 /// getGlobalBaseReg - Return a virtual register initialized with the 4523 /// the global base register value. Output instructions required to 4524 /// initialize the register in the function entry block, if necessary. 4525 /// 4526 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 4527 /// 4528 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 4529 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 4530 "X86-64 PIC uses RIP relative addressing"); 4531 4532 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 4533 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4534 if (GlobalBaseReg != 0) 4535 return GlobalBaseReg; 4536 4537 // Create the register. The code to initialize it is inserted 4538 // later, by the CGBR pass (below). 4539 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4540 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4541 X86FI->setGlobalBaseReg(GlobalBaseReg); 4542 return GlobalBaseReg; 4543 } 4544 4545 // These are the replaceable SSE instructions. Some of these have Int variants 4546 // that we don't include here. We don't want to replace instructions selected 4547 // by intrinsics. 4548 static const uint16_t ReplaceableInstrs[][3] = { 4549 //PackedSingle PackedDouble PackedInt 4550 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 4551 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 4552 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 4553 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 4554 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 4555 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 4556 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 4557 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 4558 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 4559 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 4560 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 4561 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 4562 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 4563 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 4564 // AVX 128-bit support 4565 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 4566 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 4567 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 4568 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 4569 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 4570 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 4571 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 4572 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 4573 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 4574 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 4575 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 4576 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 4577 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 4578 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 4579 // AVX 256-bit support 4580 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 4581 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 4582 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 4583 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 4584 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 4585 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 4586 }; 4587 4588 static const uint16_t ReplaceableInstrsAVX2[][3] = { 4589 //PackedSingle PackedDouble PackedInt 4590 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 4591 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 4592 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 4593 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 4594 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 4595 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 4596 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 4597 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 4598 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 4599 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 4600 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 4601 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 4602 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 4603 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr } 4604 }; 4605 4606 // FIXME: Some shuffle and unpack instructions have equivalents in different 4607 // domains, but they require a bit more work than just switching opcodes. 4608 4609 static const uint16_t *lookup(unsigned opcode, unsigned domain) { 4610 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 4611 if (ReplaceableInstrs[i][domain-1] == opcode) 4612 return ReplaceableInstrs[i]; 4613 return 0; 4614 } 4615 4616 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 4617 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 4618 if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 4619 return ReplaceableInstrsAVX2[i]; 4620 return 0; 4621 } 4622 4623 std::pair<uint16_t, uint16_t> 4624 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 4625 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4626 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2(); 4627 uint16_t validDomains = 0; 4628 if (domain && lookup(MI->getOpcode(), domain)) 4629 validDomains = 0xe; 4630 else if (domain && lookupAVX2(MI->getOpcode(), domain)) 4631 validDomains = hasAVX2 ? 0xe : 0x6; 4632 return std::make_pair(domain, validDomains); 4633 } 4634 4635 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 4636 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 4637 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4638 assert(dom && "Not an SSE instruction"); 4639 const uint16_t *table = lookup(MI->getOpcode(), dom); 4640 if (!table) { // try the other table 4641 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) && 4642 "256-bit vector operations only available in AVX2"); 4643 table = lookupAVX2(MI->getOpcode(), dom); 4644 } 4645 assert(table && "Cannot change domain"); 4646 MI->setDesc(get(table[Domain-1])); 4647 } 4648 4649 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 4650 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 4651 NopInst.setOpcode(X86::NOOP); 4652 } 4653 4654 bool X86InstrInfo::isHighLatencyDef(int opc) const { 4655 switch (opc) { 4656 default: return false; 4657 case X86::DIVSDrm: 4658 case X86::DIVSDrm_Int: 4659 case X86::DIVSDrr: 4660 case X86::DIVSDrr_Int: 4661 case X86::DIVSSrm: 4662 case X86::DIVSSrm_Int: 4663 case X86::DIVSSrr: 4664 case X86::DIVSSrr_Int: 4665 case X86::SQRTPDm: 4666 case X86::SQRTPDr: 4667 case X86::SQRTPSm: 4668 case X86::SQRTPSr: 4669 case X86::SQRTSDm: 4670 case X86::SQRTSDm_Int: 4671 case X86::SQRTSDr: 4672 case X86::SQRTSDr_Int: 4673 case X86::SQRTSSm: 4674 case X86::SQRTSSm_Int: 4675 case X86::SQRTSSr: 4676 case X86::SQRTSSr_Int: 4677 // AVX instructions with high latency 4678 case X86::VDIVSDrm: 4679 case X86::VDIVSDrm_Int: 4680 case X86::VDIVSDrr: 4681 case X86::VDIVSDrr_Int: 4682 case X86::VDIVSSrm: 4683 case X86::VDIVSSrm_Int: 4684 case X86::VDIVSSrr: 4685 case X86::VDIVSSrr_Int: 4686 case X86::VSQRTPDm: 4687 case X86::VSQRTPDr: 4688 case X86::VSQRTPSm: 4689 case X86::VSQRTPSr: 4690 case X86::VSQRTSDm: 4691 case X86::VSQRTSDm_Int: 4692 case X86::VSQRTSDr: 4693 case X86::VSQRTSSm: 4694 case X86::VSQRTSSm_Int: 4695 case X86::VSQRTSSr: 4696 return true; 4697 } 4698 } 4699 4700 bool X86InstrInfo:: 4701 hasHighOperandLatency(const InstrItineraryData *ItinData, 4702 const MachineRegisterInfo *MRI, 4703 const MachineInstr *DefMI, unsigned DefIdx, 4704 const MachineInstr *UseMI, unsigned UseIdx) const { 4705 return isHighLatencyDef(DefMI->getOpcode()); 4706 } 4707 4708 namespace { 4709 /// CGBR - Create Global Base Reg pass. This initializes the PIC 4710 /// global base register for x86-32. 4711 struct CGBR : public MachineFunctionPass { 4712 static char ID; 4713 CGBR() : MachineFunctionPass(ID) {} 4714 4715 virtual bool runOnMachineFunction(MachineFunction &MF) { 4716 const X86TargetMachine *TM = 4717 static_cast<const X86TargetMachine *>(&MF.getTarget()); 4718 4719 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 4720 "X86-64 PIC uses RIP relative addressing"); 4721 4722 // Only emit a global base reg in PIC mode. 4723 if (TM->getRelocationModel() != Reloc::PIC_) 4724 return false; 4725 4726 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 4727 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4728 4729 // If we didn't need a GlobalBaseReg, don't insert code. 4730 if (GlobalBaseReg == 0) 4731 return false; 4732 4733 // Insert the set of GlobalBaseReg into the first MBB of the function 4734 MachineBasicBlock &FirstMBB = MF.front(); 4735 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 4736 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 4737 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4738 const X86InstrInfo *TII = TM->getInstrInfo(); 4739 4740 unsigned PC; 4741 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 4742 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 4743 else 4744 PC = GlobalBaseReg; 4745 4746 // Operand of MovePCtoStack is completely ignored by asm printer. It's 4747 // only used in JIT code emission as displacement to pc. 4748 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 4749 4750 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 4751 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 4752 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 4753 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 4754 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 4755 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 4756 X86II::MO_GOT_ABSOLUTE_ADDRESS); 4757 } 4758 4759 return true; 4760 } 4761 4762 virtual const char *getPassName() const { 4763 return "X86 PIC Global Base Reg Initialization"; 4764 } 4765 4766 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4767 AU.setPreservesCFG(); 4768 MachineFunctionPass::getAnalysisUsage(AU); 4769 } 4770 }; 4771 } 4772 4773 char CGBR::ID = 0; 4774 FunctionPass* 4775 llvm::createGlobalBaseRegPass() { return new CGBR(); } 4776 4777 namespace { 4778 struct LDTLSCleanup : public MachineFunctionPass { 4779 static char ID; 4780 LDTLSCleanup() : MachineFunctionPass(ID) {} 4781 4782 virtual bool runOnMachineFunction(MachineFunction &MF) { 4783 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 4784 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 4785 // No point folding accesses if there isn't at least two. 4786 return false; 4787 } 4788 4789 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 4790 return VisitNode(DT->getRootNode(), 0); 4791 } 4792 4793 // Visit the dominator subtree rooted at Node in pre-order. 4794 // If TLSBaseAddrReg is non-null, then use that to replace any 4795 // TLS_base_addr instructions. Otherwise, create the register 4796 // when the first such instruction is seen, and then use it 4797 // as we encounter more instructions. 4798 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 4799 MachineBasicBlock *BB = Node->getBlock(); 4800 bool Changed = false; 4801 4802 // Traverse the current block. 4803 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 4804 ++I) { 4805 switch (I->getOpcode()) { 4806 case X86::TLS_base_addr32: 4807 case X86::TLS_base_addr64: 4808 if (TLSBaseAddrReg) 4809 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 4810 else 4811 I = SetRegister(I, &TLSBaseAddrReg); 4812 Changed = true; 4813 break; 4814 default: 4815 break; 4816 } 4817 } 4818 4819 // Visit the children of this block in the dominator tree. 4820 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 4821 I != E; ++I) { 4822 Changed |= VisitNode(*I, TLSBaseAddrReg); 4823 } 4824 4825 return Changed; 4826 } 4827 4828 // Replace the TLS_base_addr instruction I with a copy from 4829 // TLSBaseAddrReg, returning the new instruction. 4830 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 4831 unsigned TLSBaseAddrReg) { 4832 MachineFunction *MF = I->getParent()->getParent(); 4833 const X86TargetMachine *TM = 4834 static_cast<const X86TargetMachine *>(&MF->getTarget()); 4835 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4836 const X86InstrInfo *TII = TM->getInstrInfo(); 4837 4838 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 4839 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 4840 TII->get(TargetOpcode::COPY), 4841 is64Bit ? X86::RAX : X86::EAX) 4842 .addReg(TLSBaseAddrReg); 4843 4844 // Erase the TLS_base_addr instruction. 4845 I->eraseFromParent(); 4846 4847 return Copy; 4848 } 4849 4850 // Create a virtal register in *TLSBaseAddrReg, and populate it by 4851 // inserting a copy instruction after I. Returns the new instruction. 4852 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 4853 MachineFunction *MF = I->getParent()->getParent(); 4854 const X86TargetMachine *TM = 4855 static_cast<const X86TargetMachine *>(&MF->getTarget()); 4856 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4857 const X86InstrInfo *TII = TM->getInstrInfo(); 4858 4859 // Create a virtual register for the TLS base address. 4860 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4861 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 4862 ? &X86::GR64RegClass 4863 : &X86::GR32RegClass); 4864 4865 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 4866 MachineInstr *Next = I->getNextNode(); 4867 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 4868 TII->get(TargetOpcode::COPY), 4869 *TLSBaseAddrReg) 4870 .addReg(is64Bit ? X86::RAX : X86::EAX); 4871 4872 return Copy; 4873 } 4874 4875 virtual const char *getPassName() const { 4876 return "Local Dynamic TLS Access Clean-up"; 4877 } 4878 4879 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4880 AU.setPreservesCFG(); 4881 AU.addRequired<MachineDominatorTree>(); 4882 MachineFunctionPass::getAnalysisUsage(AU); 4883 } 4884 }; 4885 } 4886 4887 char LDTLSCleanup::ID = 0; 4888 FunctionPass* 4889 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 4890
