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    Searched refs:IsWrite (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/Transforms/Instrumentation/
AddressSanitizer.cpp 264 Value *Addr, uint32_t TypeSize, bool IsWrite,
269 bool IsWrite, size_t AccessSizeIndex,
274 Instruction *InsertBefore, bool IsWrite);
560 Value *Addr, Value *Size, Instruction *InsertBefore, bool IsWrite) {
565 instrumentAddress(OrigIns, InsertBefore, Addr, 8, IsWrite, Size);
571 instrumentAddress(OrigIns, InsertBefore, AddrLast, 8, IsWrite, Size);
601 // and set IsWrite. Otherwise return NULL.
602 static Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite) {
605 *IsWrite = false;
610 *IsWrite = true
    [all...]
ThreadSanitizer.cpp 369 bool IsWrite = isa<StoreInst>(*I);
370 Value *Addr = IsWrite
376 if (IsWrite && isVtableAccess(I)) {
389 Value *OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx];
391 if (IsWrite) NumInstrumentedWrites++;
  /external/compiler-rt/lib/tsan/tests/unit/
tsan_shadow_test.cc 28 EXPECT_EQ(s.IsWrite(), true);
  /external/compiler-rt/lib/tsan/rtl/
tsan_rtl.h 252 DCHECK_EQ(kAccessIsWrite, IsWrite());
315 bool IsWrite() const { return !IsRead(); }
345 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic));
353 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite));
361 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite));
tsan_rtl_report.cc 153 mop->write = s.IsWrite();

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