| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 608 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
609 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
614 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
616 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
622 KnownZero <<= ShiftAmt;
623 KnownOne <<= ShiftAmt;
625 if (ShiftAmt)
626 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
632 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
635 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
[all...] |
| InstCombineCasts.cpp | 569 uint32_t ShiftAmt = KnownZeroMask.logBase2();
571 if (ShiftAmt) {
572 // Perform a logical shr by shiftamt.
574 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt),
[all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 487 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
490 KnownZero <<= ShiftAmt;
491 KnownOne <<= ShiftAmt;
492 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0
500 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
505 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
506 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
508 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
516 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
521 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
[all...] |
| ConstantFolding.cpp | 170 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1);
181 ConstantInt::get(Src->getType(), ShiftAmt));
182 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
202 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1);
207 ConstantInt::get(Src->getType(), ShiftAmt));
208 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 84 unsigned ShiftAmt = Log2_32(MemSize);
85 O << " #" << ShiftAmt;
|
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 826 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
827 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
832 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
846 AM.Scale = 1 << ShiftAmt;
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyCFG.cpp | [all...] |
| /external/llvm/lib/Support/ |
| APInt.cpp | 1030 /// Arithmetic right-shift this APInt by shiftAmt.
1032 APInt APInt::ashr(const APInt &shiftAmt) const {
1033 return ashr((unsigned)shiftAmt.getLimitedValue(BitWidth));
1036 /// Arithmetic right-shift this APInt by shiftAmt.
1038 APInt APInt::ashr(unsigned shiftAmt) const {
1039 assert(shiftAmt <= BitWidth && "Invalid shift amount");
1041 if (shiftAmt == 0)
1046 if (shiftAmt == BitWidth)
1051 (((int64_t(VAL) << SignBit) >> SignBit) >> shiftAmt));
1058 if (shiftAmt == BitWidth)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 724 unsigned ShiftAmt = SVOp->getMaskElt(i);
725 if (ShiftAmt < i) return -1;
726 ShiftAmt -= i;
731 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
736 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
739 return ShiftAmt;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 747 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
749 Op.getValueType(), InOp, ShiftAmt));
[all...] |
| DAGCombiner.cpp | [all...] |
