1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the X86 target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef X86BASEINFO_H 18 #define X86BASEINFO_H 19 20 #include "X86MCTargetDesc.h" 21 #include "llvm/Support/DataTypes.h" 22 #include "llvm/Support/ErrorHandling.h" 23 24 namespace llvm { 25 26 namespace X86 { 27 // Enums for memory operand decoding. Each memory operand is represented with 28 // a 5 operand sequence in the form: 29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30 // These enums help decode this. 31 enum { 32 AddrBaseReg = 0, 33 AddrScaleAmt = 1, 34 AddrIndexReg = 2, 35 AddrDisp = 3, 36 37 /// AddrSegmentReg - The operand # of the segment in the memory operand. 38 AddrSegmentReg = 4, 39 40 /// AddrNumOperands - Total number of operands in a memory reference. 41 AddrNumOperands = 5 42 }; 43 } // end namespace X86; 44 45 46 /// X86II - This namespace holds all of the target specific flags that 47 /// instruction info tracks. 48 /// 49 namespace X86II { 50 /// Target Operand Flag enum. 51 enum TOF { 52 //===------------------------------------------------------------------===// 53 // X86 Specific MachineOperand flags. 54 55 MO_NO_FLAG, 56 57 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 58 /// relocation of: 59 /// SYMBOL_LABEL + [. - PICBASELABEL] 60 MO_GOT_ABSOLUTE_ADDRESS, 61 62 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 63 /// immediate should get the value of the symbol minus the PIC base label: 64 /// SYMBOL_LABEL - PICBASELABEL 65 MO_PIC_BASE_OFFSET, 66 67 /// MO_GOT - On a symbol operand this indicates that the immediate is the 68 /// offset to the GOT entry for the symbol name from the base of the GOT. 69 /// 70 /// See the X86-64 ELF ABI supplement for more details. 71 /// SYMBOL_LABEL @GOT 72 MO_GOT, 73 74 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 75 /// the offset to the location of the symbol name from the base of the GOT. 76 /// 77 /// See the X86-64 ELF ABI supplement for more details. 78 /// SYMBOL_LABEL @GOTOFF 79 MO_GOTOFF, 80 81 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 82 /// offset to the GOT entry for the symbol name from the current code 83 /// location. 84 /// 85 /// See the X86-64 ELF ABI supplement for more details. 86 /// SYMBOL_LABEL @GOTPCREL 87 MO_GOTPCREL, 88 89 /// MO_PLT - On a symbol operand this indicates that the immediate is 90 /// offset to the PLT entry of symbol name from the current code location. 91 /// 92 /// See the X86-64 ELF ABI supplement for more details. 93 /// SYMBOL_LABEL @PLT 94 MO_PLT, 95 96 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 97 /// the offset of the GOT entry with the TLS index structure that contains 98 /// the module number and variable offset for the symbol. Used in the 99 /// general dynamic TLS access model. 100 /// 101 /// See 'ELF Handling for Thread-Local Storage' for more details. 102 /// SYMBOL_LABEL @TLSGD 103 MO_TLSGD, 104 105 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 106 /// the offset of the GOT entry with the TLS index for the module that 107 /// contains the symbol. When this index is passed to a call to 108 /// __tls_get_addr, the function will return the base address of the TLS 109 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 110 /// 111 /// See 'ELF Handling for Thread-Local Storage' for more details. 112 /// SYMBOL_LABEL @TLSLD 113 MO_TLSLD, 114 115 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 116 /// the offset of the GOT entry with the TLS index for the module that 117 /// contains the symbol. When this index is passed to a call to 118 /// ___tls_get_addr, the function will return the base address of the TLS 119 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 120 /// 121 /// See 'ELF Handling for Thread-Local Storage' for more details. 122 /// SYMBOL_LABEL @TLSLDM 123 MO_TLSLDM, 124 125 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 126 /// the offset of the GOT entry with the thread-pointer offset for the 127 /// symbol. Used in the x86-64 initial exec TLS access model. 128 /// 129 /// See 'ELF Handling for Thread-Local Storage' for more details. 130 /// SYMBOL_LABEL @GOTTPOFF 131 MO_GOTTPOFF, 132 133 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 134 /// the absolute address of the GOT entry with the negative thread-pointer 135 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 136 /// model. 137 /// 138 /// See 'ELF Handling for Thread-Local Storage' for more details. 139 /// SYMBOL_LABEL @INDNTPOFF 140 MO_INDNTPOFF, 141 142 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 143 /// the thread-pointer offset for the symbol. Used in the x86-64 local 144 /// exec TLS access model. 145 /// 146 /// See 'ELF Handling for Thread-Local Storage' for more details. 147 /// SYMBOL_LABEL @TPOFF 148 MO_TPOFF, 149 150 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 151 /// the offset of the GOT entry with the TLS offset of the symbol. Used 152 /// in the local dynamic TLS access model. 153 /// 154 /// See 'ELF Handling for Thread-Local Storage' for more details. 155 /// SYMBOL_LABEL @DTPOFF 156 MO_DTPOFF, 157 158 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 159 /// the negative thread-pointer offset for the symbol. Used in the IA32 160 /// local exec TLS access model. 161 /// 162 /// See 'ELF Handling for Thread-Local Storage' for more details. 163 /// SYMBOL_LABEL @NTPOFF 164 MO_NTPOFF, 165 166 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 167 /// the offset of the GOT entry with the negative thread-pointer offset for 168 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 169 /// 170 /// See 'ELF Handling for Thread-Local Storage' for more details. 171 /// SYMBOL_LABEL @GOTNTPOFF 172 MO_GOTNTPOFF, 173 174 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 175 /// reference is actually to the "__imp_FOO" symbol. This is used for 176 /// dllimport linkage on windows. 177 MO_DLLIMPORT, 178 179 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 180 /// reference is actually to the "FOO$stub" symbol. This is used for calls 181 /// and jumps to external functions on Tiger and earlier. 182 MO_DARWIN_STUB, 183 184 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 185 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 186 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 187 MO_DARWIN_NONLAZY, 188 189 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 190 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 191 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 192 MO_DARWIN_NONLAZY_PIC_BASE, 193 194 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 195 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 196 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 197 /// stub. 198 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 199 200 /// MO_TLVP - On a symbol operand this indicates that the immediate is 201 /// some TLS offset. 202 /// 203 /// This is the TLS offset for the Darwin TLS mechanism. 204 MO_TLVP, 205 206 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 207 /// is some TLS offset from the picbase. 208 /// 209 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 210 MO_TLVP_PIC_BASE, 211 212 /// MO_SECREL - On a symbol operand this indicates that the immediate is 213 /// the offset from beginning of section. 214 /// 215 /// This is the TLS offset for the COFF/Windows TLS mechanism. 216 MO_SECREL 217 }; 218 219 enum { 220 //===------------------------------------------------------------------===// 221 // Instruction encodings. These are the standard/most common forms for X86 222 // instructions. 223 // 224 225 // PseudoFrm - This represents an instruction that is a pseudo instruction 226 // or one that has not been implemented yet. It is illegal to code generate 227 // it, but tolerated for intermediate implementation stages. 228 Pseudo = 0, 229 230 /// Raw - This form is for instructions that don't have any operands, so 231 /// they are just a fixed opcode value, like 'leave'. 232 RawFrm = 1, 233 234 /// AddRegFrm - This form is used for instructions like 'push r32' that have 235 /// their one register operand added to their opcode. 236 AddRegFrm = 2, 237 238 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 239 /// to specify a destination, which in this case is a register. 240 /// 241 MRMDestReg = 3, 242 243 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 244 /// to specify a destination, which in this case is memory. 245 /// 246 MRMDestMem = 4, 247 248 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 249 /// to specify a source, which in this case is a register. 250 /// 251 MRMSrcReg = 5, 252 253 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 254 /// to specify a source, which in this case is memory. 255 /// 256 MRMSrcMem = 6, 257 258 /// MRM[0-7][rm] - These forms are used to represent instructions that use 259 /// a Mod/RM byte, and use the middle field to hold extended opcode 260 /// information. In the intel manual these are represented as /0, /1, ... 261 /// 262 263 // First, instructions that operate on a register r/m operand... 264 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 265 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 266 267 // Next, instructions that operate on a memory r/m operand... 268 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 269 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 270 271 // MRMInitReg - This form is used for instructions whose source and 272 // destinations are the same register. 273 MRMInitReg = 32, 274 275 //// MRM_XX - A mod/rm byte of exactly 0xXX. 276 MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36, 277 MRM_C8 = 37, MRM_C9 = 38, MRM_E8 = 39, MRM_F0 = 40, 278 MRM_F8 = 41, MRM_F9 = 42, MRM_D0 = 45, MRM_D1 = 46, 279 MRM_D4 = 47, MRM_D5 = 48, MRM_D8 = 49, MRM_D9 = 50, 280 MRM_DA = 51, MRM_DB = 52, MRM_DC = 53, MRM_DD = 54, 281 MRM_DE = 55, MRM_DF = 56, 282 283 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 284 /// immediates, the first of which is a 16-bit immediate (specified by 285 /// the imm encoding) and the second is a 8-bit fixed value. 286 RawFrmImm8 = 43, 287 288 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 289 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 290 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 291 /// manual, this operand is described as pntr16:32 and pntr16:16 292 RawFrmImm16 = 44, 293 294 FormMask = 63, 295 296 //===------------------------------------------------------------------===// 297 // Actual flags... 298 299 // OpSize - Set if this instruction requires an operand size prefix (0x66), 300 // which most often indicates that the instruction operates on 16 bit data 301 // instead of 32 bit data. 302 OpSize = 1 << 6, 303 304 // AsSize - Set if this instruction requires an operand size prefix (0x67), 305 // which most often indicates that the instruction address 16 bit address 306 // instead of 32 bit address (or 32 bit address in 64 bit mode). 307 AdSize = 1 << 7, 308 309 //===------------------------------------------------------------------===// 310 // Op0Mask - There are several prefix bytes that are used to form two byte 311 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 312 // used to obtain the setting of this field. If no bits in this field is 313 // set, there is no prefix byte for obtaining a multibyte opcode. 314 // 315 Op0Shift = 8, 316 Op0Mask = 0x1F << Op0Shift, 317 318 // TB - TwoByte - Set if this instruction has a two byte opcode, which 319 // starts with a 0x0F byte before the real opcode. 320 TB = 1 << Op0Shift, 321 322 // REP - The 0xF3 prefix byte indicating repetition of the following 323 // instruction. 324 REP = 2 << Op0Shift, 325 326 // D8-DF - These escape opcodes are used by the floating point unit. These 327 // values must remain sequential. 328 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 329 DA = 5 << Op0Shift, DB = 6 << Op0Shift, 330 DC = 7 << Op0Shift, DD = 8 << Op0Shift, 331 DE = 9 << Op0Shift, DF = 10 << Op0Shift, 332 333 // XS, XD - These prefix codes are for single and double precision scalar 334 // floating point operations performed in the SSE registers. 335 XD = 11 << Op0Shift, XS = 12 << Op0Shift, 336 337 // T8, TA, A6, A7 - Prefix after the 0x0F prefix. 338 T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 339 A6 = 15 << Op0Shift, A7 = 16 << Op0Shift, 340 341 // T8XD - Prefix before and after 0x0F. Combination of T8 and XD. 342 T8XD = 17 << Op0Shift, 343 344 // T8XS - Prefix before and after 0x0F. Combination of T8 and XS. 345 T8XS = 18 << Op0Shift, 346 347 // TAXD - Prefix before and after 0x0F. Combination of TA and XD. 348 TAXD = 19 << Op0Shift, 349 350 // XOP8 - Prefix to include use of imm byte. 351 XOP8 = 20 << Op0Shift, 352 353 // XOP9 - Prefix to exclude use of imm byte. 354 XOP9 = 21 << Op0Shift, 355 356 //===------------------------------------------------------------------===// 357 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 358 // They are used to specify GPRs and SSE registers, 64-bit operand size, 359 // etc. We only cares about REX.W and REX.R bits and only the former is 360 // statically determined. 361 // 362 REXShift = Op0Shift + 5, 363 REX_W = 1 << REXShift, 364 365 //===------------------------------------------------------------------===// 366 // This three-bit field describes the size of an immediate operand. Zero is 367 // unused so that we can tell if we forgot to set a value. 368 ImmShift = REXShift + 1, 369 ImmMask = 7 << ImmShift, 370 Imm8 = 1 << ImmShift, 371 Imm8PCRel = 2 << ImmShift, 372 Imm16 = 3 << ImmShift, 373 Imm16PCRel = 4 << ImmShift, 374 Imm32 = 5 << ImmShift, 375 Imm32PCRel = 6 << ImmShift, 376 Imm64 = 7 << ImmShift, 377 378 //===------------------------------------------------------------------===// 379 // FP Instruction Classification... Zero is non-fp instruction. 380 381 // FPTypeMask - Mask for all of the FP types... 382 FPTypeShift = ImmShift + 3, 383 FPTypeMask = 7 << FPTypeShift, 384 385 // NotFP - The default, set for instructions that do not use FP registers. 386 NotFP = 0 << FPTypeShift, 387 388 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 389 ZeroArgFP = 1 << FPTypeShift, 390 391 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 392 OneArgFP = 2 << FPTypeShift, 393 394 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 395 // result back to ST(0). For example, fcos, fsqrt, etc. 396 // 397 OneArgFPRW = 3 << FPTypeShift, 398 399 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 400 // explicit argument, storing the result to either ST(0) or the implicit 401 // argument. For example: fadd, fsub, fmul, etc... 402 TwoArgFP = 4 << FPTypeShift, 403 404 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 405 // explicit argument, but have no destination. Example: fucom, fucomi, ... 406 CompareFP = 5 << FPTypeShift, 407 408 // CondMovFP - "2 operand" floating point conditional move instructions. 409 CondMovFP = 6 << FPTypeShift, 410 411 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 412 SpecialFP = 7 << FPTypeShift, 413 414 // Lock prefix 415 LOCKShift = FPTypeShift + 3, 416 LOCK = 1 << LOCKShift, 417 418 // Segment override prefixes. Currently we just need ability to address 419 // stuff in gs and fs segments. 420 SegOvrShift = LOCKShift + 1, 421 SegOvrMask = 3 << SegOvrShift, 422 FS = 1 << SegOvrShift, 423 GS = 2 << SegOvrShift, 424 425 // Execution domain for SSE instructions in bits 23, 24. 426 // 0 in bits 23-24 means normal, non-SSE instruction. 427 SSEDomainShift = SegOvrShift + 2, 428 429 OpcodeShift = SSEDomainShift + 2, 430 431 //===------------------------------------------------------------------===// 432 /// VEX - The opcode prefix used by AVX instructions 433 VEXShift = OpcodeShift + 8, 434 VEX = 1U << 0, 435 436 /// VEX_W - Has a opcode specific functionality, but is used in the same 437 /// way as REX_W is for regular SSE instructions. 438 VEX_W = 1U << 1, 439 440 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 441 /// address instructions in SSE are represented as 3 address ones in AVX 442 /// and the additional register is encoded in VEX_VVVV prefix. 443 VEX_4V = 1U << 2, 444 445 /// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode 446 /// operand 3 with VEX.vvvv. 447 VEX_4VOp3 = 1U << 3, 448 449 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, 450 /// must be encoded in the i8 immediate field. This usually happens in 451 /// instructions with 4 operands. 452 VEX_I8IMM = 1U << 4, 453 454 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 455 /// instruction uses 256-bit wide registers. This is usually auto detected 456 /// if a VR256 register is used, but some AVX instructions also have this 457 /// field marked when using a f256 memory references. 458 VEX_L = 1U << 5, 459 460 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX 461 // prefix. Usually used for scalar instructions. Needed by disassembler. 462 VEX_LIG = 1U << 6, 463 464 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the 465 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 466 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 467 /// storing a classifier in the imm8 field. To simplify our implementation, 468 /// we handle this by storeing the classifier in the opcode field and using 469 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 470 Has3DNow0F0FOpcode = 1U << 7, 471 472 /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in 473 /// ModRM or I8IMM. This is used for FMA4 and XOP instructions. 474 MemOp4 = 1U << 8, 475 476 /// XOP - Opcode prefix used by XOP instructions. 477 XOP = 1U << 9 478 479 }; 480 481 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 482 // specified machine instruction. 483 // 484 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 485 return TSFlags >> X86II::OpcodeShift; 486 } 487 488 inline bool hasImm(uint64_t TSFlags) { 489 return (TSFlags & X86II::ImmMask) != 0; 490 } 491 492 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 493 /// of the specified instruction. 494 inline unsigned getSizeOfImm(uint64_t TSFlags) { 495 switch (TSFlags & X86II::ImmMask) { 496 default: llvm_unreachable("Unknown immediate size"); 497 case X86II::Imm8: 498 case X86II::Imm8PCRel: return 1; 499 case X86II::Imm16: 500 case X86II::Imm16PCRel: return 2; 501 case X86II::Imm32: 502 case X86II::Imm32PCRel: return 4; 503 case X86II::Imm64: return 8; 504 } 505 } 506 507 /// isImmPCRel - Return true if the immediate of the specified instruction's 508 /// TSFlags indicates that it is pc relative. 509 inline unsigned isImmPCRel(uint64_t TSFlags) { 510 switch (TSFlags & X86II::ImmMask) { 511 default: llvm_unreachable("Unknown immediate size"); 512 case X86II::Imm8PCRel: 513 case X86II::Imm16PCRel: 514 case X86II::Imm32PCRel: 515 return true; 516 case X86II::Imm8: 517 case X86II::Imm16: 518 case X86II::Imm32: 519 case X86II::Imm64: 520 return false; 521 } 522 } 523 524 /// getMemoryOperandNo - The function returns the MCInst operand # for the 525 /// first field of the memory operand. If the instruction doesn't have a 526 /// memory operand, this returns -1. 527 /// 528 /// Note that this ignores tied operands. If there is a tied register which 529 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 530 /// counted as one operand. 531 /// 532 inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) { 533 switch (TSFlags & X86II::FormMask) { 534 case X86II::MRMInitReg: 535 // FIXME: Remove this form. 536 return -1; 537 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 538 case X86II::Pseudo: 539 case X86II::RawFrm: 540 case X86II::AddRegFrm: 541 case X86II::MRMDestReg: 542 case X86II::MRMSrcReg: 543 case X86II::RawFrmImm8: 544 case X86II::RawFrmImm16: 545 return -1; 546 case X86II::MRMDestMem: 547 return 0; 548 case X86II::MRMSrcMem: { 549 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 550 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 551 unsigned FirstMemOp = 1; 552 if (HasVEX_4V) 553 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 554 if (HasMemOp4) 555 ++FirstMemOp;// Skip the register source (which is encoded in I8IMM). 556 557 // FIXME: Maybe lea should have its own form? This is a horrible hack. 558 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 559 // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 560 return FirstMemOp; 561 } 562 case X86II::MRM0r: case X86II::MRM1r: 563 case X86II::MRM2r: case X86II::MRM3r: 564 case X86II::MRM4r: case X86II::MRM5r: 565 case X86II::MRM6r: case X86II::MRM7r: 566 return -1; 567 case X86II::MRM0m: case X86II::MRM1m: 568 case X86II::MRM2m: case X86II::MRM3m: 569 case X86II::MRM4m: case X86II::MRM5m: 570 case X86II::MRM6m: case X86II::MRM7m: { 571 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 572 unsigned FirstMemOp = 0; 573 if (HasVEX_4V) 574 ++FirstMemOp;// Skip the register dest (which is encoded in VEX_VVVV). 575 return FirstMemOp; 576 } 577 case X86II::MRM_C1: case X86II::MRM_C2: 578 case X86II::MRM_C3: case X86II::MRM_C4: 579 case X86II::MRM_C8: case X86II::MRM_C9: 580 case X86II::MRM_E8: case X86II::MRM_F0: 581 case X86II::MRM_F8: case X86II::MRM_F9: 582 case X86II::MRM_D0: case X86II::MRM_D1: 583 case X86II::MRM_D4: case X86II::MRM_D5: 584 case X86II::MRM_D8: case X86II::MRM_D9: 585 case X86II::MRM_DA: case X86II::MRM_DB: 586 case X86II::MRM_DC: case X86II::MRM_DD: 587 case X86II::MRM_DE: case X86II::MRM_DF: 588 return -1; 589 } 590 } 591 592 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 593 /// higher) register? e.g. r8, xmm8, xmm13, etc. 594 inline bool isX86_64ExtendedReg(unsigned RegNo) { 595 switch (RegNo) { 596 default: break; 597 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 598 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 599 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 600 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 601 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 602 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 603 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 604 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 605 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 606 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 607 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 608 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 609 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 610 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 611 return true; 612 } 613 return false; 614 } 615 616 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 617 return (reg == X86::SPL || reg == X86::BPL || 618 reg == X86::SIL || reg == X86::DIL); 619 } 620 } 621 622 } // end namespace llvm; 623 624 #endif 625
