| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | [all...] |
| Thumb2InstrInfo.cpp | 33 : ARMBaseInstrInfo(STI), RI(*this, STI) {
|
| ARMAsmPrinter.cpp | 231 const TargetRegisterInfo *RI = TM.getRegisterInfo();
232 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| SubtargetEmitter.cpp | [all...] |
| /frameworks/compile/slang/ |
| slang_rs_export_type.cpp | 647 for (clang::TagDecl::redecl_iterator RI = RD->redecls_begin(),
649 RI != RE;
650 RI++) {
651 slangAssert(*RI != NULL && "cannot be NULL object");
653 Name = (*RI)->getName();
[all...] |
| /external/clang/lib/Sema/ |
| SemaLookup.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 615 ReturnInst::ReturnInst(const ReturnInst &RI)
616 : TerminatorInst(Type::getVoidTy(RI.getContext()), Instruction::Ret,
618 RI.getNumOperands(),
619 RI.getNumOperands()) {
620 if (RI.getNumOperands())
621 Op<0>() = RI.Op<0>();
622 SubclassOptionalData = RI.SubclassOptionalData;
665 ResumeInst::ResumeInst(const ResumeInst &RI)
666 : TerminatorInst(Type::getVoidTy(RI.getContext()), Instruction::Resume,
668 Op<0>() = RI.Op<0>()
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 59 RI(ST, *this), Subtarget(ST) {
411 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
413 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
417 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
419 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 434 Instruction *RI = cast<Instruction>(R);
435 RI->copyFastMathFlags(&I);
436 return RI;
[all...] |
| /external/clang/tools/libclang/ |
| RecursiveASTVisitor.h | 505 RI = StmtsToEnqueu.rbegin(),
506 RE = StmtsToEnqueu.rend(); RI != RE; ++RI)
507 Queue.push_back(*RI);
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfCompileUnit.cpp | 355 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
356 unsigned DWReg = RI->getDwarfRegNum(Reg, false);
368 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
369 unsigned DWReg = RI->getDwarfRegNum(Reg, false);
[all...] |
| /external/llvm/lib/CodeGen/ |
| SplitKit.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 32 RI(ST, *this), Subtarget(ST) {
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | 100 TM(tm), RI(tm, *this) {
[all...] |
| /external/llvm/lib/Transforms/Instrumentation/ |
| AddressSanitizer.cpp | 429 void visitReturnInst(ReturnInst &RI) {
430 RetVec.push_back(&RI);
773 if (ReturnInst *RI = dyn_cast<ReturnInst>(I->getTerminator())) {
774 CallInst::Create(AsanUnpoisonGlobals, "", RI);
[all...] |
| /external/openfst/src/test/ |
| algo_test.h | 678 VectorFst<Arc> RI(T);
680 while (potential.size() < RI.NumStates())
683 Reweight(&RI, potential, REWEIGHT_TO_INITIAL);
684 CHECK(Equiv(T, RI));
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_s390_toIR.c | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUStructurizeCFG.cpp | 363 RegionInfo *RI = ParentRegion->getRegionInfo();
375 Region *R = RI->getRegionFor(*PI);
|
| /external/llvm/lib/Transforms/Utils/ |
| CodeExtractor.cpp | 267 if (ReturnInst *RI = dyn_cast<ReturnInst>((*I)->getTerminator())) {
268 BasicBlock *New = (*I)->splitBasicBlock(RI, (*I)->getName()+".ret");
|
| /external/llvm/lib/Transforms/Scalar/ |
| SCCP.cpp | [all...] |
| GVN.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 791 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
792 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
[all...] |
