| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 32 RI(tm, *this)
36 return RI;
55 unsigned SubRegIndex = RI.getSubRegFromChannel(I);
57 RI.getSubReg(DestReg, SubRegIndex),
58 RI.getSubReg(SrcReg, SubRegIndex))
548 GET_REG_INDEX(RI.getEncodingValue(LI->first)));
|
| /external/llvm/lib/CodeGen/ |
| MachineTraceMetrics.cpp | [all...] |
| ScheduleDAGInstrs.cpp | [all...] |
| LiveInterval.cpp | 907 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LI.reg),
908 RE = MRI.reg_end(); RI != RE;) {
909 MachineOperand &MO = RI.getOperand();
911 ++RI;
|
| /external/clang/lib/StaticAnalyzer/Core/ |
| RegionStore.cpp | 631 for (RegionBindingsRef::iterator RI = B.begin(), RE = B.end();
632 RI != RE; ++RI){
633 const MemRegion *Base = RI.getKey();
635 const ClusterBindings &Cluster = RI.getData();
690 for (ClusterBindings::iterator RI = Cluster->begin(), RE = Cluster->end();
691 RI != RE; ++RI) {
692 if (!Callbacks.scan(RI.getData()))
[all...] |
| /external/llvm/tools/llvm-objdump/ |
| MachODump.cpp | 365 for (relocation_iterator RI = Sections[SectIdx].begin_relocations(),
366 RE = Sections[SectIdx].end_relocations(); RI != RE; RI.increment(ec)) {
368 RI->getAddress(RelocOffset);
373 RI->getSymbol(RelocSym);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 167 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
168 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
170 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
|
| /external/clang/lib/Basic/ |
| Diagnostic.cpp | 366 RI = storedDiag.range_begin(),
367 RE = storedDiag.range_end(); RI != RE; ++RI)
368 DiagRanges[i++] = *RI;
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyCFG.cpp | 97 bool SimplifyReturn(ReturnInst *RI, IRBuilder<> &Builder);
98 bool SimplifyResume(ResumeInst *RI, IRBuilder<> &Builder);
[all...] |
| BasicBlockUtils.cpp | 652 ReturnInst *llvm::FoldReturnIntoUncondBranch(ReturnInst *RI, BasicBlock *BB,
656 Instruction *NewRet = RI->clone();
|
| LowerInvoke.cpp | 396 if (ReturnInst *RI = dyn_cast<ReturnInst>(BB->getTerminator())) {
399 Returns.push_back(RI);
|
| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.c | 222 am->ARMam1.RI.reg = reg;
223 am->ARMam1.RI.simm13 = simm13;
240 vex_printf("%d(", am->ARMam1.RI.simm13);
241 ppHRegARM(am->ARMam1.RI.reg);
259 addHRegUse(u, HRmRead, am->ARMam1.RI.reg);
273 am->ARMam1.RI.reg = lookupHRegRemap(m, am->ARMam1.RI.reg);
290 am->ARMam2.RI.reg = reg;
291 am->ARMam2.RI.simm9 = simm9;
306 vex_printf("%d(", am->ARMam2.RI.simm9)
[all...] |
| host_arm_defs.h | 134 } RI;
165 } RI;
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 563 for (unsigned ri = 0, re = Roots.size(); ri != re; ++ri) {
564 const CodeGenRegister *Root = Roots[ri];
[all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | [all...] |
| /external/llvm/lib/IR/ |
| Verifier.cpp | 283 void visitReturnInst(ReturnInst &RI);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 565 const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
576 return (RI->needsStackRealignment(MF) ||
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 40 RI(*tm.getSubtargetImpl(), *this) {}
43 return RI;
|
| MipsSEInstrInfo.cpp | 29 RI(*tm.getSubtargetImpl(), *this),
33 return RI;
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCOpts.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CodeGenFunction.cpp | 394 for (FunctionDecl::redecl_iterator RI = FD->redecls_begin(),
395 RE = FD->redecls_end(); RI != RE; ++RI)
396 if (RI->isInlineSpecified()) {
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 32 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 32 RI(tm, *this) {}
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 44 RI(*this) {
|
| /external/webkit/Source/WebKit/android/content/ |
| address_detector.cpp | 716 RI = 46, // RI Rhode Island
735 MA, MA, MA, MA, MA, MA, MA, MA, RI, RI, // 020-029
[all...] |
