1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the X86MCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "mccodeemitter" 15 #include "MCTargetDesc/X86MCTargetDesc.h" 16 #include "MCTargetDesc/X86BaseInfo.h" 17 #include "MCTargetDesc/X86FixupKinds.h" 18 #include "llvm/MC/MCCodeEmitter.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrInfo.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/MC/MCSymbol.h" 26 #include "llvm/Support/raw_ostream.h" 27 28 using namespace llvm; 29 30 namespace { 31 class X86MCCodeEmitter : public MCCodeEmitter { 32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 const MCInstrInfo &MCII; 35 const MCSubtargetInfo &STI; 36 MCContext &Ctx; 37 public: 38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 39 MCContext &ctx) 40 : MCII(mcii), STI(sti), Ctx(ctx) { 41 } 42 43 ~X86MCCodeEmitter() {} 44 45 bool is64BitMode() const { 46 // FIXME: Can tablegen auto-generate this? 47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 48 } 49 50 bool is32BitMode() const { 51 // FIXME: Can tablegen auto-generate this? 52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0; 53 } 54 55 unsigned GetX86RegNum(const MCOperand &MO) const { 56 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7; 57 } 58 59 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 60 // 0-7 and the difference between the 2 groups is given by the REX prefix. 61 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 62 // in 1's complement form, example: 63 // 64 // ModRM field => XMM9 => 1 65 // VEX.VVVV => XMM9 => ~9 66 // 67 // See table 4-35 of Intel AVX Programming Reference for details. 68 unsigned char getVEXRegisterEncoding(const MCInst &MI, 69 unsigned OpNum) const { 70 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 71 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 72 if (X86II::isX86_64ExtendedReg(SrcReg)) 73 SrcRegNum |= 8; 74 75 // The registers represented through VEX_VVVV should 76 // be encoded in 1's complement form. 77 return (~SrcRegNum) & 0xf; 78 } 79 80 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 81 OS << (char)C; 82 ++CurByte; 83 } 84 85 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 86 raw_ostream &OS) const { 87 // Output the constant in little endian byte order. 88 for (unsigned i = 0; i != Size; ++i) { 89 EmitByte(Val & 255, CurByte, OS); 90 Val >>= 8; 91 } 92 } 93 94 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 95 unsigned ImmSize, MCFixupKind FixupKind, 96 unsigned &CurByte, raw_ostream &OS, 97 SmallVectorImpl<MCFixup> &Fixups, 98 int ImmOffset = 0) const; 99 100 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 101 unsigned RM) { 102 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 103 return RM | (RegOpcode << 3) | (Mod << 6); 104 } 105 106 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 107 unsigned &CurByte, raw_ostream &OS) const { 108 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 109 } 110 111 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 112 unsigned &CurByte, raw_ostream &OS) const { 113 // SIB byte is in the same format as the ModRMByte. 114 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 115 } 116 117 118 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 119 unsigned RegOpcodeField, 120 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 121 SmallVectorImpl<MCFixup> &Fixups) const; 122 123 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 124 SmallVectorImpl<MCFixup> &Fixups) const; 125 126 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 127 const MCInst &MI, const MCInstrDesc &Desc, 128 raw_ostream &OS) const; 129 130 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, 131 int MemOperand, const MCInst &MI, 132 raw_ostream &OS) const; 133 134 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 135 const MCInst &MI, const MCInstrDesc &Desc, 136 raw_ostream &OS) const; 137 }; 138 139 } // end anonymous namespace 140 141 142 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 143 const MCRegisterInfo &MRI, 144 const MCSubtargetInfo &STI, 145 MCContext &Ctx) { 146 return new X86MCCodeEmitter(MCII, STI, Ctx); 147 } 148 149 /// isDisp8 - Return true if this signed displacement fits in a 8-bit 150 /// sign-extended field. 151 static bool isDisp8(int Value) { 152 return Value == (signed char)Value; 153 } 154 155 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 156 /// in an instruction with the specified TSFlags. 157 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 158 unsigned Size = X86II::getSizeOfImm(TSFlags); 159 bool isPCRel = X86II::isImmPCRel(TSFlags); 160 161 return MCFixup::getKindForSize(Size, isPCRel); 162 } 163 164 /// Is32BitMemOperand - Return true if the specified instruction has 165 /// a 32-bit memory operand. Op specifies the operand # of the memoperand. 166 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 168 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 169 170 if ((BaseReg.getReg() != 0 && 171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 172 (IndexReg.getReg() != 0 && 173 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 174 return true; 175 return false; 176 } 177 178 /// Is64BitMemOperand - Return true if the specified instruction has 179 /// a 64-bit memory operand. Op specifies the operand # of the memoperand. 180 #ifndef NDEBUG 181 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 183 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 184 185 if ((BaseReg.getReg() != 0 && 186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 187 (IndexReg.getReg() != 0 && 188 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 189 return true; 190 return false; 191 } 192 #endif 193 194 /// Is16BitMemOperand - Return true if the specified instruction has 195 /// a 16-bit memory operand. Op specifies the operand # of the memoperand. 196 static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) { 197 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 198 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 199 200 if ((BaseReg.getReg() != 0 && 201 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 202 (IndexReg.getReg() != 0 && 203 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 204 return true; 205 return false; 206 } 207 208 /// StartsWithGlobalOffsetTable - Check if this expression starts with 209 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form 210 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 211 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 212 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 213 /// of a binary expression. 214 enum GlobalOffsetTableExprKind { 215 GOT_None, 216 GOT_Normal, 217 GOT_SymDiff 218 }; 219 static GlobalOffsetTableExprKind 220 StartsWithGlobalOffsetTable(const MCExpr *Expr) { 221 const MCExpr *RHS = 0; 222 if (Expr->getKind() == MCExpr::Binary) { 223 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 224 Expr = BE->getLHS(); 225 RHS = BE->getRHS(); 226 } 227 228 if (Expr->getKind() != MCExpr::SymbolRef) 229 return GOT_None; 230 231 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 232 const MCSymbol &S = Ref->getSymbol(); 233 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 234 return GOT_None; 235 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 236 return GOT_SymDiff; 237 return GOT_Normal; 238 } 239 240 void X86MCCodeEmitter:: 241 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 242 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 243 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 244 const MCExpr *Expr = NULL; 245 if (DispOp.isImm()) { 246 // If this is a simple integer displacement that doesn't require a 247 // relocation, emit it now. 248 if (FixupKind != FK_PCRel_1 && 249 FixupKind != FK_PCRel_2 && 250 FixupKind != FK_PCRel_4) { 251 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 252 return; 253 } 254 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); 255 } else { 256 Expr = DispOp.getExpr(); 257 } 258 259 // If we have an immoffset, add it to the expression. 260 if ((FixupKind == FK_Data_4 || 261 FixupKind == FK_Data_8 || 262 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 263 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 264 if (Kind != GOT_None) { 265 assert(ImmOffset == 0); 266 267 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 268 if (Kind == GOT_Normal) 269 ImmOffset = CurByte; 270 } else if (Expr->getKind() == MCExpr::SymbolRef) { 271 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 272 if (Ref->getKind() == MCSymbolRefExpr::VK_SECREL) { 273 FixupKind = MCFixupKind(FK_SecRel_4); 274 } 275 } 276 } 277 278 // If the fixup is pc-relative, we need to bias the value to be relative to 279 // the start of the field, not the end of the field. 280 if (FixupKind == FK_PCRel_4 || 281 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 282 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 283 ImmOffset -= 4; 284 if (FixupKind == FK_PCRel_2) 285 ImmOffset -= 2; 286 if (FixupKind == FK_PCRel_1) 287 ImmOffset -= 1; 288 289 if (ImmOffset) 290 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), 291 Ctx); 292 293 // Emit a symbolic constant as a fixup and 4 zeros. 294 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc)); 295 EmitConstant(0, Size, CurByte, OS); 296 } 297 298 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 299 unsigned RegOpcodeField, 300 uint64_t TSFlags, unsigned &CurByte, 301 raw_ostream &OS, 302 SmallVectorImpl<MCFixup> &Fixups) const{ 303 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 304 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 305 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 306 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 307 unsigned BaseReg = Base.getReg(); 308 309 // Handle %rip relative addressing. 310 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 311 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); 312 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 313 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 314 315 unsigned FixupKind = X86::reloc_riprel_4byte; 316 317 // movq loads are handled with a special relocation form which allows the 318 // linker to eliminate some loads for GOT references which end up in the 319 // same linkage unit. 320 if (MI.getOpcode() == X86::MOV64rm) 321 FixupKind = X86::reloc_riprel_4byte_movq_load; 322 323 // rip-relative addressing is actually relative to the *next* instruction. 324 // Since an immediate can follow the mod/rm byte for an instruction, this 325 // means that we need to bias the immediate field of the instruction with 326 // the size of the immediate field. If we have this case, add it into the 327 // expression to emit. 328 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 329 330 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 331 CurByte, OS, Fixups, -ImmSize); 332 return; 333 } 334 335 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 336 337 // Determine whether a SIB byte is needed. 338 // If no BaseReg, issue a RIP relative instruction only if the MCE can 339 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 340 // 2-7) and absolute references. 341 342 if (// The SIB byte must be used if there is an index register. 343 IndexReg.getReg() == 0 && 344 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 345 // encode to an R/M value of 4, which indicates that a SIB byte is 346 // present. 347 BaseRegNo != N86::ESP && 348 // If there is no base register and we're in 64-bit mode, we need a SIB 349 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 350 (!is64BitMode() || BaseReg != 0)) { 351 352 if (BaseReg == 0) { // [disp32] in X86-32 mode 353 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 354 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 355 return; 356 } 357 358 // If the base is not EBP/ESP and there is no displacement, use simple 359 // indirect register encoding, this handles addresses like [EAX]. The 360 // encoding for [EBP] with no displacement means [disp32] so we handle it 361 // by emitting a displacement of 0 below. 362 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 363 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 364 return; 365 } 366 367 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 368 if (Disp.isImm() && isDisp8(Disp.getImm())) { 369 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 370 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 371 return; 372 } 373 374 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 375 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 376 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, 377 Fixups); 378 return; 379 } 380 381 // We need a SIB byte, so start by outputting the ModR/M byte first 382 assert(IndexReg.getReg() != X86::ESP && 383 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 384 385 bool ForceDisp32 = false; 386 bool ForceDisp8 = false; 387 if (BaseReg == 0) { 388 // If there is no base register, we emit the special case SIB byte with 389 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 390 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 391 ForceDisp32 = true; 392 } else if (!Disp.isImm()) { 393 // Emit the normal disp32 encoding. 394 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 395 ForceDisp32 = true; 396 } else if (Disp.getImm() == 0 && 397 // Base reg can't be anything that ends up with '5' as the base 398 // reg, it is the magic [*] nomenclature that indicates no base. 399 BaseRegNo != N86::EBP) { 400 // Emit no displacement ModR/M byte 401 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 402 } else if (isDisp8(Disp.getImm())) { 403 // Emit the disp8 encoding. 404 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 405 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 406 } else { 407 // Emit the normal disp32 encoding. 408 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 409 } 410 411 // Calculate what the SS field value should be... 412 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 413 unsigned SS = SSTable[Scale.getImm()]; 414 415 if (BaseReg == 0) { 416 // Handle the SIB byte for the case where there is no base, see Intel 417 // Manual 2A, table 2-7. The displacement has already been output. 418 unsigned IndexRegNo; 419 if (IndexReg.getReg()) 420 IndexRegNo = GetX86RegNum(IndexReg); 421 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 422 IndexRegNo = 4; 423 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 424 } else { 425 unsigned IndexRegNo; 426 if (IndexReg.getReg()) 427 IndexRegNo = GetX86RegNum(IndexReg); 428 else 429 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 430 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 431 } 432 433 // Do we need to output a displacement? 434 if (ForceDisp8) 435 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 436 else if (ForceDisp32 || Disp.getImm() != 0) 437 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 438 CurByte, OS, Fixups); 439 } 440 441 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 442 /// called VEX. 443 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 444 int MemOperand, const MCInst &MI, 445 const MCInstrDesc &Desc, 446 raw_ostream &OS) const { 447 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 448 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 449 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 450 451 // VEX_R: opcode externsion equivalent to REX.R in 452 // 1's complement (inverted) form 453 // 454 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 455 // 0: Same as REX_R=1 (64 bit mode only) 456 // 457 unsigned char VEX_R = 0x1; 458 459 // VEX_X: equivalent to REX.X, only used when a 460 // register is used for index in SIB Byte. 461 // 462 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 463 // 0: Same as REX.X=1 (64-bit mode only) 464 unsigned char VEX_X = 0x1; 465 466 // VEX_B: 467 // 468 // 1: Same as REX_B=0 (ignored in 32-bit mode) 469 // 0: Same as REX_B=1 (64 bit mode only) 470 // 471 unsigned char VEX_B = 0x1; 472 473 // VEX_W: opcode specific (use like REX.W, or used for 474 // opcode extension, or ignored, depending on the opcode byte) 475 unsigned char VEX_W = 0; 476 477 // XOP: Use XOP prefix byte 0x8f instead of VEX. 478 unsigned char XOP = 0; 479 480 // VEX_5M (VEX m-mmmmm field): 481 // 482 // 0b00000: Reserved for future use 483 // 0b00001: implied 0F leading opcode 484 // 0b00010: implied 0F 38 leading opcode bytes 485 // 0b00011: implied 0F 3A leading opcode bytes 486 // 0b00100-0b11111: Reserved for future use 487 // 0b01000: XOP map select - 08h instructions with imm byte 488 // 0b10001: XOP map select - 09h instructions with no imm byte 489 unsigned char VEX_5M = 0x1; 490 491 // VEX_4V (VEX vvvv field): a register specifier 492 // (in 1's complement form) or 1111 if unused. 493 unsigned char VEX_4V = 0xf; 494 495 // VEX_L (Vector Length): 496 // 497 // 0: scalar or 128-bit vector 498 // 1: 256-bit vector 499 // 500 unsigned char VEX_L = 0; 501 502 // VEX_PP: opcode extension providing equivalent 503 // functionality of a SIMD prefix 504 // 505 // 0b00: None 506 // 0b01: 66 507 // 0b10: F3 508 // 0b11: F2 509 // 510 unsigned char VEX_PP = 0; 511 512 // Encode the operand size opcode prefix as needed. 513 if (TSFlags & X86II::OpSize) 514 VEX_PP = 0x01; 515 516 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 517 VEX_W = 1; 518 519 if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 520 XOP = 1; 521 522 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 523 VEX_L = 1; 524 525 switch (TSFlags & X86II::Op0Mask) { 526 default: llvm_unreachable("Invalid prefix!"); 527 case X86II::T8: // 0F 38 528 VEX_5M = 0x2; 529 break; 530 case X86II::TA: // 0F 3A 531 VEX_5M = 0x3; 532 break; 533 case X86II::T8XS: // F3 0F 38 534 VEX_PP = 0x2; 535 VEX_5M = 0x2; 536 break; 537 case X86II::T8XD: // F2 0F 38 538 VEX_PP = 0x3; 539 VEX_5M = 0x2; 540 break; 541 case X86II::TAXD: // F2 0F 3A 542 VEX_PP = 0x3; 543 VEX_5M = 0x3; 544 break; 545 case X86II::XS: // F3 0F 546 VEX_PP = 0x2; 547 break; 548 case X86II::XD: // F2 0F 549 VEX_PP = 0x3; 550 break; 551 case X86II::XOP8: 552 VEX_5M = 0x8; 553 break; 554 case X86II::XOP9: 555 VEX_5M = 0x9; 556 break; 557 case X86II::A6: // Bypass: Not used by VEX 558 case X86II::A7: // Bypass: Not used by VEX 559 case X86II::TB: // Bypass: Not used by VEX 560 case 0: 561 break; // No prefix! 562 } 563 564 565 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 566 unsigned NumOps = Desc.getNumOperands(); 567 unsigned CurOp = 0; 568 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 569 ++CurOp; 570 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) { 571 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 572 // Special case for GATHER with 2 TIED_TO operands 573 // Skip the first 2 operands: dst, mask_wb 574 CurOp += 2; 575 } 576 577 switch (TSFlags & X86II::FormMask) { 578 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 579 case X86II::MRMDestMem: { 580 // MRMDestMem instructions forms: 581 // MemAddr, src1(ModR/M) 582 // MemAddr, src1(VEX_4V), src2(ModR/M) 583 // MemAddr, src1(ModR/M), imm8 584 // 585 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg())) 586 VEX_B = 0x0; 587 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) 588 VEX_X = 0x0; 589 590 CurOp = X86::AddrNumOperands; 591 if (HasVEX_4V) 592 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 593 594 const MCOperand &MO = MI.getOperand(CurOp); 595 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 596 VEX_R = 0x0; 597 break; 598 } 599 case X86II::MRMSrcMem: 600 // MRMSrcMem instructions forms: 601 // src1(ModR/M), MemAddr 602 // src1(ModR/M), src2(VEX_4V), MemAddr 603 // src1(ModR/M), MemAddr, imm8 604 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 605 // 606 // FMA4: 607 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 608 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 609 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp++).getReg())) 610 VEX_R = 0x0; 611 612 if (HasVEX_4V) 613 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 614 615 if (X86II::isX86_64ExtendedReg( 616 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 617 VEX_B = 0x0; 618 if (X86II::isX86_64ExtendedReg( 619 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 620 VEX_X = 0x0; 621 622 if (HasVEX_4VOp3) 623 // Instruction format for 4VOp3: 624 // src1(ModR/M), MemAddr, src3(VEX_4V) 625 // CurOp points to start of the MemoryOperand, 626 // it skips TIED_TO operands if exist, then increments past src1. 627 // CurOp + X86::AddrNumOperands will point to src3. 628 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); 629 break; 630 case X86II::MRM0m: case X86II::MRM1m: 631 case X86II::MRM2m: case X86II::MRM3m: 632 case X86II::MRM4m: case X86II::MRM5m: 633 case X86II::MRM6m: case X86II::MRM7m: { 634 // MRM[0-9]m instructions forms: 635 // MemAddr 636 // src1(VEX_4V), MemAddr 637 if (HasVEX_4V) 638 VEX_4V = getVEXRegisterEncoding(MI, 0); 639 640 if (X86II::isX86_64ExtendedReg( 641 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 642 VEX_B = 0x0; 643 if (X86II::isX86_64ExtendedReg( 644 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 645 VEX_X = 0x0; 646 break; 647 } 648 case X86II::MRMSrcReg: 649 // MRMSrcReg instructions forms: 650 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 651 // dst(ModR/M), src1(ModR/M) 652 // dst(ModR/M), src1(ModR/M), imm8 653 // 654 // FMA4: 655 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 656 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 657 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 658 VEX_R = 0x0; 659 CurOp++; 660 661 if (HasVEX_4V) 662 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 663 664 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 665 CurOp++; 666 667 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 668 VEX_B = 0x0; 669 CurOp++; 670 if (HasVEX_4VOp3) 671 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 672 break; 673 case X86II::MRMDestReg: 674 // MRMDestReg instructions forms: 675 // dst(ModR/M), src(ModR/M) 676 // dst(ModR/M), src(ModR/M), imm8 677 // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 678 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 679 VEX_B = 0x0; 680 CurOp++; 681 682 if (HasVEX_4V) 683 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 684 685 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 686 VEX_R = 0x0; 687 break; 688 case X86II::MRM0r: case X86II::MRM1r: 689 case X86II::MRM2r: case X86II::MRM3r: 690 case X86II::MRM4r: case X86II::MRM5r: 691 case X86II::MRM6r: case X86II::MRM7r: 692 // MRM0r-MRM7r instructions forms: 693 // dst(VEX_4V), src(ModR/M), imm8 694 VEX_4V = getVEXRegisterEncoding(MI, 0); 695 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 696 VEX_B = 0x0; 697 break; 698 default: // RawFrm 699 break; 700 } 701 702 // Emit segment override opcode prefix as needed. 703 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 704 705 // VEX opcode prefix can have 2 or 3 bytes 706 // 707 // 3 bytes: 708 // +-----+ +--------------+ +-------------------+ 709 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 710 // +-----+ +--------------+ +-------------------+ 711 // 2 bytes: 712 // +-----+ +-------------------+ 713 // | C5h | | R | vvvv | L | pp | 714 // +-----+ +-------------------+ 715 // 716 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 717 718 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 719 EmitByte(0xC5, CurByte, OS); 720 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 721 return; 722 } 723 724 // 3 byte VEX prefix 725 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS); 726 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 727 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 728 } 729 730 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 731 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 732 /// size, and 3) use of X86-64 extended registers. 733 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 734 const MCInstrDesc &Desc) { 735 unsigned REX = 0; 736 if (TSFlags & X86II::REX_W) 737 REX |= 1 << 3; // set REX.W 738 739 if (MI.getNumOperands() == 0) return REX; 740 741 unsigned NumOps = MI.getNumOperands(); 742 // FIXME: MCInst should explicitize the two-addrness. 743 bool isTwoAddr = NumOps > 1 && 744 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 745 746 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 747 unsigned i = isTwoAddr ? 1 : 0; 748 for (; i != NumOps; ++i) { 749 const MCOperand &MO = MI.getOperand(i); 750 if (!MO.isReg()) continue; 751 unsigned Reg = MO.getReg(); 752 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 753 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 754 // that returns non-zero. 755 REX |= 0x40; // REX fixed encoding prefix 756 break; 757 } 758 759 switch (TSFlags & X86II::FormMask) { 760 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 761 case X86II::MRMSrcReg: 762 if (MI.getOperand(0).isReg() && 763 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 764 REX |= 1 << 2; // set REX.R 765 i = isTwoAddr ? 2 : 1; 766 for (; i != NumOps; ++i) { 767 const MCOperand &MO = MI.getOperand(i); 768 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 769 REX |= 1 << 0; // set REX.B 770 } 771 break; 772 case X86II::MRMSrcMem: { 773 if (MI.getOperand(0).isReg() && 774 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 775 REX |= 1 << 2; // set REX.R 776 unsigned Bit = 0; 777 i = isTwoAddr ? 2 : 1; 778 for (; i != NumOps; ++i) { 779 const MCOperand &MO = MI.getOperand(i); 780 if (MO.isReg()) { 781 if (X86II::isX86_64ExtendedReg(MO.getReg())) 782 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 783 Bit++; 784 } 785 } 786 break; 787 } 788 case X86II::MRM0m: case X86II::MRM1m: 789 case X86II::MRM2m: case X86II::MRM3m: 790 case X86II::MRM4m: case X86II::MRM5m: 791 case X86II::MRM6m: case X86II::MRM7m: 792 case X86II::MRMDestMem: { 793 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 794 i = isTwoAddr ? 1 : 0; 795 if (NumOps > e && MI.getOperand(e).isReg() && 796 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 797 REX |= 1 << 2; // set REX.R 798 unsigned Bit = 0; 799 for (; i != e; ++i) { 800 const MCOperand &MO = MI.getOperand(i); 801 if (MO.isReg()) { 802 if (X86II::isX86_64ExtendedReg(MO.getReg())) 803 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 804 Bit++; 805 } 806 } 807 break; 808 } 809 default: 810 if (MI.getOperand(0).isReg() && 811 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 812 REX |= 1 << 0; // set REX.B 813 i = isTwoAddr ? 2 : 1; 814 for (unsigned e = NumOps; i != e; ++i) { 815 const MCOperand &MO = MI.getOperand(i); 816 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 817 REX |= 1 << 2; // set REX.R 818 } 819 break; 820 } 821 return REX; 822 } 823 824 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 825 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, 826 unsigned &CurByte, int MemOperand, 827 const MCInst &MI, 828 raw_ostream &OS) const { 829 switch (TSFlags & X86II::SegOvrMask) { 830 default: llvm_unreachable("Invalid segment!"); 831 case 0: 832 // No segment override, check for explicit one on memory operand. 833 if (MemOperand != -1) { // If the instruction has a memory operand. 834 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 835 default: llvm_unreachable("Unknown segment register!"); 836 case 0: break; 837 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 838 case X86::SS: EmitByte(0x36, CurByte, OS); break; 839 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 840 case X86::ES: EmitByte(0x26, CurByte, OS); break; 841 case X86::FS: EmitByte(0x64, CurByte, OS); break; 842 case X86::GS: EmitByte(0x65, CurByte, OS); break; 843 } 844 } 845 break; 846 case X86II::FS: 847 EmitByte(0x64, CurByte, OS); 848 break; 849 case X86II::GS: 850 EmitByte(0x65, CurByte, OS); 851 break; 852 } 853 } 854 855 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 856 /// 857 /// MemOperand is the operand # of the start of a memory operand if present. If 858 /// Not present, it is -1. 859 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 860 int MemOperand, const MCInst &MI, 861 const MCInstrDesc &Desc, 862 raw_ostream &OS) const { 863 864 // Emit the lock opcode prefix as needed. 865 if (TSFlags & X86II::LOCK) 866 EmitByte(0xF0, CurByte, OS); 867 868 // Emit segment override opcode prefix as needed. 869 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 870 871 // Emit the repeat opcode prefix as needed. 872 if ((TSFlags & X86II::Op0Mask) == X86II::REP) 873 EmitByte(0xF3, CurByte, OS); 874 875 // Emit the address size opcode prefix as needed. 876 bool need_address_override; 877 if (TSFlags & X86II::AdSize) { 878 need_address_override = true; 879 } else if (MemOperand == -1) { 880 need_address_override = false; 881 } else if (is64BitMode()) { 882 assert(!Is16BitMemOperand(MI, MemOperand)); 883 need_address_override = Is32BitMemOperand(MI, MemOperand); 884 } else if (is32BitMode()) { 885 assert(!Is64BitMemOperand(MI, MemOperand)); 886 need_address_override = Is16BitMemOperand(MI, MemOperand); 887 } else { 888 need_address_override = false; 889 } 890 891 if (need_address_override) 892 EmitByte(0x67, CurByte, OS); 893 894 // Emit the operand size opcode prefix as needed. 895 if (TSFlags & X86II::OpSize) 896 EmitByte(0x66, CurByte, OS); 897 898 bool Need0FPrefix = false; 899 switch (TSFlags & X86II::Op0Mask) { 900 default: llvm_unreachable("Invalid prefix!"); 901 case 0: break; // No prefix! 902 case X86II::REP: break; // already handled. 903 case X86II::TB: // Two-byte opcode prefix 904 case X86II::T8: // 0F 38 905 case X86II::TA: // 0F 3A 906 case X86II::A6: // 0F A6 907 case X86II::A7: // 0F A7 908 Need0FPrefix = true; 909 break; 910 case X86II::T8XS: // F3 0F 38 911 EmitByte(0xF3, CurByte, OS); 912 Need0FPrefix = true; 913 break; 914 case X86II::T8XD: // F2 0F 38 915 EmitByte(0xF2, CurByte, OS); 916 Need0FPrefix = true; 917 break; 918 case X86II::TAXD: // F2 0F 3A 919 EmitByte(0xF2, CurByte, OS); 920 Need0FPrefix = true; 921 break; 922 case X86II::XS: // F3 0F 923 EmitByte(0xF3, CurByte, OS); 924 Need0FPrefix = true; 925 break; 926 case X86II::XD: // F2 0F 927 EmitByte(0xF2, CurByte, OS); 928 Need0FPrefix = true; 929 break; 930 case X86II::D8: EmitByte(0xD8, CurByte, OS); break; 931 case X86II::D9: EmitByte(0xD9, CurByte, OS); break; 932 case X86II::DA: EmitByte(0xDA, CurByte, OS); break; 933 case X86II::DB: EmitByte(0xDB, CurByte, OS); break; 934 case X86II::DC: EmitByte(0xDC, CurByte, OS); break; 935 case X86II::DD: EmitByte(0xDD, CurByte, OS); break; 936 case X86II::DE: EmitByte(0xDE, CurByte, OS); break; 937 case X86II::DF: EmitByte(0xDF, CurByte, OS); break; 938 } 939 940 // Handle REX prefix. 941 // FIXME: Can this come before F2 etc to simplify emission? 942 if (is64BitMode()) { 943 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 944 EmitByte(0x40 | REX, CurByte, OS); 945 } 946 947 // 0x0F escape code must be emitted just before the opcode. 948 if (Need0FPrefix) 949 EmitByte(0x0F, CurByte, OS); 950 951 // FIXME: Pull this up into previous switch if REX can be moved earlier. 952 switch (TSFlags & X86II::Op0Mask) { 953 case X86II::T8XS: // F3 0F 38 954 case X86II::T8XD: // F2 0F 38 955 case X86II::T8: // 0F 38 956 EmitByte(0x38, CurByte, OS); 957 break; 958 case X86II::TAXD: // F2 0F 3A 959 case X86II::TA: // 0F 3A 960 EmitByte(0x3A, CurByte, OS); 961 break; 962 case X86II::A6: // 0F A6 963 EmitByte(0xA6, CurByte, OS); 964 break; 965 case X86II::A7: // 0F A7 966 EmitByte(0xA7, CurByte, OS); 967 break; 968 } 969 } 970 971 void X86MCCodeEmitter:: 972 EncodeInstruction(const MCInst &MI, raw_ostream &OS, 973 SmallVectorImpl<MCFixup> &Fixups) const { 974 unsigned Opcode = MI.getOpcode(); 975 const MCInstrDesc &Desc = MCII.get(Opcode); 976 uint64_t TSFlags = Desc.TSFlags; 977 978 // Pseudo instructions don't get encoded. 979 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 980 return; 981 982 // If this is a two-address instruction, skip one of the register operands. 983 // FIXME: This should be handled during MCInst lowering. 984 unsigned NumOps = Desc.getNumOperands(); 985 unsigned CurOp = 0; 986 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 987 ++CurOp; 988 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) { 989 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 990 // Special case for GATHER with 2 TIED_TO operands 991 // Skip the first 2 operands: dst, mask_wb 992 CurOp += 2; 993 } 994 995 // Keep track of the current byte being emitted. 996 unsigned CurByte = 0; 997 998 // Is this instruction encoded using the AVX VEX prefix? 999 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 1000 1001 // It uses the VEX.VVVV field? 1002 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 1003 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 1004 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 1005 const unsigned MemOp4_I8IMMOperand = 2; 1006 1007 // Determine where the memory operand starts, if present. 1008 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1009 if (MemoryOperand != -1) MemoryOperand += CurOp; 1010 1011 if (!HasVEXPrefix) 1012 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1013 else 1014 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1015 1016 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1017 1018 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1019 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1020 1021 unsigned SrcRegNum = 0; 1022 switch (TSFlags & X86II::FormMask) { 1023 case X86II::MRMInitReg: 1024 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!"); 1025 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 1026 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1027 case X86II::Pseudo: 1028 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1029 case X86II::RawFrm: 1030 EmitByte(BaseOpcode, CurByte, OS); 1031 break; 1032 case X86II::RawFrmImm8: 1033 EmitByte(BaseOpcode, CurByte, OS); 1034 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1035 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1036 CurByte, OS, Fixups); 1037 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1038 OS, Fixups); 1039 break; 1040 case X86II::RawFrmImm16: 1041 EmitByte(BaseOpcode, CurByte, OS); 1042 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1043 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1044 CurByte, OS, Fixups); 1045 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1046 OS, Fixups); 1047 break; 1048 1049 case X86II::AddRegFrm: 1050 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1051 break; 1052 1053 case X86II::MRMDestReg: 1054 EmitByte(BaseOpcode, CurByte, OS); 1055 SrcRegNum = CurOp + 1; 1056 1057 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1058 ++SrcRegNum; 1059 1060 EmitRegModRMByte(MI.getOperand(CurOp), 1061 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1062 CurOp = SrcRegNum + 1; 1063 break; 1064 1065 case X86II::MRMDestMem: 1066 EmitByte(BaseOpcode, CurByte, OS); 1067 SrcRegNum = CurOp + X86::AddrNumOperands; 1068 1069 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1070 ++SrcRegNum; 1071 1072 EmitMemModRMByte(MI, CurOp, 1073 GetX86RegNum(MI.getOperand(SrcRegNum)), 1074 TSFlags, CurByte, OS, Fixups); 1075 CurOp = SrcRegNum + 1; 1076 break; 1077 1078 case X86II::MRMSrcReg: 1079 EmitByte(BaseOpcode, CurByte, OS); 1080 SrcRegNum = CurOp + 1; 1081 1082 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1083 ++SrcRegNum; 1084 1085 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1086 ++SrcRegNum; 1087 1088 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1089 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1090 1091 // 2 operands skipped with HasMemOp4, compensate accordingly 1092 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1093 if (HasVEX_4VOp3) 1094 ++CurOp; 1095 break; 1096 1097 case X86II::MRMSrcMem: { 1098 int AddrOperands = X86::AddrNumOperands; 1099 unsigned FirstMemOp = CurOp+1; 1100 if (HasVEX_4V) { 1101 ++AddrOperands; 1102 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1103 } 1104 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1105 ++FirstMemOp; 1106 1107 EmitByte(BaseOpcode, CurByte, OS); 1108 1109 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1110 TSFlags, CurByte, OS, Fixups); 1111 CurOp += AddrOperands + 1; 1112 if (HasVEX_4VOp3) 1113 ++CurOp; 1114 break; 1115 } 1116 1117 case X86II::MRM0r: case X86II::MRM1r: 1118 case X86II::MRM2r: case X86II::MRM3r: 1119 case X86II::MRM4r: case X86II::MRM5r: 1120 case X86II::MRM6r: case X86II::MRM7r: 1121 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1122 ++CurOp; 1123 EmitByte(BaseOpcode, CurByte, OS); 1124 EmitRegModRMByte(MI.getOperand(CurOp++), 1125 (TSFlags & X86II::FormMask)-X86II::MRM0r, 1126 CurByte, OS); 1127 break; 1128 case X86II::MRM0m: case X86II::MRM1m: 1129 case X86II::MRM2m: case X86II::MRM3m: 1130 case X86II::MRM4m: case X86II::MRM5m: 1131 case X86II::MRM6m: case X86II::MRM7m: 1132 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1133 ++CurOp; 1134 EmitByte(BaseOpcode, CurByte, OS); 1135 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m, 1136 TSFlags, CurByte, OS, Fixups); 1137 CurOp += X86::AddrNumOperands; 1138 break; 1139 case X86II::MRM_C1: case X86II::MRM_C2: 1140 case X86II::MRM_C3: case X86II::MRM_C4: 1141 case X86II::MRM_C8: case X86II::MRM_C9: 1142 case X86II::MRM_D0: case X86II::MRM_D1: 1143 case X86II::MRM_D4: case X86II::MRM_D5: 1144 case X86II::MRM_D8: case X86II::MRM_D9: 1145 case X86II::MRM_DA: case X86II::MRM_DB: 1146 case X86II::MRM_DC: case X86II::MRM_DD: 1147 case X86II::MRM_DE: case X86II::MRM_DF: 1148 case X86II::MRM_E8: case X86II::MRM_F0: 1149 case X86II::MRM_F8: case X86II::MRM_F9: 1150 EmitByte(BaseOpcode, CurByte, OS); 1151 1152 unsigned char MRM; 1153 switch (TSFlags & X86II::FormMask) { 1154 default: llvm_unreachable("Invalid Form"); 1155 case X86II::MRM_C1: MRM = 0xC1; break; 1156 case X86II::MRM_C2: MRM = 0xC2; break; 1157 case X86II::MRM_C3: MRM = 0xC3; break; 1158 case X86II::MRM_C4: MRM = 0xC4; break; 1159 case X86II::MRM_C8: MRM = 0xC8; break; 1160 case X86II::MRM_C9: MRM = 0xC9; break; 1161 case X86II::MRM_D0: MRM = 0xD0; break; 1162 case X86II::MRM_D1: MRM = 0xD1; break; 1163 case X86II::MRM_D4: MRM = 0xD4; break; 1164 case X86II::MRM_D5: MRM = 0xD5; break; 1165 case X86II::MRM_D8: MRM = 0xD8; break; 1166 case X86II::MRM_D9: MRM = 0xD9; break; 1167 case X86II::MRM_DA: MRM = 0xDA; break; 1168 case X86II::MRM_DB: MRM = 0xDB; break; 1169 case X86II::MRM_DC: MRM = 0xDC; break; 1170 case X86II::MRM_DD: MRM = 0xDD; break; 1171 case X86II::MRM_DE: MRM = 0xDE; break; 1172 case X86II::MRM_DF: MRM = 0xDF; break; 1173 case X86II::MRM_E8: MRM = 0xE8; break; 1174 case X86II::MRM_F0: MRM = 0xF0; break; 1175 case X86II::MRM_F8: MRM = 0xF8; break; 1176 case X86II::MRM_F9: MRM = 0xF9; break; 1177 } 1178 EmitByte(MRM, CurByte, OS); 1179 break; 1180 } 1181 1182 // If there is a remaining operand, it must be a trailing immediate. Emit it 1183 // according to the right size for the instruction. Some instructions 1184 // (SSE4a extrq and insertq) have two trailing immediates. 1185 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1186 // The last source register of a 4 operand instruction in AVX is encoded 1187 // in bits[7:4] of a immediate byte. 1188 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1189 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1190 : CurOp); 1191 ++CurOp; 1192 unsigned RegNum = GetX86RegNum(MO) << 4; 1193 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1194 RegNum |= 1 << 7; 1195 // If there is an additional 5th operand it must be an immediate, which 1196 // is encoded in bits[3:0] 1197 if (CurOp != NumOps) { 1198 const MCOperand &MIMM = MI.getOperand(CurOp++); 1199 if (MIMM.isImm()) { 1200 unsigned Val = MIMM.getImm(); 1201 assert(Val < 16 && "Immediate operand value out of range"); 1202 RegNum |= Val; 1203 } 1204 } 1205 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1206 CurByte, OS, Fixups); 1207 } else { 1208 unsigned FixupKind; 1209 // FIXME: Is there a better way to know that we need a signed relocation? 1210 if (MI.getOpcode() == X86::ADD64ri32 || 1211 MI.getOpcode() == X86::MOV64ri32 || 1212 MI.getOpcode() == X86::MOV64mi32 || 1213 MI.getOpcode() == X86::PUSH64i32) 1214 FixupKind = X86::reloc_signed_4byte; 1215 else 1216 FixupKind = getImmFixupKind(TSFlags); 1217 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1218 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind), 1219 CurByte, OS, Fixups); 1220 } 1221 } 1222 1223 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1224 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1225 1226 #ifndef NDEBUG 1227 // FIXME: Verify. 1228 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1229 errs() << "Cannot encode all operands of: "; 1230 MI.dump(); 1231 errs() << '\n'; 1232 abort(); 1233 } 1234 #endif 1235 } 1236